[people/ms/u-boot.git] / include / configs / ts4800.h

/*
 * Copyright (C) 2015, Savoir-faire Linux Inc.
 *
 * Derived from MX51EVK code by
 *   Guennadi Liakhovetski <lg@denx.de>
 *   Freescale Semiconductor, Inc.
 *
 * Configuration settings for the TS4800 Board
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/* High Level Configuration Options */

#define CONFIG_SKIP_LOWLEVEL_INIT	/* U-Boot is a 2nd stage bootloader */

#define CONFIG_HW_WATCHDOG

#define CONFIG_MACH_TYPE	MACH_TYPE_TS48XX

/* text base address used when linking */

#include <asm/arch/imx-regs.h>

/* enable passing of ATAGs */
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
#define CONFIG_REVISION_TAG

/*
 * Size of malloc() pool
 */
#define CONFIG_SYS_MALLOC_LEN		(10 * 1024 * 1024)

/*
 * Hardware drivers
 */

#define CONFIG_MXC_UART
#define CONFIG_MXC_UART_BASE	UART1_BASE

/*
 * SPI Configs
 * */
#define CONFIG_HARD_SPI /* puts SPI: ready */
#define CONFIG_MXC_SPI /* driver for the SPI controllers*/

/*
 * MMC Configs
 * */
#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR	MMC_SDHC1_BASE_ADDR

/*
 * Eth Configs
 */
#define CONFIG_MII
#define CONFIG_PHY_SMSC

#define CONFIG_FEC_MXC
#define IMX_FEC_BASE	        FEC_BASE_ADDR
#define CONFIG_ETHPRIME		"FEC"
#define CONFIG_FEC_MXC_PHYADDR	0

/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE		/* disable vendor parameters protection (serial#, ethaddr) */
#define CONFIG_CONS_INDEX		1 /* use UART0 : used by serial driver */

/***********************************************************
 * Command definition
 ***********************************************************/

/* Environment variables */


#define CONFIG_LOADADDR		0x91000000	/* loadaddr env var */

#define CONFIG_EXTRA_ENV_SETTINGS \
	"script=boot.scr\0" \
	"image=zImage\0" \
	"fdt_file=imx51-ts4800.dtb\0" \
	"fdt_addr=0x90fe0000\0" \
	"mmcdev=0\0" \
	"mmcpart=2\0" \
	"mmcroot=/dev/mmcblk0p3 rootwait rw\0" \
	"mmcargs=setenv bootargs root=${mmcroot}\0" \
	"addtty=setenv bootargs ${bootargs} console=ttymxc0,${baudrate}\0" \
	"loadbootscript=" \
		"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
	"bootscript=echo Running bootscript from mmc ...; " \
		"source\0" \
	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image};\0" \
	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
	"mmcboot=echo Booting from mmc ...; " \
		"run mmcargs addtty; " \
		"if run loadfdt; then " \
			"bootz ${loadaddr} - ${fdt_addr}; " \
		"else " \
			"echo ERR: cannot load FDT; " \
		"fi; "


#define CONFIG_BOOTCOMMAND \
	"mmc dev ${mmcdev}; if mmc rescan; then " \
		"if run loadbootscript; then " \
			"run bootscript; " \
		"else " \
			"if run loadimage; then " \
				"run mmcboot; " \
			"fi; " \
		"fi; " \
	"fi; "

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP		/* undef to save memory */
#define CONFIG_AUTO_COMPLETE

#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR

#define CONFIG_CMDLINE_EDITING

/*-----------------------------------------------------------------------
 * Physical Memory Map
 */
#define CONFIG_NR_DRAM_BANKS	1
#define PHYS_SDRAM_1		CSD0_BASE_ADDR
#define PHYS_SDRAM_1_SIZE	(256 * 1024 * 1024)

#define CONFIG_SYS_SDRAM_BASE		(PHYS_SDRAM_1)
#define CONFIG_SYS_INIT_RAM_ADDR	(IRAM_BASE_ADDR)
#define CONFIG_SYS_INIT_RAM_SIZE	(IRAM_SIZE)

#define CONFIG_SYS_INIT_SP_OFFSET \
	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR \
	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)

/* Low level init */
#define CONFIG_SYS_DDR_CLKSEL	0
#define CONFIG_SYS_CLKTL_CBCDR	0x59E35100
#define CONFIG_SYS_MAIN_PWR_ON

/*-----------------------------------------------------------------------
 * Environment organization
 */

#define CONFIG_ENV_OFFSET      (6 * 64 * 1024)
#define CONFIG_ENV_SIZE        (8 * 1024)
#define CONFIG_SYS_MMC_ENV_DEV 0

#endif
Commit	Line	Data
9ee16897 LQ	1	/*
	2	* Copyright (C) 2015, Savoir-faire Linux Inc.
	3	*
	4	* Derived from MX51EVK code by
	5	* Guennadi Liakhovetski <lg@denx.de>
	6	* Freescale Semiconductor, Inc.
	7	*
	8	* Configuration settings for the TS4800 Board
	9	*
	10	* SPDX-License-Identifier: GPL-2.0+
	11	*/
	12
	13	#ifndef __CONFIG_H
	14	#define __CONFIG_H
	15
	16	/* High Level Configuration Options */
9ee16897	17
a187559e	18	#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is a 2nd stage bootloader */
9ee16897 LQ	19
	20	#define CONFIG_HW_WATCHDOG
	21
94ba26f2 TR	22	#define CONFIG_MACH_TYPE MACH_TYPE_TS48XX
94ba26f2 TR	23
9ee16897	24	/* text base address used when linking */
9ee16897 LQ	25
	26	#include <asm/arch/imx-regs.h>
	27
	28	/* enable passing of ATAGs */
	29	#define CONFIG_CMDLINE_TAG
	30	#define CONFIG_SETUP_MEMORY_TAGS
	31	#define CONFIG_INITRD_TAG
	32	#define CONFIG_REVISION_TAG
	33
9ee16897 LQ	34	/*
	35	* Size of malloc() pool
	36	*/
	37	#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
	38
	39	/*
	40	* Hardware drivers
	41	*/
	42
	43	#define CONFIG_MXC_UART
	44	#define CONFIG_MXC_UART_BASE UART1_BASE
9ee16897 LQ	45
	46	/*
	47	* SPI Configs
	48	* */
	49	#define CONFIG_HARD_SPI /* puts SPI: ready */
	50	#define CONFIG_MXC_SPI /* driver for the SPI controllers*/
9ee16897 LQ	51
	52	/*
	53	* MMC Configs
	54	* */
	55	#define CONFIG_FSL_ESDHC
	56	#define CONFIG_SYS_FSL_ESDHC_ADDR MMC_SDHC1_BASE_ADDR
	57
f3488bb3 DR	58	/*
	59	* Eth Configs
	60	*/
	61	#define CONFIG_MII
f3488bb3 DR	62	#define CONFIG_PHY_SMSC
	63
	64	#define CONFIG_FEC_MXC
	65	#define IMX_FEC_BASE FEC_BASE_ADDR
	66	#define CONFIG_ETHPRIME "FEC"
	67	#define CONFIG_FEC_MXC_PHYADDR 0
	68
9ee16897 LQ	69	/* allow to overwrite serial and ethaddr */
	70	#define CONFIG_ENV_OVERWRITE /* disable vendor parameters protection (serial#, ethaddr) */
	71	#define CONFIG_CONS_INDEX 1 /* use UART0 : used by serial driver */
9ee16897 LQ	72
	73	/***********************************************************
	74	* Command definition
	75	***********************************************************/
	76
9ee16897 LQ	77	/* Environment variables */
9ee16897 LQ	78
9ee16897 LQ	79
	80	#define CONFIG_LOADADDR 0x91000000 /* loadaddr env var */
	81
	82	#define CONFIG_EXTRA_ENV_SETTINGS \
	83	"script=boot.scr\0" \
e453794f DR	84	"image=zImage\0" \
	85	"fdt_file=imx51-ts4800.dtb\0" \
	86	"fdt_addr=0x90fe0000\0" \
9ee16897	87	"mmcdev=0\0" \
e453794f DR	88	"mmcpart=2\0" \
	89	"mmcroot=/dev/mmcblk0p3 rootwait rw\0" \
	90	"mmcargs=setenv bootargs root=${mmcroot}\0" \
9ee16897 LQ	91	"addtty=setenv bootargs ${bootargs} console=ttymxc0,${baudrate}\0" \
	92	"loadbootscript=" \
	93	"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
	94	"bootscript=echo Running bootscript from mmc ...; " \
	95	"source\0" \
	96	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image};\0" \
e453794f	97	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
9ee16897 LQ	98	"mmcboot=echo Booting from mmc ...; " \
9ee16897 LQ	99	"run mmcargs addtty; " \
e453794f DR	100	"if run loadfdt; then " \
	101	"bootz ${loadaddr} - ${fdt_addr}; " \
	102	"else " \
	103	"echo ERR: cannot load FDT; " \
	104	"fi; "
	105
9ee16897 LQ	106
	107	#define CONFIG_BOOTCOMMAND \
	108	"mmc dev ${mmcdev}; if mmc rescan; then " \
	109	"if run loadbootscript; then " \
	110	"run bootscript; " \
	111	"else " \
	112	"if run loadimage; then " \
	113	"run mmcboot; " \
	114	"fi; " \
	115	"fi; " \
	116	"fi; "
	117
	118	/*
	119	* Miscellaneous configurable options
	120	*/
	121	#define CONFIG_SYS_LONGHELP /* undef to save memory */
9ee16897	122	#define CONFIG_AUTO_COMPLETE
9ee16897 LQ	123
	124	#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
	125
	126	#define CONFIG_CMDLINE_EDITING
	127
	128	/*-----------------------------------------------------------------------
	129	* Physical Memory Map
	130	*/
	131	#define CONFIG_NR_DRAM_BANKS 1
	132	#define PHYS_SDRAM_1 CSD0_BASE_ADDR
	133	#define PHYS_SDRAM_1_SIZE (256 * 1024 * 1024)
	134
	135	#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
	136	#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
	137	#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
	138
9ee16897 LQ	139	#define CONFIG_SYS_INIT_SP_OFFSET \
	140	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
	141	#define CONFIG_SYS_INIT_SP_ADDR \
	142	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
	143
	144	/* Low level init */
	145	#define CONFIG_SYS_DDR_CLKSEL 0
	146	#define CONFIG_SYS_CLKTL_CBCDR 0x59E35100
	147	#define CONFIG_SYS_MAIN_PWR_ON
	148
	149	/*-----------------------------------------------------------------------
	150	* Environment organization
	151	*/
	152
	153	#define CONFIG_ENV_OFFSET (6 * 64 * 1024)
	154	#define CONFIG_ENV_SIZE (8 * 1024)
9ee16897 LQ	155	#define CONFIG_SYS_MMC_ENV_DEV 0
	156
	157	#endif