[people/ms/u-boot.git] / include / configs / tuxx1.h

/*
 * Copyright (C) 2006 Freescale Semiconductor, Inc.
 *                    Dave Liu <daveliu@freescale.com>
 *
 * Copyright (C) 2007 Logic Product Development, Inc.
 *                    Peter Barada <peterb@logicpd.com>
 *
 * Copyright (C) 2007 MontaVista Software, Inc.
 *                    Anton Vorontsov <avorontsov@ru.mvista.com>
 *
 * (C) Copyright 2008
 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
 *
 * (C) Copyright 2010-2013
 * Lukas Roggli, KEYMILE Ltd, lukas.roggli@keymile.com
 * Holger Brunck,  Keymile GmbH, holger.bruncl@keymile.com
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 */
#if defined(CONFIG_KMSUPX5)
#define CONFIG_KM_BOARD_NAME	"kmsupx5"
#define CONFIG_HOSTNAME		kmsupx5
#elif defined(CONFIG_TUGE1)
#define CONFIG_KM_BOARD_NAME	"tuge1"
#define CONFIG_HOSTNAME		tuge1
#elif defined(CONFIG_TUXX1)	/* TUXX1 board (tuxa1/tuda1) specific */
#define CONFIG_KM_BOARD_NAME	"tuxx1"
#define CONFIG_HOSTNAME		tuxx1
#elif defined(CONFIG_KMOPTI2)
#define CONFIG_KM_BOARD_NAME	"kmopti2"
#define CONFIG_HOSTNAME		kmopti2
#elif defined(CONFIG_KMTEPR2)
#define CONFIG_KM_BOARD_NAME    "kmtepr2"
#define CONFIG_HOSTNAME         kmtepr2
#else
#error ("Board not supported")
#endif

#define	CONFIG_SYS_TEXT_BASE	0xF0000000

/* include common defines/options for all 8321 Keymile boards */
#include "km/km8321-common.h"

#define CONFIG_SYS_APP1_BASE	0xA0000000    /* PAXG */
#define	CONFIG_SYS_APP1_SIZE	256 /* Megabytes */
#if defined(CONFIG_TUXX1) || defined(CONFIG_KMOPTI2) || defined(CONFIG_KMTEPR2)
#define CONFIG_SYS_APP2_BASE	0xB0000000    /* PINC3 */
#define	CONFIG_SYS_APP2_SIZE	256 /* Megabytes */
#endif

/*
 * Init Local Bus Memory Controller:
 *				      Device on board
 * Bank Bus     Machine PortSz Size   TUDA1  TUXA1  TUGE1   KMSUPX4 KMOPTI2
 * -----------------------------------------------------------------------------
 *  2   Local   GPCM    8 bit  256MB  PAXG   LPXF   PAXI    LPXF    PAXE
 *  3   Local   GPCM    8 bit  256MB  PINC3  PINC2  unused  unused  OPI2(16 bit)
 *
 *				      Device on board (continued)
 * Bank Bus     Machine PortSz Size   KMTEPR2
 * -----------------------------------------------------------------------------
 *  2   Local   GPCM    8 bit  256MB  NVRAM
 *  3   Local   GPCM    8 bit  256MB  TEP2 (16 bit)
 */

#if defined(CONFIG_KMTEPRO2)
/*
 * Configuration for C2 (NVRAM) on the local bus
 */
#define CONFIG_SYS_LBLAWBAR2_PRELIM    CONFIG_SYS_APP1_BASE
#define CONFIG_SYS_LBLAWAR2_PRELIM     (LBLAWAR_EN | LBLAWAR_256MB)
#define CONFIG_SYS_BR2_PRELIM  (CONFIG_SYS_APP1_BASE | \
				BR_PS_8 | \
				BR_MS_GPCM | \
				BR_V)
#define CONFIG_SYS_OR2_PRELIM  (MEG_TO_AM(CONFIG_SYS_APP1_SIZE) | \
				OR_GPCM_CSNT | \
				OR_GPCM_ACS_DIV2 | \
				OR_GPCM_XACS | \
				OR_GPCM_SCY_2 | \
				OR_GPCM_TRLX_SET | \
				OR_GPCM_EHTR_SET | \
				OR_GPCM_EAD)
#else
/*
 * Configuration for C2 on the local bus
 */
/* Window base at flash base */
#define CONFIG_SYS_LBLAWBAR2_PRELIM	CONFIG_SYS_APP1_BASE
/* Window size: 256 MB */
#define CONFIG_SYS_LBLAWAR2_PRELIM	(LBLAWAR_EN | LBLAWAR_256MB)

#define CONFIG_SYS_BR2_PRELIM	(CONFIG_SYS_APP1_BASE | \
				 BR_PS_8 | \
				 BR_MS_GPCM | \
				 BR_V)

#define CONFIG_SYS_OR2_PRELIM	(MEG_TO_AM(CONFIG_SYS_APP1_SIZE) | \
				 OR_GPCM_CSNT | \
				 OR_GPCM_ACS_DIV4 | \
				 OR_GPCM_SCY_2 | \
				 OR_GPCM_TRLX_SET | \
				 OR_GPCM_EHTR_CLEAR | \
				 OR_GPCM_EAD)
#endif

#if defined(CONFIG_TUXX1)
/*
 * Configuration for C3 on the local bus
 */
/* Access window base at PINC3 base */
#define CONFIG_SYS_LBLAWBAR3_PRELIM	CONFIG_SYS_APP2_BASE
/* Window size: 256 MB */
#define CONFIG_SYS_LBLAWAR3_PRELIM	(LBLAWAR_EN | LBLAWAR_256MB)

#define CONFIG_SYS_BR3_PRELIM	(CONFIG_SYS_APP2_BASE | \
				 BR_PS_8 |		\
				 BR_MS_GPCM |		\
				 BR_V)

#define CONFIG_SYS_OR3_PRELIM	(MEG_TO_AM(CONFIG_SYS_APP2_SIZE) | \
				 OR_GPCM_CSNT |	\
				 OR_GPCM_ACS_DIV2 | \
				 OR_GPCM_SCY_2 | \
				 OR_GPCM_TRLX_SET | \
				 OR_GPCM_EHTR_CLEAR)

#define CONFIG_SYS_MAMR		(MxMR_GPL_x4DIS | \
				 0x0000c000 | \
				 MxMR_WLFx_2X)
#endif

#if defined(CONFIG_KMOPTI2) || defined(CONFIG_KMTEPR2)
/*
 * Configuration for C3 on the local bus
 */
#define CONFIG_SYS_LBLAWBAR3_PRELIM	CONFIG_SYS_APP2_BASE
#define CONFIG_SYS_LBLAWAR3_PRELIM	(LBLAWAR_EN | LBLAWAR_256MB)
#define CONFIG_SYS_BR3_PRELIM	(CONFIG_SYS_APP2_BASE | \
				 BR_PS_16 |		\
				 BR_MS_GPCM |		\
				 BR_V)
#define CONFIG_SYS_OR3_PRELIM	(MEG_TO_AM(CONFIG_SYS_APP2_SIZE) | \
				 OR_GPCM_SCY_4 | \
				 OR_GPCM_TRLX_CLEAR | \
				 OR_GPCM_EHTR_CLEAR)
#endif

/*
 * MMU Setup
 */
/* APP1: icache cacheable, but dcache-inhibit and guarded */
#define CONFIG_SYS_IBAT5L	(CONFIG_SYS_APP1_BASE | \
				 BATL_PP_RW | \
				 BATL_MEMCOHERENCE)
/* 512M should also include APP2... */
#define CONFIG_SYS_IBAT5U	(CONFIG_SYS_APP1_BASE | \
				 BATU_BL_256M | \
				 BATU_VS | \
				 BATU_VP)
#define CONFIG_SYS_DBAT5L	(CONFIG_SYS_APP1_BASE | \
				 BATL_PP_RW | \
				 BATL_CACHEINHIBIT | \
				 BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_DBAT5U	CONFIG_SYS_IBAT5U

#if defined(CONFIG_TUGE1) || defined(CONFIG_KMSUPX5)
#define CONFIG_SYS_IBAT6L	(0)
#define CONFIG_SYS_IBAT6U	(0)
#define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
#else
/* APP2:  icache cacheable, but dcache-inhibit and guarded */
#define CONFIG_SYS_IBAT6L	(CONFIG_SYS_APP2_BASE | \
				 BATL_PP_RW | \
				 BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT6U	(CONFIG_SYS_APP2_BASE | \
				 BATU_BL_256M | \
				 BATU_VS | \
				 BATU_VP)
#define CONFIG_SYS_DBAT6L	(CONFIG_SYS_APP2_BASE | \
				 BATL_PP_RW | \
				 BATL_CACHEINHIBIT | \
				 BATL_GUARDEDSTORAGE)
#endif
#define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U

#define CONFIG_SYS_IBAT7L	(0)
#define CONFIG_SYS_IBAT7U	(0)
#define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
#define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U

#endif /* __CONFIG_H */
Commit	Line	Data
dc6033ec HS	1	/*
	2	* Copyright (C) 2006 Freescale Semiconductor, Inc.
	3	* Dave Liu <daveliu@freescale.com>
	4	*
	5	* Copyright (C) 2007 Logic Product Development, Inc.
	6	* Peter Barada <peterb@logicpd.com>
	7	*
	8	* Copyright (C) 2007 MontaVista Software, Inc.
	9	* Anton Vorontsov <avorontsov@ru.mvista.com>
	10	*
	11	* (C) Copyright 2008
	12	* Heiko Schocher, DENX Software Engineering, hs@denx.de.
	13	*
47f53649	14	* (C) Copyright 2010-2013
dc6033ec	15	* Lukas Roggli, KEYMILE Ltd, lukas.roggli@keymile.com
5f2a44d5	16	* Holger Brunck, Keymile GmbH, holger.bruncl@keymile.com
dc6033ec	17	*
1a459660	18	* SPDX-License-Identifier: GPL-2.0+
dc6033ec HS	19	*/
	20
	21	#ifndef __CONFIG_H
	22	#define __CONFIG_H
	23
	24	/*
	25	* High Level Configuration Options
	26	*/
47f53649	27	#if defined(CONFIG_KMSUPX5)
7f4bd9a6 HB	28	#define CONFIG_KM_BOARD_NAME "kmsupx5"
7f4bd9a6 HB	29	#define CONFIG_HOSTNAME kmsupx5
47f53649	30	#elif defined(CONFIG_TUGE1)
7f4bd9a6 HB	31	#define CONFIG_KM_BOARD_NAME "tuge1"
7f4bd9a6 HB	32	#define CONFIG_HOSTNAME tuge1
47f53649	33	#elif defined(CONFIG_TUXX1) /* TUXX1 board (tuxa1/tuda1) specific */
7f4bd9a6	34	#define CONFIG_KM_BOARD_NAME "tuxx1"
5f2a44d5	35	#define CONFIG_HOSTNAME tuxx1
4714f8e4 HB	36	#elif defined(CONFIG_KMOPTI2)
	37	#define CONFIG_KM_BOARD_NAME "kmopti2"
	38	#define CONFIG_HOSTNAME kmopti2
c1e121e4 CD	39	#elif defined(CONFIG_KMTEPR2)
	40	#define CONFIG_KM_BOARD_NAME "kmtepr2"
	41	#define CONFIG_HOSTNAME kmtepr2
47f53649 HB	42	#else
47f53649 HB	43	#error ("Board not supported")
f5a474bd	44	#endif
dc6033ec HS	45
dc6033ec HS	46	#define CONFIG_SYS_TEXT_BASE 0xF0000000
dc6033ec	47
8ed74341	48	/* include common defines/options for all 8321 Keymile boards */
264eaa0e	49	#include "km/km8321-common.h"
dc6033ec	50
dc6033ec HS	51	#define CONFIG_SYS_APP1_BASE 0xA0000000 /* PAXG */
dc6033ec HS	52	#define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */
c1e121e4	53	#if defined(CONFIG_TUXX1) \|\| defined(CONFIG_KMOPTI2) \|\| defined(CONFIG_KMTEPR2)
dc6033ec HS	54	#define CONFIG_SYS_APP2_BASE 0xB0000000 /* PINC3 */
dc6033ec HS	55	#define CONFIG_SYS_APP2_SIZE 256 /* Megabytes */
f5a474bd	56	#endif
dc6033ec	57
dc6033ec HS	58	/*
dc6033ec HS	59	* Init Local Bus Memory Controller:
c1e121e4 CD	60	* Device on board
	61	* Bank Bus Machine PortSz Size TUDA1 TUXA1 TUGE1 KMSUPX4 KMOPTI2
	62	* -----------------------------------------------------------------------------
	63	* 2 Local GPCM 8 bit 256MB PAXG LPXF PAXI LPXF PAXE
	64	* 3 Local GPCM 8 bit 256MB PINC3 PINC2 unused unused OPI2(16 bit)
dc6033ec	65	*
c1e121e4 CD	66	* Device on board (continued)
	67	* Bank Bus Machine PortSz Size KMTEPR2
	68	* -----------------------------------------------------------------------------
	69	* 2 Local GPCM 8 bit 256MB NVRAM
	70	* 3 Local GPCM 8 bit 256MB TEP2 (16 bit)
dc6033ec HS	71	*/
dc6033ec HS	72
c1e121e4 CD	73	#if defined(CONFIG_KMTEPRO2)
	74	/*
	75	* Configuration for C2 (NVRAM) on the local bus
	76	*/
	77	#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_APP1_BASE
	78	#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN \| LBLAWAR_256MB)
	79	#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_APP1_BASE \| \
	80	BR_PS_8 \| \
	81	BR_MS_GPCM \| \
	82	BR_V)
	83	#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_APP1_SIZE) \| \
	84	OR_GPCM_CSNT \| \
	85	OR_GPCM_ACS_DIV2 \| \
	86	OR_GPCM_XACS \| \
	87	OR_GPCM_SCY_2 \| \
	88	OR_GPCM_TRLX_SET \| \
	89	OR_GPCM_EHTR_SET \| \
	90	OR_GPCM_EAD)
	91	#else
dc6033ec	92	/*
5f2a44d5	93	* Configuration for C2 on the local bus
dc6033ec HS	94	*/
	95	/* Window base at flash base */
	96	#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_APP1_BASE
	97	/* Window size: 256 MB */
	98	#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN \| LBLAWAR_256MB)
	99
	100	#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_APP1_BASE \| \
	101	BR_PS_8 \| \
	102	BR_MS_GPCM \| \
	103	BR_V)
	104
	105	#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_APP1_SIZE) \| \
	106	OR_GPCM_CSNT \| \
	107	OR_GPCM_ACS_DIV4 \| \
	108	OR_GPCM_SCY_2 \| \
7d6a0982 JH	109	OR_GPCM_TRLX_SET \| \
7d6a0982 JH	110	OR_GPCM_EHTR_CLEAR \| \
dc6033ec	111	OR_GPCM_EAD)
c1e121e4 CD	112	#endif
c1e121e4 CD	113
47f53649	114	#if defined(CONFIG_TUXX1)
dc6033ec	115	/*
5f2a44d5	116	* Configuration for C3 on the local bus
dc6033ec HS	117	*/
	118	/* Access window base at PINC3 base */
	119	#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_APP2_BASE
	120	/* Window size: 256 MB */
	121	#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN \| LBLAWAR_256MB)
	122
	123	#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_APP2_BASE \| \
	124	BR_PS_8 \| \
	125	BR_MS_GPCM \| \
	126	BR_V)
	127
	128	#define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_APP2_SIZE) \| \
	129	OR_GPCM_CSNT \| \
7d6a0982 JH	130	OR_GPCM_ACS_DIV2 \| \
	131	OR_GPCM_SCY_2 \| \
	132	OR_GPCM_TRLX_SET \| \
	133	OR_GPCM_EHTR_CLEAR)
dc6033ec HS	134
	135	#define CONFIG_SYS_MAMR (MxMR_GPL_x4DIS \| \
	136	0x0000c000 \| \
	137	MxMR_WLFx_2X)
f5a474bd	138	#endif
dc6033ec	139
c1e121e4	140	#if defined(CONFIG_KMOPTI2) \|\| defined(CONFIG_KMTEPR2)
4714f8e4 HB	141	/*
	142	* Configuration for C3 on the local bus
	143	*/
	144	#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_APP2_BASE
	145	#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN \| LBLAWAR_256MB)
	146	#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_APP2_BASE \| \
	147	BR_PS_16 \| \
	148	BR_MS_GPCM \| \
	149	BR_V)
	150	#define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_APP2_SIZE) \| \
	151	OR_GPCM_SCY_4 \| \
	152	OR_GPCM_TRLX_CLEAR \| \
	153	OR_GPCM_EHTR_CLEAR)
	154	#endif
	155
dc6033ec HS	156	/*
	157	* MMU Setup
	158	*/
5f2a44d5	159	/* APP1: icache cacheable, but dcache-inhibit and guarded */
dc6033ec	160	#define CONFIG_SYS_IBAT5L (CONFIG_SYS_APP1_BASE \| \
72cd4087	161	BATL_PP_RW \| \
dc6033ec HS	162	BATL_MEMCOHERENCE)
	163	/* 512M should also include APP2... */
	164	#define CONFIG_SYS_IBAT5U (CONFIG_SYS_APP1_BASE \| \
	165	BATU_BL_256M \| \
	166	BATU_VS \| \
	167	BATU_VP)
	168	#define CONFIG_SYS_DBAT5L (CONFIG_SYS_APP1_BASE \| \
72cd4087	169	BATL_PP_RW \| \
dc6033ec HS	170	BATL_CACHEINHIBIT \| \
	171	BATL_GUARDEDSTORAGE)
	172	#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
	173
47f53649	174	#if defined(CONFIG_TUGE1) \|\| defined(CONFIG_KMSUPX5)
f5a474bd HB	175	#define CONFIG_SYS_IBAT6L (0)
	176	#define CONFIG_SYS_IBAT6U (0)
	177	#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
	178	#else
5f2a44d5	179	/* APP2: icache cacheable, but dcache-inhibit and guarded */
dc6033ec	180	#define CONFIG_SYS_IBAT6L (CONFIG_SYS_APP2_BASE \| \
72cd4087	181	BATL_PP_RW \| \
dc6033ec HS	182	BATL_MEMCOHERENCE)
	183	#define CONFIG_SYS_IBAT6U (CONFIG_SYS_APP2_BASE \| \
	184	BATU_BL_256M \| \
	185	BATU_VS \| \
	186	BATU_VP)
	187	#define CONFIG_SYS_DBAT6L (CONFIG_SYS_APP2_BASE \| \
72cd4087	188	BATL_PP_RW \| \
dc6033ec HS	189	BATL_CACHEINHIBIT \| \
dc6033ec HS	190	BATL_GUARDEDSTORAGE)
f5a474bd	191	#endif
dc6033ec HS	192	#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
	193
	194	#define CONFIG_SYS_IBAT7L (0)
	195	#define CONFIG_SYS_IBAT7U (0)
	196	#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
	197	#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
dc6033ec HS	198
dc6033ec HS	199	#endif /* __CONFIG_H */