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Commit | Line | Data |
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bd39050c MV |
1 | /* |
2 | * include/configs/ulcb.h | |
3 | * This file is ULCB board configuration. | |
4 | * | |
5 | * Copyright (C) 2017 Renesas Electronics Corporation | |
6 | * | |
7 | * SPDX-License-Identifier: GPL-2.0+ | |
8 | */ | |
9 | ||
10 | #ifndef __ULCB_H | |
11 | #define __ULCB_H | |
12 | ||
13 | #undef DEBUG | |
14 | ||
15 | #define CONFIG_RCAR_BOARD_STRING "ULCB" | |
16 | ||
17 | #include "rcar-gen3-common.h" | |
18 | ||
19 | /* M3 ULCB has 2 banks, each with 1 GiB of RAM */ | |
20 | #if defined(CONFIG_R8A7796) | |
21 | #undef PHYS_SDRAM_1_SIZE | |
22 | #undef PHYS_SDRAM_2_SIZE | |
23 | #define PHYS_SDRAM_1_SIZE (0x40000000u - DRAM_RSV_SIZE) | |
24 | #define PHYS_SDRAM_2_SIZE 0x40000000u | |
25 | #endif | |
26 | ||
27 | /* SCIF */ | |
bd39050c MV |
28 | #define CONFIG_CONS_SCIF2 |
29 | #define CONFIG_CONS_INDEX 2 | |
30 | #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_S3D4_CLK_FREQ | |
31 | ||
32 | /* [A] Hyper Flash */ | |
33 | /* use to RPC(SPI Multi I/O Bus Controller) */ | |
34 | ||
35 | /* Ethernet RAVB */ | |
bd39050c MV |
36 | #define CONFIG_BITBANGMII |
37 | #define CONFIG_BITBANGMII_MULTI | |
38 | ||
39 | /* Board Clock */ | |
40 | /* XTAL_CLK : 33.33MHz */ | |
41 | #define RCAR_XTAL_CLK 33333333u | |
42 | #define CONFIG_SYS_CLK_FREQ RCAR_XTAL_CLK | |
43 | /* ch0to2 CPclk, ch3to11 S3D2_PEREclk, ch12to14 S3D2_RTclk */ | |
44 | /* CPclk 16.66MHz, S3D2 133.33MHz , S3D4 66.66MHz */ | |
45 | #define CONFIG_CP_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) | |
46 | #define CONFIG_PLL1_CLK_FREQ (CONFIG_SYS_CLK_FREQ * 192 / 2) | |
47 | #define CONFIG_S3D2_CLK_FREQ (266666666u/2) | |
48 | #define CONFIG_S3D4_CLK_FREQ (266666666u/4) | |
49 | ||
50 | /* Generic Timer Definitions (use in assembler source) */ | |
51 | #define COUNTER_FREQUENCY 0xFE502A /* 16.66MHz from CPclk */ | |
52 | ||
53 | /* Generic Interrupt Controller Definitions */ | |
54 | #define CONFIG_GICV2 | |
55 | #define GICD_BASE 0xF1010000 | |
56 | #define GICC_BASE 0xF1020000 | |
57 | ||
58 | /* CPLD SPI */ | |
59 | #define CONFIG_CMD_SPI | |
60 | #define CONFIG_SOFT_SPI | |
61 | #define SPI_DELAY udelay(0) | |
62 | #define SPI_SDA(val) ulcb_softspi_sda(val) | |
63 | #define SPI_SCL(val) ulcb_softspi_scl(val) | |
64 | #define SPI_READ ulcb_softspi_read() | |
65 | #ifndef __ASSEMBLY__ | |
66 | void ulcb_softspi_sda(int); | |
67 | void ulcb_softspi_scl(int); | |
68 | unsigned char ulcb_softspi_read(void); | |
69 | #endif | |
70 | ||
71 | /* i2c */ | |
72 | #define CONFIG_SYS_I2C | |
73 | #define CONFIG_SYS_I2C_SH | |
74 | #define CONFIG_SYS_I2C_SLAVE 0x60 | |
75 | #define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 1 | |
76 | #define CONFIG_SYS_I2C_SH_SPEED0 400000 | |
77 | #define CONFIG_SH_I2C_DATA_HIGH 4 | |
78 | #define CONFIG_SH_I2C_DATA_LOW 5 | |
79 | #define CONFIG_SH_I2C_CLOCK 10000000 | |
80 | ||
81 | #define CONFIG_SYS_I2C_POWERIC_ADDR 0x30 | |
82 | ||
83 | /* USB */ | |
84 | #ifdef CONFIG_R8A7795 | |
85 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 3 | |
86 | #else | |
87 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 | |
88 | #endif | |
89 | ||
90 | /* SDHI */ | |
91 | #define CONFIG_SH_SDHI_FREQ 200000000 | |
92 | ||
93 | /* Environment in eMMC, at the end of 2nd "boot sector" */ | |
bd39050c MV |
94 | #define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE) |
95 | #define CONFIG_SYS_MMC_ENV_DEV 1 | |
96 | #define CONFIG_SYS_MMC_ENV_PART 2 | |
97 | ||
98 | /* Module stop status bits */ | |
99 | /* MFIS, SCIF1 */ | |
100 | #define CONFIG_SMSTP2_ENA 0x00002040 | |
101 | /* SCIF2 */ | |
102 | #define CONFIG_SMSTP3_ENA 0x00000400 | |
103 | /* INTC-AP, IRQC */ | |
104 | #define CONFIG_SMSTP4_ENA 0x00000180 | |
105 | ||
106 | #endif /* __ULCB_H */ |