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5894ca00 | 1 | /* |
f8f35944 | 2 | * Copyright (C) 2012-2015 Masahiro Yamada <yamada.masahiro@socionext.com> |
5894ca00 MY |
3 | * |
4 | * SPDX-License-Identifier: GPL-2.0+ | |
5 | */ | |
6 | ||
a187559e | 7 | /* U-Boot - Common settings for UniPhier Family */ |
5894ca00 MY |
8 | |
9 | #ifndef __CONFIG_UNIPHIER_COMMON_H__ | |
10 | #define __CONFIG_UNIPHIER_COMMON_H__ | |
11 | ||
233e42a9 MY |
12 | #define CONFIG_I2C_EEPROM |
13 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 | |
14 | ||
d064cbff | 15 | #ifdef CONFIG_SYS_NS16550_SERIAL |
5894ca00 MY |
16 | #define CONFIG_SYS_NS16550_COM1 CONFIG_SUPPORT_CARD_UART_BASE |
17 | #define CONFIG_SYS_NS16550_CLK 12288000 | |
18 | #define CONFIG_SYS_NS16550_REG_SIZE -2 | |
d064cbff | 19 | #endif |
5894ca00 | 20 | |
f5d0b9b2 MY |
21 | /* TODO: move to Kconfig and device tree */ |
22 | #if 0 | |
23 | #define CONFIG_SYS_NS16550_SERIAL | |
24 | #endif | |
25 | ||
26 | #define CONFIG_SMC911X | |
27 | ||
d7728aa4 MY |
28 | /* dummy: referenced by examples/standalone/smc911x_eeprom.c */ |
29 | #define CONFIG_SMC911X_BASE 0 | |
5894ca00 MY |
30 | #define CONFIG_SMC911X_32_BIT |
31 | ||
5894ca00 MY |
32 | /*----------------------------------------------------------------------- |
33 | * MMU and Cache Setting | |
34 | *----------------------------------------------------------------------*/ | |
35 | ||
36 | /* Comment out the following to enable L1 cache */ | |
37 | /* #define CONFIG_SYS_ICACHE_OFF */ | |
38 | /* #define CONFIG_SYS_DCACHE_OFF */ | |
39 | ||
53c45d4e MY |
40 | #define CONFIG_SYS_CACHELINE_SIZE 32 |
41 | ||
5894ca00 MY |
42 | /* Comment out the following to enable L2 cache */ |
43 | #define CONFIG_UNIPHIER_L2CACHE_ON | |
44 | ||
45 | #define CONFIG_DISPLAY_CPUINFO | |
46 | #define CONFIG_DISPLAY_BOARDINFO | |
08fda258 | 47 | #define CONFIG_MISC_INIT_F |
84ccd791 | 48 | #define CONFIG_BOARD_EARLY_INIT_F |
7a3620b2 | 49 | #define CONFIG_BOARD_EARLY_INIT_R |
5894ca00 MY |
50 | #define CONFIG_BOARD_LATE_INIT |
51 | ||
52 | #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) | |
53 | ||
54 | #define CONFIG_TIMESTAMP | |
55 | ||
56 | /* FLASH related */ | |
57 | #define CONFIG_MTD_DEVICE | |
58 | ||
59 | /* | |
60 | * uncomment the following to disable FLASH related code. | |
61 | */ | |
62 | /* #define CONFIG_SYS_NO_FLASH */ | |
63 | ||
64 | #define CONFIG_FLASH_CFI_DRIVER | |
65 | #define CONFIG_SYS_FLASH_CFI | |
66 | ||
67 | #define CONFIG_SYS_MAX_FLASH_SECT 256 | |
68 | #define CONFIG_SYS_MONITOR_BASE 0 | |
69 | #define CONFIG_SYS_FLASH_BASE 0 | |
70 | ||
71 | /* | |
72 | * flash_toggle does not work for out supoort card. | |
73 | * We need to use flash_status_poll. | |
74 | */ | |
75 | #define CONFIG_SYS_CFI_FLASH_STATUS_POLL | |
76 | ||
77 | #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ | |
78 | ||
9879842c | 79 | #define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1 |
5894ca00 MY |
80 | |
81 | /* serial console configuration */ | |
82 | #define CONFIG_BAUDRATE 115200 | |
83 | ||
5894ca00 MY |
84 | |
85 | #if !defined(CONFIG_SPL_BUILD) | |
86 | #define CONFIG_USE_ARCH_MEMSET | |
87 | #define CONFIG_USE_ARCH_MEMCPY | |
88 | #endif | |
89 | ||
90 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
91 | ||
92 | #define CONFIG_CMDLINE_EDITING /* add command line history */ | |
5894ca00 MY |
93 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
94 | /* Print Buffer Size */ | |
95 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) | |
96 | #define CONFIG_SYS_MAXARGS 16 /* max number of command */ | |
97 | /* Boot Argument Buffer Size */ | |
98 | #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) | |
99 | ||
100 | #define CONFIG_CONS_INDEX 1 | |
101 | ||
aa8a9348 | 102 | /* #define CONFIG_ENV_IS_NOWHERE */ |
5894ca00 | 103 | /* #define CONFIG_ENV_IS_IN_NAND */ |
aa8a9348 MY |
104 | #define CONFIG_ENV_IS_IN_MMC |
105 | #define CONFIG_ENV_OFFSET 0x80000 | |
5894ca00 | 106 | #define CONFIG_ENV_SIZE 0x2000 |
5894ca00 MY |
107 | /* #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) */ |
108 | ||
aa8a9348 MY |
109 | #define CONFIG_SYS_MMC_ENV_DEV 0 |
110 | #define CONFIG_SYS_MMC_ENV_PART 1 | |
111 | ||
5894ca00 MY |
112 | /* Time clock 1MHz */ |
113 | #define CONFIG_SYS_TIMER_RATE 1000000 | |
114 | ||
115 | /* | |
116 | * By default, ARP timeout is 5 sec. | |
117 | * The first ARP request does not seem to work. | |
118 | * So we need to retry ARP request anyway. | |
119 | * We want to shrink the interval until the second ARP request. | |
120 | */ | |
121 | #define CONFIG_ARP_TIMEOUT 500UL /* 0.5 msec */ | |
122 | ||
5894ca00 MY |
123 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 |
124 | #define CONFIG_SYS_NAND_MAX_CHIPS 2 | |
125 | #define CONFIG_SYS_NAND_ONFI_DETECTION | |
126 | ||
127 | #define CONFIG_NAND_DENALI_ECC_SIZE 1024 | |
128 | ||
8497ccc4 | 129 | #ifdef CONFIG_ARCH_UNIPHIER_PH1_SLD3 |
3365b4eb MY |
130 | #define CONFIG_SYS_NAND_REGS_BASE 0xf8100000 |
131 | #define CONFIG_SYS_NAND_DATA_BASE 0xf8000000 | |
132 | #else | |
5894ca00 MY |
133 | #define CONFIG_SYS_NAND_REGS_BASE 0x68100000 |
134 | #define CONFIG_SYS_NAND_DATA_BASE 0x68000000 | |
3365b4eb | 135 | #endif |
5894ca00 MY |
136 | |
137 | #define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_DATA_BASE + 0x10) | |
138 | ||
139 | #define CONFIG_SYS_NAND_USE_FLASH_BBT | |
140 | #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 | |
141 | ||
495deb44 | 142 | /* USB */ |
495deb44 | 143 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 |
53c45d4e | 144 | #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 4 |
495deb44 MY |
145 | #define CONFIG_CMD_FAT |
146 | #define CONFIG_FAT_WRITE | |
147 | #define CONFIG_DOS_PARTITION | |
148 | ||
4aceb3f8 MY |
149 | /* SD/MMC */ |
150 | #define CONFIG_CMD_MMC | |
a55d9fee | 151 | #define CONFIG_SUPPORT_EMMC_BOOT |
4aceb3f8 MY |
152 | #define CONFIG_GENERIC_MMC |
153 | ||
5894ca00 MY |
154 | /* memtest works on */ |
155 | #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE | |
156 | #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x01000000) | |
157 | ||
158 | #define CONFIG_BOOTDELAY 3 | |
159 | #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ | |
5894ca00 MY |
160 | |
161 | /* | |
162 | * Network Configuration | |
163 | */ | |
5894ca00 MY |
164 | #define CONFIG_SERVERIP 192.168.11.1 |
165 | #define CONFIG_IPADDR 192.168.11.10 | |
166 | #define CONFIG_GATEWAYIP 192.168.11.1 | |
167 | #define CONFIG_NETMASK 255.255.255.0 | |
168 | ||
169 | #define CONFIG_LOADADDR 0x84000000 | |
170 | #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR | |
5894ca00 MY |
171 | |
172 | #define CONFIG_CMDLINE_EDITING /* add command line history */ | |
173 | ||
174 | #define CONFIG_BOOTCOMMAND "run $bootmode" | |
175 | ||
176 | #define CONFIG_ROOTPATH "/nfs/root/path" | |
177 | #define CONFIG_NFSBOOTCOMMAND \ | |
178 | "setenv bootargs $bootargs root=/dev/nfs rw " \ | |
179 | "nfsroot=$serverip:$rootpath " \ | |
180 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off;" \ | |
d566f754 | 181 | "run __nfsboot" |
5894ca00 | 182 | |
421376ae MY |
183 | #ifdef CONFIG_FIT |
184 | #define CONFIG_BOOTFILE "fitImage" | |
185 | #define LINUXBOOT_ENV_SETTINGS \ | |
186 | "fit_addr=0x00100000\0" \ | |
187 | "fit_addr_r=0x84100000\0" \ | |
188 | "fit_size=0x00f00000\0" \ | |
5451b777 | 189 | "norboot=setexpr fit_addr $nor_base + $fit_addr &&" \ |
421376ae | 190 | "bootm $fit_addr\0" \ |
5451b777 | 191 | "nandboot=nand read $fit_addr_r $fit_addr $fit_size &&" \ |
e037db0c | 192 | "bootm $fit_addr_r\0" \ |
5451b777 | 193 | "tftpboot=tftpboot $fit_addr_r $bootfile &&" \ |
d566f754 MY |
194 | "bootm $fit_addr_r\0" \ |
195 | "__nfsboot=run tftpboot\0" | |
421376ae | 196 | #else |
89835b35 MY |
197 | #define CONFIG_CMD_BOOTZ |
198 | #define CONFIG_BOOTFILE "zImage" | |
421376ae MY |
199 | #define LINUXBOOT_ENV_SETTINGS \ |
200 | "fdt_addr=0x00100000\0" \ | |
201 | "fdt_addr_r=0x84100000\0" \ | |
202 | "fdt_size=0x00008000\0" \ | |
203 | "kernel_addr=0x00200000\0" \ | |
89835b35 | 204 | "kernel_addr_r=0x80208000\0" \ |
421376ae MY |
205 | "kernel_size=0x00800000\0" \ |
206 | "ramdisk_addr=0x00a00000\0" \ | |
207 | "ramdisk_addr_r=0x84a00000\0" \ | |
208 | "ramdisk_size=0x00600000\0" \ | |
e037db0c | 209 | "ramdisk_file=rootfs.cpio.uboot\0" \ |
cd5d9565 MY |
210 | "boot_common=setexpr bootm_low $kernel_addr_r '&' fe000000 &&" \ |
211 | "bootz $kernel_addr_r $ramdisk_addr_r $fdt_addr_r\0" \ | |
212 | "norboot=setexpr kernel_addr $nor_base + $kernel_addr &&" \ | |
90a6e929 | 213 | "cp.b $kernel_addr $kernel_addr_r $kernel_size &&" \ |
cd5d9565 MY |
214 | "setexpr ramdisk_addr_r $nor_base + $ramdisk_addr &&" \ |
215 | "setexpr fdt_addr_r $nor_base + $fdt_addr &&" \ | |
216 | "run boot_common\0" \ | |
217 | "nandboot=nand read $kernel_addr_r $kernel_addr $kernel_size &&" \ | |
421376ae MY |
218 | "nand read $ramdisk_addr_r $ramdisk_addr $ramdisk_size &&" \ |
219 | "nand read $fdt_addr_r $fdt_addr $fdt_size &&" \ | |
cd5d9565 MY |
220 | "run boot_common\0" \ |
221 | "tftpboot=tftpboot $kernel_addr_r $bootfile &&" \ | |
e037db0c MY |
222 | "tftpboot $ramdisk_addr_r $ramdisk_file &&" \ |
223 | "tftpboot $fdt_addr_r $fdt_file &&" \ | |
d566f754 MY |
224 | "run boot_common\0" \ |
225 | "__nfsboot=tftpboot $kernel_addr_r $bootfile &&" \ | |
226 | "tftpboot $fdt_addr_r $fdt_file &&" \ | |
227 | "tftpboot $fdt_addr_r $fdt_file &&" \ | |
228 | "setenv ramdisk_addr_r - &&" \ | |
cd5d9565 | 229 | "run boot_common\0" |
421376ae MY |
230 | #endif |
231 | ||
232 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
233 | "netdev=eth0\0" \ | |
234 | "verify=n\0" \ | |
90a6e929 | 235 | "nor_base=0x42000000\0" \ |
c231c436 MY |
236 | "emmcupdate=mmcsetn &&" \ |
237 | "mmc partconf $mmc_first_dev 0 1 1 &&" \ | |
238 | "mmc erase 0 800 &&" \ | |
239 | "tftpboot u-boot-spl.bin &&" \ | |
240 | "mmc write $loadaddr 0 80 &&" \ | |
241 | "tftpboot u-boot.img &&" \ | |
242 | "mmc write $loadaddr 80 780\0" \ | |
421376ae | 243 | "nandupdate=nand erase 0 0x00100000 &&" \ |
3cb9abc9 | 244 | "tftpboot u-boot-spl.bin &&" \ |
421376ae | 245 | "nand write $loadaddr 0 0x00010000 &&" \ |
3cb9abc9 | 246 | "tftpboot u-boot.img &&" \ |
421376ae | 247 | "nand write $loadaddr 0x00010000 0x000f0000\0" \ |
421376ae | 248 | LINUXBOOT_ENV_SETTINGS |
5894ca00 | 249 | |
17bd4a21 MY |
250 | #define CONFIG_SYS_BOOTMAPSZ 0x20000000 |
251 | ||
cf88affa | 252 | #define CONFIG_SYS_SDRAM_BASE 0x80000000 |
5894ca00 | 253 | #define CONFIG_NR_DRAM_BANKS 2 |
5894ca00 | 254 | |
8497ccc4 MY |
255 | #if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD3) || \ |
256 | defined(CONFIG_ARCH_UNIPHIER_PH1_LD4) || \ | |
257 | defined(CONFIG_ARCH_UNIPHIER_PH1_SLD8) | |
f5d0b9b2 | 258 | #define CONFIG_SPL_TEXT_BASE 0x00040000 |
323d1f9d | 259 | #else |
f5d0b9b2 MY |
260 | #define CONFIG_SPL_TEXT_BASE 0x00100000 |
261 | #endif | |
262 | ||
755c7d9a | 263 | #define CONFIG_SPL_STACK (0x00100000) |
8cddc279 | 264 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE) |
5894ca00 | 265 | |
a286039b MY |
266 | #define CONFIG_PANIC_HANG |
267 | ||
5894ca00 | 268 | #define CONFIG_SPL_FRAMEWORK |
499785b9 | 269 | #define CONFIG_SPL_SERIAL_SUPPORT |
5894ca00 | 270 | #define CONFIG_SPL_NAND_SUPPORT |
a55d9fee | 271 | #define CONFIG_SPL_MMC_SUPPORT |
5894ca00 MY |
272 | |
273 | #define CONFIG_SPL_LIBCOMMON_SUPPORT /* for mem_malloc_init */ | |
274 | #define CONFIG_SPL_LIBGENERIC_SUPPORT | |
275 | ||
276 | #define CONFIG_SPL_BOARD_INIT | |
277 | ||
278 | #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x10000 | |
a55d9fee | 279 | #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x80 |
5894ca00 | 280 | |
6a3cffe8 MY |
281 | #define CONFIG_SPL_MAX_FOOTPRINT 0x10000 |
282 | ||
5894ca00 | 283 | #endif /* __CONFIG_UNIPHIER_COMMON_H__ */ |