[people/ms/u-boot.git] / include / configs / utx8245.h

/*
 * (C) Copyright 2001
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * (C) Copyright 2002
 * Gregory E. Allen, gallen@arlut.utexas.edu
 * Matthew E. Karger, karger@arlut.utexas.edu
 * Applied Research Laboratories, The University of Texas at Austin
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*
 *
 * Configuration settings for the utx8245 board.
 *
 */

/* ------------------------------------------------------------------------- */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MPC8245		1
#define CONFIG_UTX8245		1

#define	CONFIG_SYS_TEXT_BASE	0xFFF00000

#define DEBUG				1

#define CONFIG_IDENT_STRING     " [UTX5] "

#define CONFIG_CONS_INDEX	1
#define CONFIG_BAUDRATE		57600

#define CONFIG_BOOTDELAY	2
#define CONFIG_AUTOBOOT_PROMPT	"autoboot in %d seconds\n", bootdelay
#define CONFIG_BOOTCOMMAND	"run nfsboot"	/* autoboot command	*/
#define CONFIG_BOOTARGS		"root=/dev/ram console=ttyS0,57600" /* RAMdisk */
#define CONFIG_ETHADDR		00:AA:00:14:00:05	/* UTX5 */
#define CONFIG_SERVERIP		10.8.17.105	/* Spree */

#define CONFIG_EXTRA_ENV_SETTINGS \
	"kernel_addr=FFA00000\0" \
	"ramdisk_addr=FF800000\0" \
	"u-boot_startaddr=FFB00000\0" \
	"u-boot_endaddr=FFB2FFFF\0" \
	"nfsargs=setenv bootargs console=ttyS0,${baudrate} root=/dev/nfs rw \
nfsroot=${nfsrootip}:${rootpath} ip=dhcp\0" \
	"ramargs=setenv bootargs console=ttyS0,${baudrate} root=/dev/ram0\0" \
	"smargs=setenv bootargs console=ttyS0,${baudrate} root=/dev/mtdblock1 ro\0" \
	"fwargs=setenv bootargs console=ttyS0,${baudrate} root=/dev/sda2 ro\0" \
	"nfsboot=run nfsargs;bootm ${kernel_addr}\0" \
	"ramboot=run ramargs;bootm ${kernel_addr} ${ramdisk_addr}\0" \
	"smboot=run smargs;bootm ${kernel_addr} ${ramdisk_addr}\0" \
	"fwboot=run fwargs;bootm ${kernel_addr} ${ramdisk_addr}\0" \
	"update_u-boot=tftp ${loadaddr} /bdi2000/u-boot.bin;protect off \
${u-boot_startaddr} ${u-boot_endaddr};era ${u-boot_startaddr} \
${u-boot_endaddr};cp.b ${loadaddr} ${u-boot_startaddr} ${filesize};\
protect on ${u-boot_startaddr} ${u-boot_endaddr}"

#define CONFIG_ENV_OVERWRITE


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_BDI
#define CONFIG_CMD_PCI
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_CONSOLE
#define CONFIG_CMD_LOADS
#define CONFIG_CMD_LOADB
#define CONFIG_CMD_IMI
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_NET
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_I2C
#define CONFIG_CMD_DATE


/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP				/* undef to save memory		*/
#define CONFIG_SYS_CBSIZE	256				/* Console I/O Buffer Size	*/

/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)

#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
#define CONFIG_SYS_LOAD_ADDR	0x00100000	/* Default load address		*/


/*-----------------------------------------------------------------------
 * PCI configuration
 *-----------------------------------------------------------------------
 */
#define CONFIG_PCI				/* include pci support		*/
#define	CONFIG_PCI_INDIRECT_BRIDGE 1	/* indirect PCI bridge support */
#undef CONFIG_PCI_PNP
#define CONFIG_PCI_SCAN_SHOW
#define CONFIG_EEPRO100
#define CONFIG_SYS_RX_ETH_BUFFER	8               /* use 8 rx buffer on eepro100  */
#define CONFIG_EEPRO100_SROM_WRITE

#define PCI_ENET0_IOADDR	0xF0000000
#define PCI_ENET0_MEMADDR	0xF0000000

#define PCI_FIREWIRE_IOADDR		0xF1000000
#define PCI_FIREWIRE_MEMADDR	0xF1000000
/*
#define PCI_ENET0_IOADDR	0xFE000000
#define PCI_ENET0_MEMADDR	0x80000000

#define PCI_FIREWIRE_IOADDR	0x81000000
#define PCI_FIREWIRE_MEMADDR	0x81000000
*/

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define CONFIG_SYS_SDRAM_BASE	    0x00000000
#define CONFIG_SYS_MAX_RAM_SIZE    0x10000000	/* 256MB  */
/*#define CONFIG_SYS_VERY_BIG_RAM	1 */

/* FLASH_BASE is FF800000, with 4MB on RCS0, but the reset vector
 * is actually located at FFF00100.  Therefore, U-Boot is
 * physically located at 0xFFB0_0000, but is also mirrored at
 * 0xFFF0_0000.
 */
#define CONFIG_SYS_RESET_ADDRESS   0xFFF00100

#define CONFIG_SYS_EUMB_ADDR	    0xFC000000

#define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_TEXT_BASE

#define CONFIG_SYS_MONITOR_LEN	    (256 << 10) /* Reserve 256 kB for Monitor	*/
#define CONFIG_SYS_MALLOC_LEN	    (128 << 10) /* Reserve 128 kB for malloc()	*/

/*#define CONFIG_SYS_DRAM_TEST		1 */
#define CONFIG_SYS_MEMTEST_START   0x00003000	/* memtest works on	0...256 MB	*/
#define CONFIG_SYS_MEMTEST_END	    0x0ff8ffa7	/* in SDRAM, skips exception */
										/* vectors and U-Boot */


/*--------------------------------------------------------------------
 * Definitions for initial stack pointer and data area
 *------------------------------------------------------------------*/
#define CONFIG_SYS_INIT_DATA_SIZE    128	/* Size in bytes reserved for */
									/* initial data */
#define CONFIG_SYS_INIT_RAM_ADDR     0x40000000
#define CONFIG_SYS_INIT_RAM_SIZE      0x1000
#define CONFIG_SYS_INIT_DATA_OFFSET  (CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_INIT_DATA_SIZE)
#define CONFIG_SYS_GBL_DATA_OFFSET  (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)

/*--------------------------------------------------------------------
 * NS16550 Configuration
 *------------------------------------------------------------------*/
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL

#define CONFIG_SYS_NS16550_REG_SIZE	1

#if (CONFIG_CONS_INDEX == 1 || CONFIG_CONS_INDEX == 2)
#	define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
#else
#	define CONFIG_SYS_NS16550_CLK 33000000
#endif

#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_EUMB_ADDR + 0x4500)
#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_EUMB_ADDR + 0x4600)
#define CONFIG_SYS_NS16550_COM3	0xFF000000
#define CONFIG_SYS_NS16550_COM4	0xFF000008

/*--------------------------------------------------------------------
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 * For the detail description refer to the MPC8240 user's manual.
 *------------------------------------------------------------------*/

#define CONFIG_SYS_CLK_FREQ  33000000

/*#define CONFIG_SYS_ETH_DEV_FN	     0x7800 */
/*#define CONFIG_SYS_ETH_IOBASE	     0x00104000 */

/*--------------------------------------------------------------------
 * I2C Configuration
 *------------------------------------------------------------------*/
#if 1
#define CONFIG_HARD_I2C		1		/* To enable I2C support	*/
#define CONFIG_SYS_I2C_SPEED		400000
#define CONFIG_SYS_I2C_SLAVE		0x7F
#endif

#define CONFIG_RTC_PCF8563	1		/* enable I2C support for */
									/* Philips PCF8563 RTC */
#define CONFIG_SYS_I2C_RTC_ADDR	0x51	/* Philips PCF8563 RTC address */

/*--------------------------------------------------------------------
 *	Memory Control Configuration Register values
 *	- see sec. 4.12 of MPC8245 UM
 *------------------------------------------------------------------*/

/**** MCCR1 ****/
#define CONFIG_SYS_ROMNAL	    0
#define CONFIG_SYS_ROMFAL	    10		/* (tacc=70ns)*mem_freq - 2,
									mem_freq = 100MHz */

#define CONFIG_SYS_BANK7_ROW	0		/* SDRAM bank 7-0 row address */
#define CONFIG_SYS_BANK6_ROW	0		/*	bit count */
#define CONFIG_SYS_BANK5_ROW	0
#define CONFIG_SYS_BANK4_ROW	0
#define CONFIG_SYS_BANK3_ROW	0
#define CONFIG_SYS_BANK2_ROW	0
#define CONFIG_SYS_BANK1_ROW	2
#define CONFIG_SYS_BANK0_ROW	2

/**** MCCR2, refresh interval clock cycles ****/
#define CONFIG_SYS_REFINT	    480	    /* 33 MHz SDRAM clock was 480 */

/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4. */
#define CONFIG_SYS_BSTOPRE	    1023	/* burst to precharge[0..9], */
								/* sets open page interval */

/**** MCCR3 ****/
#define CONFIG_SYS_REFREC	    7	    /* Refresh to activate interval, trc */

/**** MCCR4 ****/
#define CONFIG_SYS_PRETOACT	    2	    /* trp */
#define CONFIG_SYS_ACTTOPRE	    7	    /* trcd + (burst length - 1) + trdl */
#define CONFIG_SYS_SDMODE_CAS_LAT  3	    /* SDMODE CAS latancy */
#define CONFIG_SYS_SDMODE_WRAP	    0	    /* SDMODE wrap type, sequential */
#define CONFIG_SYS_ACTORW		2		/* trcd min */
#define CONFIG_SYS_DBUS_SIZE2		1		/* set for 8-bit RCS1, clear for 32,64 */
#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1
#define CONFIG_SYS_EXTROM	    0			/* we don't need extended ROM space */
#define CONFIG_SYS_REGDIMM	    0

/* calculate according to formula in sec. 6-22 of 8245 UM */
#define CONFIG_SYS_PGMAX           50		/* how long the 8245 retains the */
									/* currently accessed page in memory */
									/* was 45 */

#define CONFIG_SYS_SDRAM_DSCD	0x20	/* SDRAM data in sample clock delay - note */
								/* bits 7,6, and 3-0 MUST be 0 */

#if 0
#define CONFIG_SYS_DLL_MAX_DELAY	0x04
#else
#define CONFIG_SYS_DLL_MAX_DELAY	0
#endif
#if 0							/* need for 33MHz SDRAM */
#define CONFIG_SYS_DLL_EXTEND	0x80
#else
#define CONFIG_SYS_DLL_EXTEND	0
#endif
#define CONFIG_SYS_PCI_HOLD_DEL 0x20


/* Memory bank settings.
 * Only bits 20-29 are actually used from these values to set the
 * start/end addresses. The upper two bits will always be 0, and the lower
 * 20 bits will be 0x00000 for a start address, or 0xfffff for an end
 * address. Refer to the MPC8245 user manual.
 */

#define CONFIG_SYS_BANK0_START	    0x00000000
#define CONFIG_SYS_BANK0_END	    (CONFIG_SYS_MAX_RAM_SIZE/2 - 1)
#define CONFIG_SYS_BANK0_ENABLE    1
#define CONFIG_SYS_BANK1_START	    CONFIG_SYS_MAX_RAM_SIZE/2
#define CONFIG_SYS_BANK1_END	    (CONFIG_SYS_MAX_RAM_SIZE - 1)
#define CONFIG_SYS_BANK1_ENABLE    1
#define CONFIG_SYS_BANK2_START	    0x3ff00000		/* not available in this design */
#define CONFIG_SYS_BANK2_END	    0x3fffffff
#define CONFIG_SYS_BANK2_ENABLE    0
#define CONFIG_SYS_BANK3_START	    0x3ff00000
#define CONFIG_SYS_BANK3_END	    0x3fffffff
#define CONFIG_SYS_BANK3_ENABLE    0
#define CONFIG_SYS_BANK4_START	    0x3ff00000
#define CONFIG_SYS_BANK4_END	    0x3fffffff
#define CONFIG_SYS_BANK4_ENABLE    0
#define CONFIG_SYS_BANK5_START	    0x3ff00000
#define CONFIG_SYS_BANK5_END	    0x3fffffff
#define CONFIG_SYS_BANK5_ENABLE    0
#define CONFIG_SYS_BANK6_START	    0x3ff00000
#define CONFIG_SYS_BANK6_END	    0x3fffffff
#define CONFIG_SYS_BANK6_ENABLE    0
#define CONFIG_SYS_BANK7_START	    0x3ff00000
#define CONFIG_SYS_BANK7_END	    0x3fffffff
#define CONFIG_SYS_BANK7_ENABLE    0

/*--------------------------------------------------------------------*/
/* 4.4 - Output Driver Control Register */
/*--------------------------------------------------------------------*/
#define CONFIG_SYS_ODCR	    0xe5

/*--------------------------------------------------------------------*/
/* 4.8 - Error Handling Registers */
/*-------------------------------CONFIG_SYS_SDMODE_BURSTLEN-------------------------------------*/
#define CONFIG_SYS_ERRENR1	0x11	/* enable SDRAM refresh overflow error */

/* SDRAM 0-256 MB */
#define CONFIG_SYS_IBAT0L  (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
/*#define CONFIG_SYS_IBAT0L  (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_CACHEINHIBIT) */
#define CONFIG_SYS_IBAT0U  (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)

/* stack in dcache */
#define CONFIG_SYS_IBAT1L  (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT1U  (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)


#define CONFIG_SYS_IBAT2L  (CONFIG_SYS_SDRAM_BASE + 0x10000000 | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT2U  (CONFIG_SYS_SDRAM_BASE + 0x10000000| BATU_BL_256M | BATU_VS | BATU_VP)

/* PCI memory */
/*#define CONFIG_SYS_IBAT2L  (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) */
/*#define CONFIG_SYS_IBAT2U  (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) */

/*Flash, config addrs, etc. */
#define CONFIG_SYS_IBAT3L  (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
#define CONFIG_SYS_IBAT3U  (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)

#define CONFIG_SYS_DBAT0L  CONFIG_SYS_IBAT0L
#define CONFIG_SYS_DBAT0U  CONFIG_SYS_IBAT0U
#define CONFIG_SYS_DBAT1L  CONFIG_SYS_IBAT1L
#define CONFIG_SYS_DBAT1U  CONFIG_SYS_IBAT1U
#define CONFIG_SYS_DBAT2L  CONFIG_SYS_IBAT2L
#define CONFIG_SYS_DBAT2U  CONFIG_SYS_IBAT2U
#define CONFIG_SYS_DBAT3L  CONFIG_SYS_IBAT3L
#define CONFIG_SYS_DBAT3U  CONFIG_SYS_IBAT3U

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ	    (8 << 20)	/* Initial Memory map for Linux */

/*-----------------------------------------------------------------------
 * FLASH organization
 *----------------------------------------------------------------------*/
#define CONFIG_SYS_FLASH_BASE	    0xFF800000
#define CONFIG_SYS_MAX_FLASH_BANKS	1			/* Max number of flash banks */

/*	NOTE: environment is not EMBEDDED in the u-boot code.
	It's stored in flash in its own separate sector.  */
#define CONFIG_ENV_IS_IN_FLASH	    1

#if 1	/* AMD AM29LV033C */
#define CONFIG_SYS_MAX_FLASH_SECT	64		/* Max number of sectors in one bank */
#define CONFIG_ENV_ADDR		0xFFBF0000	/* flash sector SA63 */
#define CONFIG_ENV_SECT_SIZE	(64*1024)	/* Size of the Environment Sector */
#else	/* AMD AM29LV116D */
#define CONFIG_SYS_MAX_FLASH_SECT	35	/* Max number of sectors in one bank */
#define CONFIG_ENV_ADDR		0xFF9FA000	/* flash sector SA33 */
#define CONFIG_ENV_SECT_SIZE	(8*1024)	/* Size of the Environment Sector */
#endif /* #if */

#define CONFIG_ENV_SIZE		CONFIG_ENV_SECT_SIZE		/* Size of the Environment */
#define CONFIG_ENV_OFFSET		0			/* starting right at the beginning */

#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CONFIG_SYS_FLASH_WRITE_TOUT	500		/* Timeout for Flash Write (in ms)	*/

#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
#undef CONFIG_SYS_RAMBOOT
#else
#define CONFIG_SYS_RAMBOOT
#endif


/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CONFIG_SYS_CACHELINE_SIZE	32
#if defined(CONFIG_CMD_KGDB)
#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
#endif

#endif	/* __CONFIG_H */
Commit	Line	Data
c609719b WD	1	/*
	2	* (C) Copyright 2001
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* (C) Copyright 2002
	6	* Gregory E. Allen, gallen@arlut.utexas.edu
	7	* Matthew E. Karger, karger@arlut.utexas.edu
	8	* Applied Research Laboratories, The University of Texas at Austin
	9	*
3765b3e7	10	* SPDX-License-Identifier: GPL-2.0+
c609719b WD	11	*/
	12
	13	/*
	14	*
	15	* Configuration settings for the utx8245 board.
	16	*
	17	*/
	18
	19	/* ------------------------------------------------------------------------- */
	20
	21	/*
	22	* board/config.h - configuration options, board specific
	23	*/
	24
	25	#ifndef __CONFIG_H
	26	#define __CONFIG_H
	27
	28	/*
	29	* High Level Configuration Options
	30	* (easy to change)
	31	*/
	32
c609719b WD	33	#define CONFIG_MPC8245 1
c609719b WD	34	#define CONFIG_UTX8245 1
2ae18241 WD	35
	36	#define CONFIG_SYS_TEXT_BASE 0xFFF00000
	37
c609719b WD	38	#define DEBUG 1
c609719b WD	39
7a8e9bed WD	40	#define CONFIG_IDENT_STRING " [UTX5] "
7a8e9bed WD	41
c609719b WD	42	#define CONFIG_CONS_INDEX 1
c609719b WD	43	#define CONFIG_BAUDRATE 57600
c609719b	44
7a8e9bed	45	#define CONFIG_BOOTDELAY 2
f2302d44	46	#define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds\n", bootdelay
7a8e9bed	47	#define CONFIG_BOOTCOMMAND "run nfsboot" /* autoboot command */
c609719b	48	#define CONFIG_BOOTARGS "root=/dev/ram console=ttyS0,57600" /* RAMdisk */
7a8e9bed WD	49	#define CONFIG_ETHADDR 00:AA:00:14:00:05 /* UTX5 */
7a8e9bed WD	50	#define CONFIG_SERVERIP 10.8.17.105 /* Spree */
7a8e9bed WD	51
	52	#define CONFIG_EXTRA_ENV_SETTINGS \
	53	"kernel_addr=FFA00000\0" \
	54	"ramdisk_addr=FF800000\0" \
	55	"u-boot_startaddr=FFB00000\0" \
	56	"u-boot_endaddr=FFB2FFFF\0" \
fe126d8b WD	57	"nfsargs=setenv bootargs console=ttyS0,${baudrate} root=/dev/nfs rw \
	58	nfsroot=${nfsrootip}:${rootpath} ip=dhcp\0" \
	59	"ramargs=setenv bootargs console=ttyS0,${baudrate} root=/dev/ram0\0" \
	60	"smargs=setenv bootargs console=ttyS0,${baudrate} root=/dev/mtdblock1 ro\0" \
	61	"fwargs=setenv bootargs console=ttyS0,${baudrate} root=/dev/sda2 ro\0" \
	62	"nfsboot=run nfsargs;bootm ${kernel_addr}\0" \
	63	"ramboot=run ramargs;bootm ${kernel_addr} ${ramdisk_addr}\0" \
	64	"smboot=run smargs;bootm ${kernel_addr} ${ramdisk_addr}\0" \
	65	"fwboot=run fwargs;bootm ${kernel_addr} ${ramdisk_addr}\0" \
	66	"update_u-boot=tftp ${loadaddr} /bdi2000/u-boot.bin;protect off \
	67	${u-boot_startaddr} ${u-boot_endaddr};era ${u-boot_startaddr} \
	68	${u-boot_endaddr};cp.b ${loadaddr} ${u-boot_startaddr} ${filesize};\
	69	protect on ${u-boot_startaddr} ${u-boot_endaddr}"
7a8e9bed	70
c609719b WD	71	#define CONFIG_ENV_OVERWRITE
c609719b WD	72
6c18eb98	73
079a136c JL	74	/*
	75	* BOOTP options
	76	*/
	77	#define CONFIG_BOOTP_BOOTFILESIZE
	78	#define CONFIG_BOOTP_BOOTPATH
	79	#define CONFIG_BOOTP_GATEWAY
	80	#define CONFIG_BOOTP_HOSTNAME
	81
	82
6c18eb98 JL	83	/*
6c18eb98 JL	84	* Command line configuration.
c609719b	85	*/
6c18eb98 JL	86	#include <config_cmd_default.h>
	87
	88	#define CONFIG_CMD_BDI
	89	#define CONFIG_CMD_PCI
	90	#define CONFIG_CMD_FLASH
	91	#define CONFIG_CMD_MEMORY
bdab39d3	92	#define CONFIG_CMD_SAVEENV
6c18eb98 JL	93	#define CONFIG_CMD_CONSOLE
	94	#define CONFIG_CMD_LOADS
	95	#define CONFIG_CMD_LOADB
	96	#define CONFIG_CMD_IMI
	97	#define CONFIG_CMD_CACHE
	98	#define CONFIG_CMD_REGINFO
	99	#define CONFIG_CMD_NET
	100	#define CONFIG_CMD_DHCP
	101	#define CONFIG_CMD_I2C
	102	#define CONFIG_CMD_DATE
c609719b WD	103
	104
	105	/*
	106	* Miscellaneous configurable options
	107	*/
6d0f6bcf	108	#define CONFIG_SYS_LONGHELP /* undef to save memory */
6d0f6bcf	109	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
c609719b WD	110
c609719b WD	111	/* Print Buffer Size */
6d0f6bcf	112	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
c609719b	113
6d0f6bcf JCPV	114	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	115	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
	116	#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* Default load address */
c609719b WD	117
	118
	119	/*-----------------------------------------------------------------------
	120	* PCI configuration
	121	*-----------------------------------------------------------------------
	122	*/
	123	#define CONFIG_PCI /* include pci support */
842033e6	124	#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
c609719b WD	125	#undef CONFIG_PCI_PNP
c609719b WD	126	#define CONFIG_PCI_SCAN_SHOW
c609719b	127	#define CONFIG_EEPRO100
6d0f6bcf	128	#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
7a8e9bed WD	129	#define CONFIG_EEPRO100_SROM_WRITE
	130
	131	#define PCI_ENET0_IOADDR 0xF0000000
	132	#define PCI_ENET0_MEMADDR 0xF0000000
c609719b	133
7a8e9bed WD	134	#define PCI_FIREWIRE_IOADDR 0xF1000000
	135	#define PCI_FIREWIRE_MEMADDR 0xF1000000
	136	/*
	137	#define PCI_ENET0_IOADDR 0xFE000000
c609719b	138	#define PCI_ENET0_MEMADDR 0x80000000
7a8e9bed	139
c609719b WD	140	#define PCI_FIREWIRE_IOADDR 0x81000000
c609719b WD	141	#define PCI_FIREWIRE_MEMADDR 0x81000000
7a8e9bed	142	*/
c609719b WD	143
	144	/*-----------------------------------------------------------------------
	145	* Start addresses for the final memory configuration
	146	* (Set up by the startup code)
6d0f6bcf	147	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
c609719b	148	*/
6d0f6bcf JCPV	149	#define CONFIG_SYS_SDRAM_BASE 0x00000000
	150	#define CONFIG_SYS_MAX_RAM_SIZE 0x10000000 /* 256MB */
	151	/#define CONFIG_SYS_VERY_BIG_RAM 1 /
c609719b	152
7a8e9bed WD	153	/* FLASH_BASE is FF800000, with 4MB on RCS0, but the reset vector
	154	* is actually located at FFF00100. Therefore, U-Boot is
	155	* physically located at 0xFFB0_0000, but is also mirrored at
	156	* 0xFFF0_0000.
c609719b	157	*/
6d0f6bcf	158	#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100
c609719b	159
6d0f6bcf	160	#define CONFIG_SYS_EUMB_ADDR 0xFC000000
c609719b	161
14d0a02a	162	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
c609719b	163
6d0f6bcf JCPV	164	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
6d0f6bcf JCPV	165	#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
c609719b	166
6d0f6bcf JCPV	167	/#define CONFIG_SYS_DRAM_TEST 1 /
	168	#define CONFIG_SYS_MEMTEST_START 0x00003000 /* memtest works on 0...256 MB */
	169	#define CONFIG_SYS_MEMTEST_END 0x0ff8ffa7 /* in SDRAM, skips exception */
c609719b WD	170	/* vectors and U-Boot */
	171
	172
	173	/*--------------------------------------------------------------------
	174	* Definitions for initial stack pointer and data area
	175	------------------------------------------------------------------/
6d0f6bcf	176	#define CONFIG_SYS_INIT_DATA_SIZE 128 /* Size in bytes reserved for */
c609719b	177	/* initial data */
6d0f6bcf	178	#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
553f0982 WD	179	#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
553f0982 WD	180	#define CONFIG_SYS_INIT_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_INIT_DATA_SIZE)
25ddd1fb	181	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
c609719b WD	182
	183	/*--------------------------------------------------------------------
	184	* NS16550 Configuration
	185	------------------------------------------------------------------/
6d0f6bcf JCPV	186	#define CONFIG_SYS_NS16550
6d0f6bcf JCPV	187	#define CONFIG_SYS_NS16550_SERIAL
c609719b	188
6d0f6bcf	189	#define CONFIG_SYS_NS16550_REG_SIZE 1
c609719b	190
7a8e9bed	191	#if (CONFIG_CONS_INDEX == 1 \|\| CONFIG_CONS_INDEX == 2)
6d0f6bcf	192	# define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
7a8e9bed	193	#else
6d0f6bcf	194	# define CONFIG_SYS_NS16550_CLK 33000000
7a8e9bed	195	#endif
c609719b	196
6d0f6bcf JCPV	197	#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_EUMB_ADDR + 0x4500)
	198	#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_EUMB_ADDR + 0x4600)
	199	#define CONFIG_SYS_NS16550_COM3 0xFF000000
	200	#define CONFIG_SYS_NS16550_COM4 0xFF000008
c609719b WD	201
	202	/*--------------------------------------------------------------------
	203	* Low Level Configuration Settings
	204	* (address mappings, register initial values, etc.)
	205	* You should know what you are doing if you make changes here.
	206	* For the detail description refer to the MPC8240 user's manual.
	207	------------------------------------------------------------------/
	208
	209	#define CONFIG_SYS_CLK_FREQ 33000000
c609719b	210
6d0f6bcf JCPV	211	/#define CONFIG_SYS_ETH_DEV_FN 0x7800 /
6d0f6bcf JCPV	212	/#define CONFIG_SYS_ETH_IOBASE 0x00104000 /
7a8e9bed WD	213
	214	/*--------------------------------------------------------------------
	215	* I2C Configuration
	216	------------------------------------------------------------------/
	217	#if 1
	218	#define CONFIG_HARD_I2C 1 /* To enable I2C support */
ea818dbb	219	#define CONFIG_SYS_I2C_SPEED 400000
6d0f6bcf	220	#define CONFIG_SYS_I2C_SLAVE 0x7F
7a8e9bed	221	#endif
c609719b	222
7a8e9bed WD	223	#define CONFIG_RTC_PCF8563 1 /* enable I2C support for */
7a8e9bed WD	224	/* Philips PCF8563 RTC */
6d0f6bcf	225	#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Philips PCF8563 RTC address */
c609719b WD	226
	227	/*--------------------------------------------------------------------
	228	* Memory Control Configuration Register values
	229	* - see sec. 4.12 of MPC8245 UM
	230	------------------------------------------------------------------/
	231
7a8e9bed	232	/** MCCR1 **/
6d0f6bcf JCPV	233	#define CONFIG_SYS_ROMNAL 0
6d0f6bcf JCPV	234	#define CONFIG_SYS_ROMFAL 10 /* (tacc=70ns)*mem_freq - 2,
7a8e9bed WD	235	mem_freq = 100MHz */
7a8e9bed WD	236
6d0f6bcf JCPV	237	#define CONFIG_SYS_BANK7_ROW 0 /* SDRAM bank 7-0 row address */
	238	#define CONFIG_SYS_BANK6_ROW 0 /* bit count */
	239	#define CONFIG_SYS_BANK5_ROW 0
	240	#define CONFIG_SYS_BANK4_ROW 0
	241	#define CONFIG_SYS_BANK3_ROW 0
	242	#define CONFIG_SYS_BANK2_ROW 0
	243	#define CONFIG_SYS_BANK1_ROW 2
	244	#define CONFIG_SYS_BANK0_ROW 2
c609719b	245
7a8e9bed	246	/** MCCR2, refresh interval clock cycles **/
6d0f6bcf	247	#define CONFIG_SYS_REFINT 480 /* 33 MHz SDRAM clock was 480 */
c609719b	248
7a8e9bed	249	/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4. */
6d0f6bcf	250	#define CONFIG_SYS_BSTOPRE 1023 /* burst to precharge[0..9], */
c609719b WD	251	/* sets open page interval */
c609719b WD	252
7a8e9bed	253	/** MCCR3 **/
6d0f6bcf	254	#define CONFIG_SYS_REFREC 7 /* Refresh to activate interval, trc */
c609719b	255
7a8e9bed	256	/** MCCR4 **/
6d0f6bcf JCPV	257	#define CONFIG_SYS_PRETOACT 2 /* trp */
	258	#define CONFIG_SYS_ACTTOPRE 7 /* trcd + (burst length - 1) + trdl */
	259	#define CONFIG_SYS_SDMODE_CAS_LAT 3 /* SDMODE CAS latancy */
	260	#define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE wrap type, sequential */
	261	#define CONFIG_SYS_ACTORW 2 /* trcd min */
	262	#define CONFIG_SYS_DBUS_SIZE2 1 /* set for 8-bit RCS1, clear for 32,64 */
	263	#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1
	264	#define CONFIG_SYS_EXTROM 0 /* we don't need extended ROM space */
	265	#define CONFIG_SYS_REGDIMM 0
c609719b WD	266
c609719b WD	267	/* calculate according to formula in sec. 6-22 of 8245 UM */
6d0f6bcf	268	#define CONFIG_SYS_PGMAX 50 /* how long the 8245 retains the */
c609719b WD	269	/* currently accessed page in memory */
	270	/* was 45 */
	271
6d0f6bcf	272	#define CONFIG_SYS_SDRAM_DSCD 0x20 /* SDRAM data in sample clock delay - note */
7a8e9bed	273	/* bits 7,6, and 3-0 MUST be 0 */
c609719b	274
7a8e9bed	275	#if 0
6d0f6bcf	276	#define CONFIG_SYS_DLL_MAX_DELAY 0x04
7a8e9bed	277	#else
6d0f6bcf	278	#define CONFIG_SYS_DLL_MAX_DELAY 0
7a8e9bed WD	279	#endif
7a8e9bed WD	280	#if 0 /* need for 33MHz SDRAM */
6d0f6bcf	281	#define CONFIG_SYS_DLL_EXTEND 0x80
7a8e9bed	282	#else
6d0f6bcf	283	#define CONFIG_SYS_DLL_EXTEND 0
7a8e9bed	284	#endif
6d0f6bcf	285	#define CONFIG_SYS_PCI_HOLD_DEL 0x20
c609719b WD	286
	287
	288	/* Memory bank settings.
	289	* Only bits 20-29 are actually used from these values to set the
	290	* start/end addresses. The upper two bits will always be 0, and the lower
	291	* 20 bits will be 0x00000 for a start address, or 0xfffff for an end
	292	* address. Refer to the MPC8245 user manual.
	293	*/
	294
6d0f6bcf JCPV	295	#define CONFIG_SYS_BANK0_START 0x00000000
	296	#define CONFIG_SYS_BANK0_END (CONFIG_SYS_MAX_RAM_SIZE/2 - 1)
	297	#define CONFIG_SYS_BANK0_ENABLE 1
	298	#define CONFIG_SYS_BANK1_START CONFIG_SYS_MAX_RAM_SIZE/2
	299	#define CONFIG_SYS_BANK1_END (CONFIG_SYS_MAX_RAM_SIZE - 1)
	300	#define CONFIG_SYS_BANK1_ENABLE 1
	301	#define CONFIG_SYS_BANK2_START 0x3ff00000 /* not available in this design */
	302	#define CONFIG_SYS_BANK2_END 0x3fffffff
	303	#define CONFIG_SYS_BANK2_ENABLE 0
	304	#define CONFIG_SYS_BANK3_START 0x3ff00000
	305	#define CONFIG_SYS_BANK3_END 0x3fffffff
	306	#define CONFIG_SYS_BANK3_ENABLE 0
	307	#define CONFIG_SYS_BANK4_START 0x3ff00000
	308	#define CONFIG_SYS_BANK4_END 0x3fffffff
	309	#define CONFIG_SYS_BANK4_ENABLE 0
	310	#define CONFIG_SYS_BANK5_START 0x3ff00000
	311	#define CONFIG_SYS_BANK5_END 0x3fffffff
	312	#define CONFIG_SYS_BANK5_ENABLE 0
	313	#define CONFIG_SYS_BANK6_START 0x3ff00000
	314	#define CONFIG_SYS_BANK6_END 0x3fffffff
	315	#define CONFIG_SYS_BANK6_ENABLE 0
	316	#define CONFIG_SYS_BANK7_START 0x3ff00000
	317	#define CONFIG_SYS_BANK7_END 0x3fffffff
	318	#define CONFIG_SYS_BANK7_ENABLE 0
c609719b	319
7a8e9bed WD	320	/--------------------------------------------------------------------/
	321	/* 4.4 - Output Driver Control Register */
	322	/--------------------------------------------------------------------/
6d0f6bcf	323	#define CONFIG_SYS_ODCR 0xe5
c609719b	324
7a8e9bed WD	325	/--------------------------------------------------------------------/
7a8e9bed WD	326	/* 4.8 - Error Handling Registers */
6d0f6bcf JCPV	327	/-------------------------------CONFIG_SYS_SDMODE_BURSTLEN-------------------------------------/
6d0f6bcf JCPV	328	#define CONFIG_SYS_ERRENR1 0x11 /* enable SDRAM refresh overflow error */
c609719b WD	329
c609719b WD	330	/* SDRAM 0-256 MB */
6d0f6bcf JCPV	331	#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \| BATL_PP_10 \| BATL_MEMCOHERENCE)
	332	/#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \| BATL_PP_10 \| BATL_CACHEINHIBIT) /
	333	#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \| BATU_BL_256M \| BATU_VS \| BATU_VP)
c609719b WD	334
c609719b WD	335	/* stack in dcache */
6d0f6bcf JCPV	336	#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR \| BATL_PP_10 \| BATL_MEMCOHERENCE)
6d0f6bcf JCPV	337	#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR \| BATU_BL_128K \| BATU_VS \| BATU_VP)
c609719b	338
7a8e9bed	339
6d0f6bcf JCPV	340	#define CONFIG_SYS_IBAT2L (CONFIG_SYS_SDRAM_BASE + 0x10000000 \| BATL_PP_10 \| BATL_MEMCOHERENCE)
6d0f6bcf JCPV	341	#define CONFIG_SYS_IBAT2U (CONFIG_SYS_SDRAM_BASE + 0x10000000\| BATU_BL_256M \| BATU_VS \| BATU_VP)
7a8e9bed	342
c609719b	343	/* PCI memory */
6d0f6bcf JCPV	344	/#define CONFIG_SYS_IBAT2L (0x80000000 \| BATL_PP_10 \| BATL_CACHEINHIBIT) /
6d0f6bcf JCPV	345	/#define CONFIG_SYS_IBAT2U (0x80000000 \| BATU_BL_256M \| BATU_VS \| BATU_VP) /
c609719b	346
7a8e9bed	347	/Flash, config addrs, etc. /
6d0f6bcf JCPV	348	#define CONFIG_SYS_IBAT3L (0xF0000000 \| BATL_PP_10 \| BATL_CACHEINHIBIT)
	349	#define CONFIG_SYS_IBAT3U (0xF0000000 \| BATU_BL_256M \| BATU_VS \| BATU_VP)
	350
	351	#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
	352	#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
	353	#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
	354	#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
	355	#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
	356	#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
	357	#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
	358	#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
c609719b WD	359
	360	/*
	361	* For booting Linux, the board info and command line data
	362	* have to be in the first 8 MB of memory, since this is
	363	* the maximum mapped by the Linux kernel during initialization.
	364	*/
6d0f6bcf	365	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
c609719b WD	366
c609719b WD	367	/*-----------------------------------------------------------------------
7a8e9bed WD	368	* FLASH organization
7a8e9bed WD	369	----------------------------------------------------------------------/
6d0f6bcf JCPV	370	#define CONFIG_SYS_FLASH_BASE 0xFF800000
6d0f6bcf JCPV	371	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max number of flash banks */
c609719b	372
7a8e9bed WD	373	/* NOTE: environment is not EMBEDDED in the u-boot code.
7a8e9bed WD	374	It's stored in flash in its own separate sector. */
5a1aceb0	375	#define CONFIG_ENV_IS_IN_FLASH 1
c609719b	376
7a8e9bed	377	#if 1 /* AMD AM29LV033C */
6d0f6bcf	378	#define CONFIG_SYS_MAX_FLASH_SECT 64 /* Max number of sectors in one bank */
0e8d1586 JCPV	379	#define CONFIG_ENV_ADDR 0xFFBF0000 /* flash sector SA63 */
0e8d1586 JCPV	380	#define CONFIG_ENV_SECT_SIZE (641024) / Size of the Environment Sector */
7a8e9bed	381	#else /* AMD AM29LV116D */
6d0f6bcf	382	#define CONFIG_SYS_MAX_FLASH_SECT 35 /* Max number of sectors in one bank */
0e8d1586 JCPV	383	#define CONFIG_ENV_ADDR 0xFF9FA000 /* flash sector SA33 */
0e8d1586 JCPV	384	#define CONFIG_ENV_SECT_SIZE (81024) / Size of the Environment Sector */
7a8e9bed WD	385	#endif /* #if */
7a8e9bed WD	386
0e8d1586 JCPV	387	#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE /* Size of the Environment */
0e8d1586 JCPV	388	#define CONFIG_ENV_OFFSET 0 /* starting right at the beginning */
c609719b	389
6d0f6bcf JCPV	390	#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
6d0f6bcf JCPV	391	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
c609719b	392
6d0f6bcf JCPV	393	#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
6d0f6bcf JCPV	394	#undef CONFIG_SYS_RAMBOOT
c609719b	395	#else
6d0f6bcf	396	#define CONFIG_SYS_RAMBOOT
c609719b WD	397	#endif
	398
	399
	400	/*-----------------------------------------------------------------------
	401	* Cache Configuration
	402	*/
6d0f6bcf	403	#define CONFIG_SYS_CACHELINE_SIZE 32
6c18eb98	404	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	405	# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
c609719b WD	406	#endif
c609719b WD	407
c609719b	408	#endif /* __CONFIG_H */