[people/ms/u-boot.git] / include / configs / vct.h

/*
 * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*
 * This file contains the configuration parameters for the VCT board
 * family:
 *
 * vct_premium
 * vct_premium_small
 * vct_premium_onenand
 * vct_premium_onenand_small
 * vct_platinum
 * vct_platinum_small
 * vct_platinum_onenand
 * vct_platinum_onenand_small
 * vct_platinumavc
 * vct_platinumavc_small
 * vct_platinumavc_onenand
 * vct_platinumavc_onenand_small
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#define CPU_CLOCK_RATE			324000000 /* Clock for the MIPS core */
#define CONFIG_SYS_MIPS_TIMER_FREQ	(CPU_CLOCK_RATE / 2)

#define CONFIG_SKIP_LOWLEVEL_INIT	/* SDRAM is initialized by the bootstrap code */

#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MONITOR_LEN		(256 << 10)
#define CONFIG_SYS_MALLOC_LEN		(1 << 20)
#define CONFIG_SYS_BOOTPARAMS_LEN	(128 << 10)
#define CONFIG_SYS_INIT_SP_OFFSET	0x400000

#if !defined(CONFIG_VCT_NAND) && !defined(CONFIG_VCT_ONENAND)
#define CONFIG_VCT_NOR
#endif

/*
 * UART
 */
#ifdef CONFIG_VCT_PLATINUMAVC
#define UART_1_BASE		0xBDC30000
#else
#define UART_1_BASE		0xBF89C000
#endif

#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	-4
#define CONFIG_SYS_NS16550_COM1		UART_1_BASE
#define CONFIG_CONS_INDEX		1
#define CONFIG_SYS_NS16550_CLK		921600

/*
 * SDRAM
 */
#define CONFIG_SYS_SDRAM_BASE		0x80000000
#define CONFIG_SYS_MBYTES_SDRAM		128
#define CONFIG_SYS_MEMTEST_START	0x80200000
#define CONFIG_SYS_MEMTEST_END		0x80400000
#define CONFIG_SYS_LOAD_ADDR		0x80400000	/* default load address */

#if defined(CONFIG_VCT_PREMIUM) || defined(CONFIG_VCT_PLATINUM)
#define CONFIG_NET_RETRY_COUNT		20
#endif

/*
 * Commands
 */
#if defined(CONFIG_CMD_USB)

/*
 * USB/EHCI
 */
#define CONFIG_USB_EHCI_VCT		/* on VCT platform		*/
#define CONFIG_EHCI_MMIO_BIG_ENDIAN
#define CONFIG_EHCI_DESC_BIG_ENDIAN
#define CONFIG_EHCI_IS_TDI
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* re-init HCD after CMD_RESET */
#endif /* CONFIG_CMD_USB */

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_CBSIZE	512		/* Console I/O Buffer Size	*/
#define CONFIG_TIMESTAMP			/* Print image info with timestamp */

/*
 * FLASH and environment organization
 */
#if defined(CONFIG_VCT_NOR)
#define CONFIG_FLASH_NOT_MEM_MAPPED

/*
 * We need special accessor functions for the CFI FLASH driver. This
 * can be enabled via the CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS option.
 */
#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS

/*
 * For the non-memory-mapped NOR FLASH, we need to define the
 * NOR FLASH area. This can't be detected via the addr2info()
 * function, since we check for flash access in the very early
 * U-Boot code, before the NOR FLASH is detected.
 */
#define CONFIG_FLASH_BASE		0xb0000000
#define CONFIG_FLASH_END		0xbfffffff

/*
 * CFI driver settings
 */
#define CONFIG_SYS_FLASH_CFI			/* The flash is CFI compatible	*/
#define CONFIG_FLASH_CFI_DRIVER		/* Use common CFI driver	*/
#define CONFIG_SYS_FLASH_CFI_AMD_RESET	1	/* Use AMD (Spansion) reset cmd */
#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT	/* no byte writes on IXP4xx	*/

#define CONFIG_SYS_FLASH_BASE		0xb0000000
#define CONFIG_SYS_FLASH_BANKS_LIST    { CONFIG_SYS_FLASH_BASE }
#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max number of sectors on one chip	*/

#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

#ifdef CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_SECT_SIZE	0x10000		/* size of one complete sector	*/
#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
#define	CONFIG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/

/* Address and size of Redundant Environment Sector	*/
#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
#endif /* CONFIG_ENV_IS_IN_FLASH */
#endif /* CONFIG_VCT_NOR */

#if defined(CONFIG_VCT_ONENAND)
#define CONFIG_USE_ONENAND_BOARD_INIT
#define	CONFIG_SYS_ONENAND_BASE		0x00000000	/* this is not real address */
#define CONFIG_SYS_FLASH_BASE		0x00000000
#define CONFIG_ENV_ADDR			(128 << 10)	/* after compr. U-Boot image */
#define	CONFIG_ENV_SIZE			(128 << 10)	/* erase size */
#endif /* CONFIG_VCT_ONENAND */

/*
 * I2C/EEPROM
 */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_SOFT		/* I2C bit-banged */
#define CONFIG_SYS_I2C_SOFT_SPEED	83000	/* 83 kHz is supposed to work */
#define CONFIG_SYS_I2C_SOFT_SLAVE	0x7f

/*
 * Software (bit-bang) I2C driver configuration
 */
#define CONFIG_SYS_GPIO_I2C_SCL		11
#define CONFIG_SYS_GPIO_I2C_SDA		10

#ifndef __ASSEMBLY__
int vct_gpio_dir(int pin, int dir);
void vct_gpio_set(int pin, int val);
int vct_gpio_get(int pin);
#endif

#define I2C_INIT	vct_gpio_dir(CONFIG_SYS_GPIO_I2C_SCL, 1)
#define I2C_ACTIVE	vct_gpio_dir(CONFIG_SYS_GPIO_I2C_SDA, 1)
#define I2C_TRISTATE	vct_gpio_dir(CONFIG_SYS_GPIO_I2C_SDA, 0)
#define I2C_READ	vct_gpio_get(CONFIG_SYS_GPIO_I2C_SDA)
#define I2C_SDA(bit)	vct_gpio_set(CONFIG_SYS_GPIO_I2C_SDA, bit)
#define I2C_SCL(bit)	vct_gpio_set(CONFIG_SYS_GPIO_I2C_SCL, bit)
#define I2C_DELAY	udelay(5)	/* 1/4 I2C clock duration */

#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50
/* CAT24WC32 */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2	/* Bytes of address		*/
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5	/* The Catalyst CAT24WC32 has	*/
					/* 32 byte page write mode using*/
					/* last 5 bits of the address	*/
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */

#define CONFIG_BOOTCOMMAND	"run test3"

/*
 * UBI configuration
 */
#if defined(CONFIG_VCT_ONENAND)
#define CONFIG_MTD_DEVICE		/* needed for mtdparts commands */
#define CONFIG_MTD_PARTITIONS
#endif

/*
 * We need a small, stripped down image to fit into the first 128k OneNAND
 * erase block (gzipped). This image only needs basic commands for FLASH
 * (NOR/OneNAND) usage and Linux kernel booting.
 */
#if defined(CONFIG_VCT_SMALL_IMAGE)
#undef CONFIG_SYS_I2C_SOFT
#undef CONFIG_SOURCE
#undef CONFIG_TIMESTAMP
#endif /* CONFIG_VCT_SMALL_IMAGE */

#endif  /* __CONFIG_H */
Commit	Line	Data
ae691e57 SR	1	/*
	2	* (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
	3	*
1a459660	4	* SPDX-License-Identifier: GPL-2.0+
ae691e57 SR	5	*/
	6
	7	/*
	8	* This file contains the configuration parameters for the VCT board
	9	* family:
	10	*
	11	* vct_premium
	12	* vct_premium_small
	13	* vct_premium_onenand
	14	* vct_premium_onenand_small
	15	* vct_platinum
	16	* vct_platinum_small
	17	* vct_platinum_onenand
	18	* vct_platinum_onenand_small
	19	* vct_platinumavc
	20	* vct_platinumavc_small
	21	* vct_platinumavc_onenand
	22	* vct_platinumavc_onenand_small
	23	*/
	24
	25	#ifndef __CONFIG_H
	26	#define __CONFIG_H
	27
ae691e57 SR	28	#define CPU_CLOCK_RATE 324000000 /* Clock for the MIPS core */
ae691e57 SR	29	#define CONFIG_SYS_MIPS_TIMER_FREQ (CPU_CLOCK_RATE / 2)
ae691e57 SR	30
	31	#define CONFIG_SKIP_LOWLEVEL_INIT /* SDRAM is initialized by the bootstrap code */
	32
14d0a02a	33	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
ae691e57	34	#define CONFIG_SYS_MONITOR_LEN (256 << 10)
ae691e57 SR	35	#define CONFIG_SYS_MALLOC_LEN (1 << 20)
	36	#define CONFIG_SYS_BOOTPARAMS_LEN (128 << 10)
	37	#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
	38
	39	#if !defined(CONFIG_VCT_NAND) && !defined(CONFIG_VCT_ONENAND)
	40	#define CONFIG_VCT_NOR
ae691e57 SR	41	#endif
	42
	43	/*
	44	* UART
	45	*/
294f10ca DZ	46	#ifdef CONFIG_VCT_PLATINUMAVC
	47	#define UART_1_BASE 0xBDC30000
	48	#else
	49	#define UART_1_BASE 0xBF89C000
	50	#endif
	51
	52	#define CONFIG_SYS_NS16550_SERIAL
294f10ca DZ	53	#define CONFIG_SYS_NS16550_REG_SIZE -4
	54	#define CONFIG_SYS_NS16550_COM1 UART_1_BASE
	55	#define CONFIG_CONS_INDEX 1
	56	#define CONFIG_SYS_NS16550_CLK 921600
ae691e57 SR	57
	58	/*
	59	* SDRAM
	60	*/
	61	#define CONFIG_SYS_SDRAM_BASE 0x80000000
	62	#define CONFIG_SYS_MBYTES_SDRAM 128
	63	#define CONFIG_SYS_MEMTEST_START 0x80200000
	64	#define CONFIG_SYS_MEMTEST_END 0x80400000
	65	#define CONFIG_SYS_LOAD_ADDR 0x80400000 /* default load address */
	66
	67	#if defined(CONFIG_VCT_PREMIUM) \|\| defined(CONFIG_VCT_PLATINUM)
ae691e57 SR	68	#define CONFIG_NET_RETRY_COUNT 20
	69	#endif
	70
	71	/*
	72	* Commands
	73	*/
ae691e57	74	#if defined(CONFIG_CMD_USB)
ae691e57 SR	75
	76	/*
	77	* USB/EHCI
	78	*/
ae691e57	79	#define CONFIG_USB_EHCI_VCT /* on VCT platform */
ae691e57 SR	80	#define CONFIG_EHCI_MMIO_BIG_ENDIAN
	81	#define CONFIG_EHCI_DESC_BIG_ENDIAN
	82	#define CONFIG_EHCI_IS_TDI
	83	#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* re-init HCD after CMD_RESET */
	84	#endif /* CONFIG_CMD_USB */
	85
ae691e57 SR	86	/*
	87	* BOOTP options
	88	*/
	89	#define CONFIG_BOOTP_BOOTFILESIZE
ae691e57 SR	90
	91	/*
	92	* Miscellaneous configurable options
	93	*/
ae691e57	94	#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
ae691e57	95	#define CONFIG_TIMESTAMP /* Print image info with timestamp */
ae691e57 SR	96
	97	/*
	98	* FLASH and environment organization
	99	*/
	100	#if defined(CONFIG_VCT_NOR)
ae691e57 SR	101	#define CONFIG_FLASH_NOT_MEM_MAPPED
	102
	103	/*
	104	* We need special accessor functions for the CFI FLASH driver. This
	105	* can be enabled via the CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS option.
	106	*/
	107	#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
	108
	109	/*
	110	* For the non-memory-mapped NOR FLASH, we need to define the
	111	* NOR FLASH area. This can't be detected via the addr2info()
	112	* function, since we check for flash access in the very early
	113	* U-Boot code, before the NOR FLASH is detected.
	114	*/
	115	#define CONFIG_FLASH_BASE 0xb0000000
	116	#define CONFIG_FLASH_END 0xbfffffff
	117
	118	/*
	119	* CFI driver settings
	120	*/
	121	#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
	122	#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
	123	#define CONFIG_SYS_FLASH_CFI_AMD_RESET 1 /* Use AMD (Spansion) reset cmd */
	124	#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT /* no byte writes on IXP4xx */
	125
	126	#define CONFIG_SYS_FLASH_BASE 0xb0000000
	127	#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
	128	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
	129	#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
	130
	131	#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
	132	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
	133
	134	#ifdef CONFIG_ENV_IS_IN_FLASH
	135	#define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
	136	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
	137	#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
	138
	139	/* Address and size of Redundant Environment Sector */
	140	#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
	141	#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
	142	#endif /* CONFIG_ENV_IS_IN_FLASH */
	143	#endif /* CONFIG_VCT_NOR */
	144
	145	#if defined(CONFIG_VCT_ONENAND)
	146	#define CONFIG_USE_ONENAND_BOARD_INIT
ae691e57 SR	147	#define CONFIG_SYS_ONENAND_BASE 0x00000000 /* this is not real address */
	148	#define CONFIG_SYS_FLASH_BASE 0x00000000
	149	#define CONFIG_ENV_ADDR (128 << 10) /* after compr. U-Boot image */
	150	#define CONFIG_ENV_SIZE (128 << 10) /* erase size */
	151	#endif /* CONFIG_VCT_ONENAND */
	152
ae691e57 SR	153	/*
	154	* I2C/EEPROM
	155	*/
ea818dbb HS	156	#define CONFIG_SYS_I2C
	157	#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
	158	#define CONFIG_SYS_I2C_SOFT_SPEED 83000 /* 83 kHz is supposed to work */
	159	#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7f
ae691e57 SR	160
	161	/*
	162	* Software (bit-bang) I2C driver configuration
	163	*/
	164	#define CONFIG_SYS_GPIO_I2C_SCL 11
	165	#define CONFIG_SYS_GPIO_I2C_SDA 10
	166
	167	#ifndef __ASSEMBLY__
	168	int vct_gpio_dir(int pin, int dir);
	169	void vct_gpio_set(int pin, int val);
	170	int vct_gpio_get(int pin);
	171	#endif
	172
	173	#define I2C_INIT vct_gpio_dir(CONFIG_SYS_GPIO_I2C_SCL, 1)
	174	#define I2C_ACTIVE vct_gpio_dir(CONFIG_SYS_GPIO_I2C_SDA, 1)
	175	#define I2C_TRISTATE vct_gpio_dir(CONFIG_SYS_GPIO_I2C_SDA, 0)
	176	#define I2C_READ vct_gpio_get(CONFIG_SYS_GPIO_I2C_SDA)
	177	#define I2C_SDA(bit) vct_gpio_set(CONFIG_SYS_GPIO_I2C_SDA, bit)
	178	#define I2C_SCL(bit) vct_gpio_set(CONFIG_SYS_GPIO_I2C_SCL, bit)
	179	#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
	180
	181	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
	182	/* CAT24WC32 */
	183	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
	184	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* The Catalyst CAT24WC32 has */
	185	/* 32 byte page write mode using*/
	186	/* last 5 bits of the address */
	187	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
	188
	189	#define CONFIG_BOOTCOMMAND "run test3"
ae691e57	190
ae691e57 SR	191	/*
	192	* UBI configuration
	193	*/
	194	#if defined(CONFIG_VCT_ONENAND)
942556a9	195	#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
ae691e57	196	#define CONFIG_MTD_PARTITIONS
ae691e57 SR	197	#endif
	198
	199	/*
	200	* We need a small, stripped down image to fit into the first 128k OneNAND
	201	* erase block (gzipped). This image only needs basic commands for FLASH
	202	* (NOR/OneNAND) usage and Linux kernel booting.
	203	*/
	204	#if defined(CONFIG_VCT_SMALL_IMAGE)
ea818dbb	205	#undef CONFIG_SYS_I2C_SOFT
74de7aef	206	#undef CONFIG_SOURCE
ae691e57 SR	207	#undef CONFIG_TIMESTAMP
	208	#endif /* CONFIG_VCT_SMALL_IMAGE */
	209
	210	#endif /* __CONFIG_H */