[people/ms/u-boot.git] / include / configs / vct.h

/*
 * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*
 * This file contains the configuration parameters for the VCT board
 * family:
 *
 * vct_premium
 * vct_premium_small
 * vct_premium_onenand
 * vct_premium_onenand_small
 * vct_platinum
 * vct_platinum_small
 * vct_platinum_onenand
 * vct_platinum_onenand_small
 * vct_platinumavc
 * vct_platinumavc_small
 * vct_platinumavc_onenand
 * vct_platinumavc_onenand_small
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#define CONFIG_DISPLAY_BOARDINFO

#define CPU_CLOCK_RATE			324000000 /* Clock for the MIPS core */
#define CONFIG_SYS_MIPS_TIMER_FREQ	(CPU_CLOCK_RATE / 2)

#define CONFIG_SKIP_LOWLEVEL_INIT	/* SDRAM is initialized by the bootstrap code */

#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MONITOR_LEN		(256 << 10)
#define CONFIG_SYS_MALLOC_LEN		(1 << 20)
#define CONFIG_SYS_BOOTPARAMS_LEN	(128 << 10)
#define CONFIG_SYS_INIT_SP_OFFSET	0x400000

#if !defined(CONFIG_VCT_NAND) && !defined(CONFIG_VCT_ONENAND)
#define CONFIG_VCT_NOR
#else
#define CONFIG_SYS_NO_FLASH
#endif

/*
 * UART
 */
#ifdef CONFIG_VCT_PLATINUMAVC
#define UART_1_BASE		0xBDC30000
#else
#define UART_1_BASE		0xBF89C000
#endif

#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	-4
#define CONFIG_SYS_NS16550_COM1		UART_1_BASE
#define CONFIG_CONS_INDEX		1
#define CONFIG_SYS_NS16550_CLK		921600
#define CONFIG_BAUDRATE			115200

/*
 * SDRAM
 */
#define CONFIG_SYS_SDRAM_BASE		0x80000000
#define CONFIG_SYS_MBYTES_SDRAM		128
#define CONFIG_SYS_MEMTEST_START	0x80200000
#define CONFIG_SYS_MEMTEST_END		0x80400000
#define CONFIG_SYS_LOAD_ADDR		0x80400000	/* default load address */

#if defined(CONFIG_VCT_PREMIUM) || defined(CONFIG_VCT_PLATINUM)
/*
 * SMSC91C11x Network Card
 */
#define CONFIG_SMC911X
#define CONFIG_SMC911X_BASE	0x00000000
#define CONFIG_SMC911X_32_BIT
#define CONFIG_NET_RETRY_COUNT		20
#endif

/*
 * Commands
 */
#define CONFIG_CMD_EEPROM

/*
 * Only Premium/Platinum have ethernet support right now
 */
#if (defined(CONFIG_VCT_PREMIUM) || defined(CONFIG_VCT_PLATINUM)) && \
	!defined(CONFIG_VCT_SMALL_IMAGE)
#endif

/*
 * Only Premium/Platinum have USB-EHCI support right now
 */
#if (defined(CONFIG_VCT_PREMIUM) || defined(CONFIG_VCT_PLATINUM)) && \
	!defined(CONFIG_VCT_SMALL_IMAGE)
#endif

#if defined(CONFIG_CMD_USB)
#define CONFIG_USB_STORAGE
#define CONFIG_DOS_PARTITION
#define CONFIG_ISO_PARTITION

#define CONFIG_SUPPORT_VFAT

/*
 * USB/EHCI
 */
#define CONFIG_USB_EHCI			/* Enable EHCI USB support	*/
#define CONFIG_USB_EHCI_VCT		/* on VCT platform		*/
#define CONFIG_EHCI_MMIO_BIG_ENDIAN
#define CONFIG_EHCI_DESC_BIG_ENDIAN
#define CONFIG_EHCI_IS_TDI
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* re-init HCD after CMD_RESET */
#endif /* CONFIG_CMD_USB */

#if defined(CONFIG_VCT_NAND)
#define CONFIG_CMD_NAND
#endif

#if defined(CONFIG_VCT_ONENAND)
#define CONFIG_CMD_ONENAND
#endif

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_SUBNETMASK

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
#define CONFIG_SYS_CBSIZE	512		/* Console I/O Buffer Size	*/
#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE + \
				 sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
#define CONFIG_TIMESTAMP			/* Print image info with timestamp */
#define CONFIG_CMDLINE_EDITING			/* add command line history	*/
#define CONFIG_SYS_CONSOLE_INFO_QUIET		/* don't print console @ startup*/

/*
 * FLASH and environment organization
 */
#if defined(CONFIG_VCT_NOR)
#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_FLASH_NOT_MEM_MAPPED

/*
 * We need special accessor functions for the CFI FLASH driver. This
 * can be enabled via the CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS option.
 */
#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS

/*
 * For the non-memory-mapped NOR FLASH, we need to define the
 * NOR FLASH area. This can't be detected via the addr2info()
 * function, since we check for flash access in the very early
 * U-Boot code, before the NOR FLASH is detected.
 */
#define CONFIG_FLASH_BASE		0xb0000000
#define CONFIG_FLASH_END		0xbfffffff

/*
 * CFI driver settings
 */
#define CONFIG_SYS_FLASH_CFI			/* The flash is CFI compatible	*/
#define CONFIG_FLASH_CFI_DRIVER		/* Use common CFI driver	*/
#define CONFIG_SYS_FLASH_CFI_AMD_RESET	1	/* Use AMD (Spansion) reset cmd */
#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT	/* no byte writes on IXP4xx	*/

#define CONFIG_SYS_FLASH_BASE		0xb0000000
#define CONFIG_SYS_FLASH_BANKS_LIST    { CONFIG_SYS_FLASH_BASE }
#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max number of sectors on one chip	*/

#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

#ifdef CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_SECT_SIZE	0x10000		/* size of one complete sector	*/
#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
#define	CONFIG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/

/* Address and size of Redundant Environment Sector	*/
#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
#endif /* CONFIG_ENV_IS_IN_FLASH */
#endif /* CONFIG_VCT_NOR */

#if defined(CONFIG_VCT_ONENAND)
#define CONFIG_USE_ONENAND_BOARD_INIT
#define	CONFIG_ENV_IS_IN_ONENAND
#define	CONFIG_SYS_ONENAND_BASE		0x00000000	/* this is not real address */
#define CONFIG_SYS_FLASH_BASE		0x00000000
#define CONFIG_ENV_ADDR			(128 << 10)	/* after compr. U-Boot image */
#define	CONFIG_ENV_SIZE			(128 << 10)	/* erase size */
#endif /* CONFIG_VCT_ONENAND */

/*
 * I2C/EEPROM
 */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_SOFT		/* I2C bit-banged */
#define CONFIG_SYS_I2C_SOFT_SPEED	83000	/* 83 kHz is supposed to work */
#define CONFIG_SYS_I2C_SOFT_SLAVE	0x7f

/*
 * Software (bit-bang) I2C driver configuration
 */
#define CONFIG_SYS_GPIO_I2C_SCL		11
#define CONFIG_SYS_GPIO_I2C_SDA		10

#ifndef __ASSEMBLY__
int vct_gpio_dir(int pin, int dir);
void vct_gpio_set(int pin, int val);
int vct_gpio_get(int pin);
#endif

#define I2C_INIT	vct_gpio_dir(CONFIG_SYS_GPIO_I2C_SCL, 1)
#define I2C_ACTIVE	vct_gpio_dir(CONFIG_SYS_GPIO_I2C_SDA, 1)
#define I2C_TRISTATE	vct_gpio_dir(CONFIG_SYS_GPIO_I2C_SDA, 0)
#define I2C_READ	vct_gpio_get(CONFIG_SYS_GPIO_I2C_SDA)
#define I2C_SDA(bit)	vct_gpio_set(CONFIG_SYS_GPIO_I2C_SDA, bit)
#define I2C_SCL(bit)	vct_gpio_set(CONFIG_SYS_GPIO_I2C_SCL, bit)
#define I2C_DELAY	udelay(5)	/* 1/4 I2C clock duration */

#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50
/* CAT24WC32 */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2	/* Bytes of address		*/
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5	/* The Catalyst CAT24WC32 has	*/
					/* 32 byte page write mode using*/
					/* last 5 bits of the address	*/
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */

#define CONFIG_BOOTCOMMAND	"run test3"

/*
 * UBI configuration
 */
#if defined(CONFIG_VCT_ONENAND)
#define CONFIG_SYS_USE_UBI
#define	CONFIG_CMD_JFFS2
#define	CONFIG_CMD_UBI
#define	CONFIG_RBTREE
#define CONFIG_MTD_DEVICE		/* needed for mtdparts commands */
#define CONFIG_MTD_PARTITIONS
#define CONFIG_CMD_MTDPARTS

#define MTDIDS_DEFAULT		"onenand0=onenand"
#define MTDPARTS_DEFAULT	"mtdparts=onenand:128k(u-boot),"	\
					"128k(env),"		\
					"20m(kernel),"		\
					"-(rootfs)"
#endif

/*
 * We need a small, stripped down image to fit into the first 128k OneNAND
 * erase block (gzipped). This image only needs basic commands for FLASH
 * (NOR/OneNAND) usage and Linux kernel booting.
 */
#if defined(CONFIG_VCT_SMALL_IMAGE)
#undef CONFIG_CMD_BEDBUG
#undef CONFIG_CMD_EEPROM
#undef CONFIG_CMD_EEPROM
#undef CONFIG_CMD_IRQ
#undef CONFIG_CMD_LOADY
#undef CONFIG_CMD_REGINFO
#undef CONFIG_CMD_STRINGS
#undef CONFIG_CMD_TERMINAL

#undef CONFIG_SMC911X
#undef CONFIG_SYS_I2C_SOFT
#undef CONFIG_SOURCE
#undef CONFIG_SYS_LONGHELP
#undef CONFIG_TIMESTAMP
#endif /* CONFIG_VCT_SMALL_IMAGE */

#endif  /* __CONFIG_H */
Commit	Line	Data
ae691e57 SR	1	/*
	2	* (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
	3	*
1a459660	4	* SPDX-License-Identifier: GPL-2.0+
ae691e57 SR	5	*/
	6
	7	/*
	8	* This file contains the configuration parameters for the VCT board
	9	* family:
	10	*
	11	* vct_premium
	12	* vct_premium_small
	13	* vct_premium_onenand
	14	* vct_premium_onenand_small
	15	* vct_platinum
	16	* vct_platinum_small
	17	* vct_platinum_onenand
	18	* vct_platinum_onenand_small
	19	* vct_platinumavc
	20	* vct_platinumavc_small
	21	* vct_platinumavc_onenand
	22	* vct_platinumavc_onenand_small
	23	*/
	24
	25	#ifndef __CONFIG_H
	26	#define __CONFIG_H
	27
d146e36c DS	28	#define CONFIG_DISPLAY_BOARDINFO
d146e36c DS	29
ae691e57 SR	30	#define CPU_CLOCK_RATE 324000000 /* Clock for the MIPS core */
ae691e57 SR	31	#define CONFIG_SYS_MIPS_TIMER_FREQ (CPU_CLOCK_RATE / 2)
ae691e57 SR	32
	33	#define CONFIG_SKIP_LOWLEVEL_INIT /* SDRAM is initialized by the bootstrap code */
	34
14d0a02a	35	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
ae691e57	36	#define CONFIG_SYS_MONITOR_LEN (256 << 10)
ae691e57 SR	37	#define CONFIG_SYS_MALLOC_LEN (1 << 20)
	38	#define CONFIG_SYS_BOOTPARAMS_LEN (128 << 10)
	39	#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
	40
	41	#if !defined(CONFIG_VCT_NAND) && !defined(CONFIG_VCT_ONENAND)
	42	#define CONFIG_VCT_NOR
	43	#else
	44	#define CONFIG_SYS_NO_FLASH
	45	#endif
	46
	47	/*
	48	* UART
	49	*/
294f10ca DZ	50	#ifdef CONFIG_VCT_PLATINUMAVC
	51	#define UART_1_BASE 0xBDC30000
	52	#else
	53	#define UART_1_BASE 0xBF89C000
	54	#endif
	55
	56	#define CONFIG_SYS_NS16550_SERIAL
294f10ca DZ	57	#define CONFIG_SYS_NS16550_REG_SIZE -4
	58	#define CONFIG_SYS_NS16550_COM1 UART_1_BASE
	59	#define CONFIG_CONS_INDEX 1
	60	#define CONFIG_SYS_NS16550_CLK 921600
ae691e57	61	#define CONFIG_BAUDRATE 115200
ae691e57 SR	62
	63	/*
	64	* SDRAM
	65	*/
	66	#define CONFIG_SYS_SDRAM_BASE 0x80000000
	67	#define CONFIG_SYS_MBYTES_SDRAM 128
	68	#define CONFIG_SYS_MEMTEST_START 0x80200000
	69	#define CONFIG_SYS_MEMTEST_END 0x80400000
	70	#define CONFIG_SYS_LOAD_ADDR 0x80400000 /* default load address */
	71
	72	#if defined(CONFIG_VCT_PREMIUM) \|\| defined(CONFIG_VCT_PLATINUM)
	73	/*
	74	* SMSC91C11x Network Card
	75	*/
736fead8 BW	76	#define CONFIG_SMC911X
	77	#define CONFIG_SMC911X_BASE 0x00000000
	78	#define CONFIG_SMC911X_32_BIT
ae691e57 SR	79	#define CONFIG_NET_RETRY_COUNT 20
	80	#endif
	81
	82	/*
	83	* Commands
	84	*/
ae691e57	85	#define CONFIG_CMD_EEPROM
ae691e57 SR	86
	87	/*
	88	* Only Premium/Platinum have ethernet support right now
	89	*/
383015b2 DS	90	#if (defined(CONFIG_VCT_PREMIUM) \|\| defined(CONFIG_VCT_PLATINUM)) && \
383015b2 DS	91	!defined(CONFIG_VCT_SMALL_IMAGE)
ae691e57 SR	92	#endif
	93
	94	/*
	95	* Only Premium/Platinum have USB-EHCI support right now
	96	*/
383015b2 DS	97	#if (defined(CONFIG_VCT_PREMIUM) \|\| defined(CONFIG_VCT_PLATINUM)) && \
383015b2 DS	98	!defined(CONFIG_VCT_SMALL_IMAGE)
ae691e57 SR	99	#endif
	100
	101	#if defined(CONFIG_CMD_USB)
	102	#define CONFIG_USB_STORAGE
	103	#define CONFIG_DOS_PARTITION
	104	#define CONFIG_ISO_PARTITION
	105
	106	#define CONFIG_SUPPORT_VFAT
	107
	108	/*
	109	* USB/EHCI
	110	*/
	111	#define CONFIG_USB_EHCI /* Enable EHCI USB support */
	112	#define CONFIG_USB_EHCI_VCT /* on VCT platform */
ae691e57 SR	113	#define CONFIG_EHCI_MMIO_BIG_ENDIAN
	114	#define CONFIG_EHCI_DESC_BIG_ENDIAN
	115	#define CONFIG_EHCI_IS_TDI
	116	#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* re-init HCD after CMD_RESET */
	117	#endif /* CONFIG_CMD_USB */
	118
ae691e57 SR	119	#if defined(CONFIG_VCT_NAND)
	120	#define CONFIG_CMD_NAND
	121	#endif
	122
	123	#if defined(CONFIG_VCT_ONENAND)
	124	#define CONFIG_CMD_ONENAND
	125	#endif
	126
	127	/*
	128	* BOOTP options
	129	*/
	130	#define CONFIG_BOOTP_BOOTFILESIZE
	131	#define CONFIG_BOOTP_BOOTPATH
	132	#define CONFIG_BOOTP_GATEWAY
	133	#define CONFIG_BOOTP_HOSTNAME
	134	#define CONFIG_BOOTP_SUBNETMASK
	135
	136	/*
	137	* Miscellaneous configurable options
	138	*/
	139	#define CONFIG_SYS_LONGHELP /* undef to save memory */
ae691e57 SR	140	#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
	141	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
	142	sizeof(CONFIG_SYS_PROMPT) + 16)
	143	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	144	#define CONFIG_TIMESTAMP /* Print image info with timestamp */
	145	#define CONFIG_CMDLINE_EDITING /* add command line history */
	146	#define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup*/
	147
	148	/*
	149	* FLASH and environment organization
	150	*/
	151	#if defined(CONFIG_VCT_NOR)
	152	#define CONFIG_ENV_IS_IN_FLASH
	153	#define CONFIG_FLASH_NOT_MEM_MAPPED
	154
	155	/*
	156	* We need special accessor functions for the CFI FLASH driver. This
	157	* can be enabled via the CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS option.
	158	*/
	159	#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
	160
	161	/*
	162	* For the non-memory-mapped NOR FLASH, we need to define the
	163	* NOR FLASH area. This can't be detected via the addr2info()
	164	* function, since we check for flash access in the very early
	165	* U-Boot code, before the NOR FLASH is detected.
	166	*/
	167	#define CONFIG_FLASH_BASE 0xb0000000
	168	#define CONFIG_FLASH_END 0xbfffffff
	169
	170	/*
	171	* CFI driver settings
	172	*/
	173	#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
	174	#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
	175	#define CONFIG_SYS_FLASH_CFI_AMD_RESET 1 /* Use AMD (Spansion) reset cmd */
	176	#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT /* no byte writes on IXP4xx */
	177
	178	#define CONFIG_SYS_FLASH_BASE 0xb0000000
	179	#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
	180	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
	181	#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
	182
	183	#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
	184	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
	185
	186	#ifdef CONFIG_ENV_IS_IN_FLASH
	187	#define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
	188	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
	189	#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
	190
	191	/* Address and size of Redundant Environment Sector */
	192	#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
	193	#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
	194	#endif /* CONFIG_ENV_IS_IN_FLASH */
	195	#endif /* CONFIG_VCT_NOR */
	196
	197	#if defined(CONFIG_VCT_ONENAND)
	198	#define CONFIG_USE_ONENAND_BOARD_INIT
	199	#define CONFIG_ENV_IS_IN_ONENAND
	200	#define CONFIG_SYS_ONENAND_BASE 0x00000000 /* this is not real address */
	201	#define CONFIG_SYS_FLASH_BASE 0x00000000
	202	#define CONFIG_ENV_ADDR (128 << 10) /* after compr. U-Boot image */
	203	#define CONFIG_ENV_SIZE (128 << 10) /* erase size */
204	#endif /* CONFIG_VCT_ONENAND */
205
ae691e57 SR	206	/*
	207	* I2C/EEPROM
	208	*/
ea818dbb HS	209	#define CONFIG_SYS_I2C
	210	#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
	211	#define CONFIG_SYS_I2C_SOFT_SPEED 83000 /* 83 kHz is supposed to work */
	212	#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7f
ae691e57 SR	213
	214	/*
	215	* Software (bit-bang) I2C driver configuration
	216	*/
	217	#define CONFIG_SYS_GPIO_I2C_SCL 11
	218	#define CONFIG_SYS_GPIO_I2C_SDA 10
	219
	220	#ifndef __ASSEMBLY__
	221	int vct_gpio_dir(int pin, int dir);
	222	void vct_gpio_set(int pin, int val);
	223	int vct_gpio_get(int pin);
	224	#endif
	225
	226	#define I2C_INIT vct_gpio_dir(CONFIG_SYS_GPIO_I2C_SCL, 1)
	227	#define I2C_ACTIVE vct_gpio_dir(CONFIG_SYS_GPIO_I2C_SDA, 1)
	228	#define I2C_TRISTATE vct_gpio_dir(CONFIG_SYS_GPIO_I2C_SDA, 0)
	229	#define I2C_READ vct_gpio_get(CONFIG_SYS_GPIO_I2C_SDA)
	230	#define I2C_SDA(bit) vct_gpio_set(CONFIG_SYS_GPIO_I2C_SDA, bit)
	231	#define I2C_SCL(bit) vct_gpio_set(CONFIG_SYS_GPIO_I2C_SCL, bit)
	232	#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
	233
	234	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
	235	/* CAT24WC32 */
	236	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
	237	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* The Catalyst CAT24WC32 has */
	238	/* 32 byte page write mode using*/
	239	/* last 5 bits of the address */
	240	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
	241
	242	#define CONFIG_BOOTCOMMAND "run test3"
ae691e57	243
ae691e57 SR	244	/*
	245	* UBI configuration
	246	*/
	247	#if defined(CONFIG_VCT_ONENAND)
	248	#define CONFIG_SYS_USE_UBI
	249	#define CONFIG_CMD_JFFS2
	250	#define CONFIG_CMD_UBI
	251	#define CONFIG_RBTREE
942556a9	252	#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
ae691e57	253	#define CONFIG_MTD_PARTITIONS
68d7d651	254	#define CONFIG_CMD_MTDPARTS
ae691e57 SR	255
	256	#define MTDIDS_DEFAULT "onenand0=onenand"
	257	#define MTDPARTS_DEFAULT "mtdparts=onenand:128k(u-boot)," \
	258	"128k(env)," \
	259	"20m(kernel)," \
	260	"-(rootfs)"
	261	#endif
	262
	263	/*
	264	* We need a small, stripped down image to fit into the first 128k OneNAND
	265	* erase block (gzipped). This image only needs basic commands for FLASH
	266	* (NOR/OneNAND) usage and Linux kernel booting.
	267	*/
	268	#if defined(CONFIG_VCT_SMALL_IMAGE)
74de7aef	269	#undef CONFIG_CMD_BEDBUG
74de7aef	270	#undef CONFIG_CMD_EEPROM
ae691e57	271	#undef CONFIG_CMD_EEPROM
ae691e57	272	#undef CONFIG_CMD_IRQ
74de7aef	273	#undef CONFIG_CMD_LOADY
ae691e57 SR	274	#undef CONFIG_CMD_REGINFO
	275	#undef CONFIG_CMD_STRINGS
	276	#undef CONFIG_CMD_TERMINAL
ae691e57	277
736fead8	278	#undef CONFIG_SMC911X
ea818dbb	279	#undef CONFIG_SYS_I2C_SOFT
74de7aef	280	#undef CONFIG_SOURCE
ae691e57 SR	281	#undef CONFIG_SYS_LONGHELP
	282	#undef CONFIG_TIMESTAMP
	283	#endif /* CONFIG_VCT_SMALL_IMAGE */
	284
	285	#endif /* __CONFIG_H */