[people/ms/u-boot.git] / include / configs / ve8313.h

/*
 * Copyright (C) Freescale Semiconductor, Inc. 2006.
 *
 * (C) Copyright 2010
 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */
/*
 * ve8313 board configuration file
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 */
#define CONFIG_E300		1
#define CONFIG_MPC831x		1
#define CONFIG_MPC8313		1
#define CONFIG_VE8313		1

#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE	0xfe000000
#endif

#define CONFIG_PCI_INDIRECT_BRIDGE 1
#define CONFIG_FSL_ELBC		1

#define CONFIG_BOARD_EARLY_INIT_F	1

/*
 * On-board devices
 *
 */
#define CONFIG_83XX_CLKIN	32000000	/* in Hz */

#define CONFIG_SYS_CLK_FREQ	CONFIG_83XX_CLKIN

#define CONFIG_SYS_IMMR		0xE0000000

#define CONFIG_SYS_MEMTEST_START	0x00001000
#define CONFIG_SYS_MEMTEST_END		0x07000000

#define CONFIG_SYS_ACR_PIPE_DEP		3	/* Arbiter pipeline depth */
#define CONFIG_SYS_ACR_RPTCNT		3	/* Arbiter repeat count */

/*
 * Device configurations
 */

/*
 * DDR Setup
 */
#define CONFIG_SYS_DDR_BASE		0x00000000 /* DDR is system memory*/
#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
#define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE

/*
 * Manually set up DDR parameters, as this board does not
 * have the SPD connected to I2C.
 */
#define CONFIG_SYS_DDR_SIZE	128	/* MB */
#define CONFIG_SYS_DDR_CS0_CONFIG	(CSCONFIG_EN \
				| CSCONFIG_AP \
				| CSCONFIG_ODT_RD_NEVER \
				| CSCONFIG_ODT_WR_ALL \
				| CSCONFIG_ROW_BIT_13 \
				| CSCONFIG_COL_BIT_10)
				/* 0x80840102 */

#define CONFIG_SYS_DDR_TIMING_3	0x00000000
#define CONFIG_SYS_DDR_TIMING_0	((0 << TIMING_CFG0_RWT_SHIFT) \
				| (0 << TIMING_CFG0_WRT_SHIFT) \
				| (3 << TIMING_CFG0_RRT_SHIFT) \
				| (2 << TIMING_CFG0_WWT_SHIFT) \
				| (7 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
				| (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
				| (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
				| (2 << TIMING_CFG0_MRS_CYC_SHIFT))
				/* 0x0e720802 */
#define CONFIG_SYS_DDR_TIMING_1	((2 << TIMING_CFG1_PRETOACT_SHIFT) \
				| (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \
				| (2 << TIMING_CFG1_ACTTORW_SHIFT) \
				| (5 << TIMING_CFG1_CASLAT_SHIFT) \
				| (6 << TIMING_CFG1_REFREC_SHIFT) \
				| (2 << TIMING_CFG1_WRREC_SHIFT) \
				| (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
				| (2 << TIMING_CFG1_WRTORD_SHIFT))
				/* 0x26256222 */
#define CONFIG_SYS_DDR_TIMING_2	((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
				| (5 << TIMING_CFG2_CPO_SHIFT) \
				| (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
				| (1 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
				| (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
				| (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
				| (7 << TIMING_CFG2_FOUR_ACT_SHIFT))
				/* 0x029028c7 */
#define CONFIG_SYS_DDR_INTERVAL	((0x320 << SDRAM_INTERVAL_REFINT_SHIFT) \
				| (0x2000 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
				/* 0x03202000 */
#define CONFIG_SYS_SDRAM_CFG	(SDRAM_CFG_SREN \
				| SDRAM_CFG_SDRAM_TYPE_DDR2 \
				| SDRAM_CFG_DBW_32)
				/* 0x43080000 */
#define CONFIG_SYS_SDRAM_CFG2	0x00401000
#define CONFIG_SYS_DDR_MODE	((0x4440 << SDRAM_MODE_ESD_SHIFT) \
				| (0x0232 << SDRAM_MODE_SD_SHIFT))
				/* 0x44400232 */
#define CONFIG_SYS_DDR_MODE_2	0x8000C000

#define CONFIG_SYS_DDR_CLK_CNTL	DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
				/*0x02000000*/
#define CONFIG_SYS_DDRCDR_VALUE	(DDRCDR_EN \
				| DDRCDR_PZ_NOMZ \
				| DDRCDR_NZ_NOMZ \
				| DDRCDR_M_ODR)
				/* 0x73000002 */

/*
 * FLASH on the Local Bus
 */
#define CONFIG_SYS_FLASH_CFI		/* use the Common Flash Interface */
#define CONFIG_FLASH_CFI_DRIVER		/* use the CFI driver */
#define CONFIG_SYS_FLASH_BASE		0xFE000000
#define CONFIG_SYS_FLASH_SIZE		32	/* size in MB */
#define CONFIG_SYS_FLASH_EMPTY_INFO		/* display empty sectors */
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	/* buffer up multiple bytes */

#define CONFIG_SYS_NOR_BR_PRELIM	(CONFIG_SYS_FLASH_BASE \
					| BR_PS_16	/* 16 bit */ \
					| BR_MS_GPCM	/* MSEL = GPCM */ \
					| BR_V)		/* valid */
#define CONFIG_SYS_NOR_OR_PRELIM	(MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
					| OR_GPCM_CSNT \
					| OR_GPCM_ACS_DIV4 \
					| OR_GPCM_SCY_5 \
					| OR_GPCM_TRLX_SET \
					| OR_GPCM_EAD)
					/* 0xfe000c55 */

#define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_LBLAWAR0_PRELIM	(LBLAWAR_EN | LBLAWAR_32MB)

#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT	256		/* sectors per dev */

#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */

#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */

#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#define CONFIG_SYS_RAMBOOT
#endif

#define CONFIG_SYS_INIT_RAM_LOCK	1
#define CONFIG_SYS_INIT_RAM_ADDR	0xFD000000 /* Initial RAM address */
#define CONFIG_SYS_INIT_RAM_SIZE	0x1000	/* Size of used area in RAM*/

#define CONFIG_SYS_GBL_DATA_OFFSET	\
			(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
#define CONFIG_SYS_MONITOR_LEN		(384 * 1024)
#define CONFIG_SYS_MALLOC_LEN		(512 * 1024)

/*
 * Local Bus LCRR and LBCR regs
 */
#define CONFIG_SYS_LCRR_EADC	LCRR_EADC_3
#define CONFIG_SYS_LCRR_CLKDIV	LCRR_CLKDIV_2

#define CONFIG_SYS_LBC_LBCR	0x00040000

#define CONFIG_SYS_LBC_MRTPR	0x20000000

/*
 * NAND settings
 */
#define CONFIG_SYS_NAND_BASE		0x61000000
#define CONFIG_SYS_MAX_NAND_DEVICE	1
#define CONFIG_CMD_NAND 1
#define CONFIG_NAND_FSL_ELBC 1
#define CONFIG_SYS_NAND_BLOCK_SIZE 16384

#define CONFIG_SYS_NAND_BR_PRELIM	(CONFIG_SYS_NAND_BASE \
					| BR_PS_8		\
					| BR_DECC_CHK_GEN	\
					| BR_MS_FCM		\
					| BR_V)	/* valid */
					/* 0x61000c21 */
#define CONFIG_SYS_NAND_OR_PRELIM	(OR_AM_32KB \
					| OR_FCM_BCTLD \
					| OR_FCM_CHT \
					| OR_FCM_SCY_2 \
					| OR_FCM_RST \
					| OR_FCM_TRLX)
					/* 0xffff90ac */

#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM
#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM
#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM
#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM

#define CONFIG_SYS_LBLAWBAR1_PRELIM	CONFIG_SYS_NAND_BASE
#define CONFIG_SYS_LBLAWAR1_PRELIM	(LBLAWAR_EN | LBLAWAR_32KB)

#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM

/* CS2 NvRAM */
#define CONFIG_SYS_BR2_PRELIM	(0x60000000 \
				| BR_PS_8 \
				| BR_V)
				/* 0x60000801 */
#define CONFIG_SYS_OR2_PRELIM	(OR_AM_128KB \
				| OR_GPCM_CSNT \
				| OR_GPCM_XACS \
				| OR_GPCM_SCY_3 \
				| OR_GPCM_TRLX_SET \
				| OR_GPCM_EHTR_SET \
				| OR_GPCM_EAD)
				/* 0xfffe0937 */
/* local bus read write buffer mapping SRAM@0x64000000 */
#define CONFIG_SYS_BR3_PRELIM	(0x62000000 \
				| BR_PS_16 \
				| BR_V)
				/* 0x62001001 */

#define CONFIG_SYS_OR3_PRELIM	(OR_AM_32MB \
				| OR_GPCM_CSNT \
				| OR_GPCM_XACS \
				| OR_GPCM_SCY_15 \
				| OR_GPCM_TRLX_SET \
				| OR_GPCM_EHTR_SET \
				| OR_GPCM_EAD)
				/* 0xfe0009f7 */

/*
 * Serial Port
 */
#define CONFIG_CONS_INDEX	1
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)

#define CONFIG_SYS_BAUDRATE_TABLE	\
	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}

#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR+0x4500)
#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR+0x4600)

#if defined(CONFIG_PCI)
/*
 * General PCI
 * Addresses are mapped 1-1.
 */
#define CONFIG_SYS_PCI1_MEM_BASE	0x80000000
#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
#define CONFIG_SYS_PCI1_MEM_SIZE	0x10000000	/* 256M */
#define CONFIG_SYS_PCI1_MMIO_BASE	0x90000000
#define CONFIG_SYS_PCI1_MMIO_PHYS	CONFIG_SYS_PCI1_MMIO_BASE
#define CONFIG_SYS_PCI1_MMIO_SIZE	0x10000000	/* 256M */
#define CONFIG_SYS_PCI1_IO_BASE		0x00000000
#define CONFIG_SYS_PCI1_IO_PHYS		0xE2000000
#define CONFIG_SYS_PCI1_IO_SIZE		0x00100000	/* 1M */

#define CONFIG_PCI_PNP		/* do pci plug-and-play */
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957	/* Freescale */
#endif

/*
 * TSEC
 */
#define CONFIG_TSEC_ENET		/* TSEC ethernet support */

#define CONFIG_TSEC1
#ifdef CONFIG_TSEC1
#define CONFIG_HAS_ETH0
#define CONFIG_TSEC1_NAME	"TSEC1"
#define CONFIG_SYS_TSEC1_OFFSET	0x24000
#define TSEC1_PHY_ADDR		0x01
#define TSEC1_FLAGS		0
#define TSEC1_PHYIDX		0
#endif

/* Options are: TSEC[0-1] */
#define CONFIG_ETHPRIME			"TSEC1"

/*
 * Environment
 */
#define CONFIG_ENV_IS_IN_FLASH	1
#define CONFIG_ENV_ADDR		\
			(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
#define CONFIG_ENV_SECT_SIZE	0x20000	/* 128K(one sector) for env */
#define CONFIG_ENV_SIZE		0x4000
/* Address and size of Redundant Environment Sector */
#define CONFIG_ENV_OFFSET_REDUND	\
			(CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME

/*
 * Command line configuration.
 */
#define CONFIG_CMD_PCI

#define CONFIG_CMDLINE_EDITING 1
#define CONFIG_AUTO_COMPLETE	/* add autocompletion support   */

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP			/* undef to save memory */
#define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */

#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
#define CONFIG_SYS_MAXARGS	16		/* max number of cmd args */
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE /* Boot arg Buffer size */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 256 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
				/* Initial Memory map for Linux*/
#define CONFIG_SYS_BOOTMAPSZ	(256 << 20)

/* 0x64050000 */
#define CONFIG_SYS_HRCW_LOW (\
	0x20000000 /* reserved, must be set */ |\
	HRCWL_DDRCM |\
	HRCWL_CSB_TO_CLKIN_4X1 | \
	HRCWL_CORE_TO_CSB_2_5X1)

/* 0xa0600004 */
#define CONFIG_SYS_HRCW_HIGH (HRCWH_PCI_HOST | \
	HRCWH_PCI_ARBITER_ENABLE | \
	HRCWH_CORE_ENABLE | \
	HRCWH_FROM_0X00000100 | \
	HRCWH_BOOTSEQ_DISABLE |\
	HRCWH_SW_WATCHDOG_DISABLE |\
	HRCWH_ROM_LOC_LOCAL_16BIT | \
	HRCWH_TSEC1M_IN_MII | \
	HRCWH_BIG_ENDIAN | \
	HRCWH_LALE_EARLY)

/* System IO Config */
#define CONFIG_SYS_SICRH	(0x01000000 | \
				SICRH_ETSEC2_B | \
				SICRH_ETSEC2_C | \
				SICRH_ETSEC2_D | \
				SICRH_ETSEC2_E | \
				SICRH_ETSEC2_F | \
				SICRH_ETSEC2_G | \
				SICRH_TSOBI1 | \
				SICRH_TSOBI2)
				/* 0x010fff03 */
#define CONFIG_SYS_SICRL	(SICRL_LBC | \
				SICRL_SPI_A | \
				SICRL_SPI_B | \
				SICRL_SPI_C | \
				SICRL_SPI_D | \
				SICRL_ETSEC2_A)
				/* 0x33fc0003) */

#define CONFIG_SYS_HID0_INIT	0x000000000
#define CONFIG_SYS_HID0_FINAL	(HID0_ENABLE_MACHINE_CHECK | \
				 HID0_ENABLE_INSTRUCTION_CACHE)

#define CONFIG_SYS_HID2 HID2_HBE

#define CONFIG_HIGH_BATS	1	/* High BATs supported */

/* DDR @ 0x00000000 */
#define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE | BATL_PP_RW)
#define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE \
				| BATU_BL_256M \
				| BATU_VS \
				| BATU_VP)

#if defined(CONFIG_PCI)
/* PCI @ 0x80000000 */
#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW)
#define CONFIG_SYS_IBAT1U	(CONFIG_SYS_PCI1_MEM_BASE \
				| BATU_BL_256M \
				| BATU_VS \
				| BATU_VP)
#define CONFIG_SYS_IBAT2L	(CONFIG_SYS_PCI1_MMIO_BASE \
				| BATL_PP_RW \
				| BATL_CACHEINHIBIT \
				| BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT2U	(CONFIG_SYS_PCI1_MMIO_BASE \
				| BATU_BL_256M \
				| BATU_VS \
				| BATU_VP)
#else
#define CONFIG_SYS_IBAT1L	(0)
#define CONFIG_SYS_IBAT1U	(0)
#define CONFIG_SYS_IBAT2L	(0)
#define CONFIG_SYS_IBAT2U	(0)
#endif

/* PCI2 not supported on 8313 */
#define CONFIG_SYS_IBAT3L	(0)
#define CONFIG_SYS_IBAT3U	(0)
#define CONFIG_SYS_IBAT4L	(0)
#define CONFIG_SYS_IBAT4U	(0)

/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
#define CONFIG_SYS_IBAT5L	(CONFIG_SYS_IMMR \
				| BATL_PP_RW \
				| BATL_CACHEINHIBIT \
				| BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT5U	(CONFIG_SYS_IMMR \
				| BATU_BL_256M \
				| BATU_VS \
				| BATU_VP)

/* stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
#define CONFIG_SYS_IBAT6L	(0xF0000000 | BATL_PP_RW | BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT6U	(0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)

/*  FPGA, SRAM, NAND @ 0x60000000 */
#define CONFIG_SYS_IBAT7L	(0x60000000 | BATL_PP_RW | BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT7U	(0x60000000 | BATU_BL_256M | BATU_VS | BATU_VP)

#define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
#define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
#define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
#define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
#define CONFIG_SYS_DBAT2L	CONFIG_SYS_IBAT2L
#define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
#define CONFIG_SYS_DBAT3L	CONFIG_SYS_IBAT3L
#define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
#define CONFIG_SYS_DBAT4L	CONFIG_SYS_IBAT4L
#define CONFIG_SYS_DBAT4U	CONFIG_SYS_IBAT4U
#define CONFIG_SYS_DBAT5L	CONFIG_SYS_IBAT5L
#define CONFIG_SYS_DBAT5U	CONFIG_SYS_IBAT5U
#define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
#define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
#define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
#define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U

#define CONFIG_NETDEV		eth0

#define CONFIG_HOSTNAME		ve8313
#define CONFIG_UBOOTPATH	ve8313/u-boot.bin

#define CONFIG_BAUDRATE		115200

#define CONFIG_EXTRA_ENV_SETTINGS \
	"netdev=" __stringify(CONFIG_NETDEV) "\0"			\
	"ethprime=" __stringify(CONFIG_TSEC1_NAME) "\0"			\
	"u-boot=" __stringify(CONFIG_UBOOTPATH) "\0"			\
	"u-boot_addr_r=100000\0"					\
	"load=tftp ${u-boot_addr_r} ${u-boot}\0"			\
	"update=protect off " __stringify(CONFIG_SYS_FLASH_BASE)	\
		" +${filesize};"	\
	"erase " __stringify(CONFIG_SYS_FLASH_BASE) " +${filesize};"	\
	"cp.b ${u-boot_addr_r} " __stringify(CONFIG_SYS_FLASH_BASE)	\
	" ${filesize};"							\
	"protect on " __stringify(CONFIG_SYS_FLASH_BASE) " +${filesize}\0" \

#endif	/* __CONFIG_H */
Commit	Line	Data
4e43b2e8 HS	1	/*
	2	* Copyright (C) Freescale Semiconductor, Inc. 2006.
	3	*
	4	* (C) Copyright 2010
	5	* Heiko Schocher, DENX Software Engineering, hs@denx.de.
	6	*
3765b3e7	7	* SPDX-License-Identifier: GPL-2.0+
4e43b2e8 HS	8	*/
	9	/*
	10	* ve8313 board configuration file
	11	*/
	12
	13	#ifndef __CONFIG_H
	14	#define __CONFIG_H
	15
	16	/*
	17	* High Level Configuration Options
	18	*/
	19	#define CONFIG_E300 1
4e43b2e8 HS	20	#define CONFIG_MPC831x 1
	21	#define CONFIG_MPC8313 1
	22	#define CONFIG_VE8313 1
	23
2ae18241 WD	24	#ifndef CONFIG_SYS_TEXT_BASE
	25	#define CONFIG_SYS_TEXT_BASE 0xfe000000
	26	#endif
	27
842033e6	28	#define CONFIG_PCI_INDIRECT_BRIDGE 1
a2243b84	29	#define CONFIG_FSL_ELBC 1
4e43b2e8 HS	30
	31	#define CONFIG_BOARD_EARLY_INIT_F 1
	32
	33	/*
	34	* On-board devices
	35	*
	36	*/
	37	#define CONFIG_83XX_CLKIN 32000000 /* in Hz */
	38
	39	#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
	40
	41	#define CONFIG_SYS_IMMR 0xE0000000
	42
	43	#define CONFIG_SYS_MEMTEST_START 0x00001000
	44	#define CONFIG_SYS_MEMTEST_END 0x07000000
	45
	46	#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth */
	47	#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count */
	48
	49	/*
	50	* Device configurations
	51	*/
	52
	53	/*
	54	* DDR Setup
	55	*/
be29fa71	56	#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
4e43b2e8 HS	57	#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
	58	#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
	59
	60	/*
	61	* Manually set up DDR parameters, as this board does not
	62	* have the SPD connected to I2C.
	63	*/
be29fa71	64	#define CONFIG_SYS_DDR_SIZE 128 /* MB */
2e651b24	65	#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
4e43b2e8	66	\| CSCONFIG_AP \
2fef4020 JH	67	\| CSCONFIG_ODT_RD_NEVER \
2fef4020 JH	68	\| CSCONFIG_ODT_WR_ALL \
be29fa71 JH	69	\| CSCONFIG_ROW_BIT_13 \
be29fa71 JH	70	\| CSCONFIG_COL_BIT_10)
4e43b2e8 HS	71	/* 0x80840102 */
	72
	73	#define CONFIG_SYS_DDR_TIMING_3 0x00000000
be29fa71 JH	74	#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
	75	\| (0 << TIMING_CFG0_WRT_SHIFT) \
	76	\| (3 << TIMING_CFG0_RRT_SHIFT) \
	77	\| (2 << TIMING_CFG0_WWT_SHIFT) \
	78	\| (7 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
	79	\| (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
	80	\| (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
	81	\| (2 << TIMING_CFG0_MRS_CYC_SHIFT))
4e43b2e8	82	/* 0x0e720802 */
be29fa71 JH	83	#define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
	84	\| (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \
	85	\| (2 << TIMING_CFG1_ACTTORW_SHIFT) \
	86	\| (5 << TIMING_CFG1_CASLAT_SHIFT) \
	87	\| (6 << TIMING_CFG1_REFREC_SHIFT) \
	88	\| (2 << TIMING_CFG1_WRREC_SHIFT) \
	89	\| (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
	90	\| (2 << TIMING_CFG1_WRTORD_SHIFT))
4e43b2e8	91	/* 0x26256222 */
be29fa71 JH	92	#define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
	93	\| (5 << TIMING_CFG2_CPO_SHIFT) \
	94	\| (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
	95	\| (1 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
	96	\| (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
	97	\| (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
	98	\| (7 << TIMING_CFG2_FOUR_ACT_SHIFT))
4e43b2e8	99	/* 0x029028c7 */
be29fa71 JH	100	#define CONFIG_SYS_DDR_INTERVAL ((0x320 << SDRAM_INTERVAL_REFINT_SHIFT) \
be29fa71 JH	101	\| (0x2000 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
4e43b2e8	102	/* 0x03202000 */
be29fa71	103	#define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \
4e43b2e8	104	\| SDRAM_CFG_SDRAM_TYPE_DDR2 \
2fef4020	105	\| SDRAM_CFG_DBW_32)
4e43b2e8	106	/* 0x43080000 */
be29fa71 JH	107	#define CONFIG_SYS_SDRAM_CFG2 0x00401000
	108	#define CONFIG_SYS_DDR_MODE ((0x4440 << SDRAM_MODE_ESD_SHIFT) \
	109	\| (0x0232 << SDRAM_MODE_SD_SHIFT))
4e43b2e8	110	/* 0x44400232 */
be29fa71	111	#define CONFIG_SYS_DDR_MODE_2 0x8000C000
4e43b2e8 HS	112
	113	#define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
	114	/0x02000000/
be29fa71	115	#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
4e43b2e8 HS	116	\| DDRCDR_PZ_NOMZ \
4e43b2e8 HS	117	\| DDRCDR_NZ_NOMZ \
be29fa71	118	\| DDRCDR_M_ODR)
4e43b2e8 HS	119	/* 0x73000002 */
	120
	121	/*
	122	* FLASH on the Local Bus
	123	*/
	124	#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
	125	#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
	126	#define CONFIG_SYS_FLASH_BASE 0xFE000000
	127	#define CONFIG_SYS_FLASH_SIZE 32 /* size in MB */
	128	#define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */
	129	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* buffer up multiple bytes */
	130
be29fa71	131	#define CONFIG_SYS_NOR_BR_PRELIM (CONFIG_SYS_FLASH_BASE \
7d6a0982 JH	132	\| BR_PS_16 /* 16 bit */ \
	133	\| BR_MS_GPCM /* MSEL = GPCM */ \
	134	\| BR_V) /* valid */
4e43b2e8	135	#define CONFIG_SYS_NOR_OR_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
be29fa71 JH	136	\| OR_GPCM_CSNT \
	137	\| OR_GPCM_ACS_DIV4 \
	138	\| OR_GPCM_SCY_5 \
7d6a0982	139	\| OR_GPCM_TRLX_SET \
be29fa71 JH	140	\| OR_GPCM_EAD)
be29fa71 JH	141	/* 0xfe000c55 */
4e43b2e8 HS	142
4e43b2e8 HS	143	#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
7d6a0982	144	#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN \| LBLAWAR_32MB)
4e43b2e8 HS	145
	146	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
	147	#define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per dev */
	148
	149	#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
	150	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
	151
14d0a02a	152	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
4e43b2e8 HS	153
	154	#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
	155	#define CONFIG_SYS_RAMBOOT
	156	#endif
	157
	158	#define CONFIG_SYS_INIT_RAM_LOCK 1
	159	#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */
be29fa71	160	#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
4e43b2e8	161
be29fa71 JH	162	#define CONFIG_SYS_GBL_DATA_OFFSET \
be29fa71 JH	163	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
4e43b2e8 HS	164	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
	165
	166	/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
	167	#define CONFIG_SYS_MONITOR_LEN (384 * 1024)
	168	#define CONFIG_SYS_MALLOC_LEN (512 * 1024)
	169
	170	/*
	171	* Local Bus LCRR and LBCR regs
	172	*/
	173	#define CONFIG_SYS_LCRR_EADC LCRR_EADC_3
	174	#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
	175
	176	#define CONFIG_SYS_LBC_LBCR 0x00040000
	177
	178	#define CONFIG_SYS_LBC_MRTPR 0x20000000
	179
	180	/*
	181	* NAND settings
	182	*/
	183	#define CONFIG_SYS_NAND_BASE 0x61000000
	184	#define CONFIG_SYS_MAX_NAND_DEVICE 1
4e43b2e8 HS	185	#define CONFIG_CMD_NAND 1
	186	#define CONFIG_NAND_FSL_ELBC 1
	187	#define CONFIG_SYS_NAND_BLOCK_SIZE 16384
	188
be29fa71 JH	189	#define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE \
	190	\| BR_PS_8 \
	191	\| BR_DECC_CHK_GEN \
	192	\| BR_MS_FCM \
	193	\| BR_V) /* valid */
	194	/* 0x61000c21 */
7d6a0982	195	#define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB \
be29fa71 JH	196	\| OR_FCM_BCTLD \
	197	\| OR_FCM_CHT \
	198	\| OR_FCM_SCY_2 \
	199	\| OR_FCM_RST \
	200	\| OR_FCM_TRLX)
	201	/* 0xffff90ac */
4e43b2e8 HS	202
	203	#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM
	204	#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM
	205	#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM
	206	#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM
	207
	208	#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
7d6a0982	209	#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN \| LBLAWAR_32KB)
4e43b2e8 HS	210
	211	#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
	212	#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
	213
	214	/* CS2 NvRAM */
be29fa71 JH	215	#define CONFIG_SYS_BR2_PRELIM (0x60000000 \
be29fa71 JH	216	\| BR_PS_8 \
4e43b2e8 HS	217	\| BR_V)
4e43b2e8 HS	218	/* 0x60000801 */
7d6a0982	219	#define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB \
be29fa71 JH	220	\| OR_GPCM_CSNT \
be29fa71 JH	221	\| OR_GPCM_XACS \
4e43b2e8	222	\| OR_GPCM_SCY_3 \
7d6a0982 JH	223	\| OR_GPCM_TRLX_SET \
7d6a0982 JH	224	\| OR_GPCM_EHTR_SET \
4e43b2e8 HS	225	\| OR_GPCM_EAD)
	226	/* 0xfffe0937 */
	227	/* local bus read write buffer mapping SRAM@0x64000000 */
be29fa71 JH	228	#define CONFIG_SYS_BR3_PRELIM (0x62000000 \
be29fa71 JH	229	\| BR_PS_16 \
4e43b2e8 HS	230	\| BR_V)
	231	/* 0x62001001 */
	232
7d6a0982	233	#define CONFIG_SYS_OR3_PRELIM (OR_AM_32MB \
be29fa71 JH	234	\| OR_GPCM_CSNT \
be29fa71 JH	235	\| OR_GPCM_XACS \
4e43b2e8	236	\| OR_GPCM_SCY_15 \
7d6a0982 JH	237	\| OR_GPCM_TRLX_SET \
7d6a0982 JH	238	\| OR_GPCM_EHTR_SET \
4e43b2e8 HS	239	\| OR_GPCM_EAD)
	240	/* 0xfe0009f7 */
	241
4e43b2e8 HS	242	/*
	243	* Serial Port
	244	*/
	245	#define CONFIG_CONS_INDEX 1
4e43b2e8 HS	246	#define CONFIG_SYS_NS16550_SERIAL
	247	#define CONFIG_SYS_NS16550_REG_SIZE 1
	248	#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
	249
	250	#define CONFIG_SYS_BAUDRATE_TABLE \
	251	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
	252
	253	#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
	254	#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
	255
4e43b2e8 HS	256	#if defined(CONFIG_PCI)
	257	/*
	258	* General PCI
	259	* Addresses are mapped 1-1.
	260	*/
	261	#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
	262	#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
	263	#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
	264	#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
	265	#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
	266	#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
be29fa71 JH	267	#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
	268	#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
	269	#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
4e43b2e8 HS	270
	271	#define CONFIG_PCI_PNP /* do pci plug-and-play */
	272	#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
	273	#endif
	274
	275	/*
	276	* TSEC
	277	*/
	278	#define CONFIG_TSEC_ENET /* TSEC ethernet support */
	279
4e43b2e8 HS	280	#define CONFIG_TSEC1
	281	#ifdef CONFIG_TSEC1
	282	#define CONFIG_HAS_ETH0
	283	#define CONFIG_TSEC1_NAME "TSEC1"
	284	#define CONFIG_SYS_TSEC1_OFFSET 0x24000
	285	#define TSEC1_PHY_ADDR 0x01
	286	#define TSEC1_FLAGS 0
	287	#define TSEC1_PHYIDX 0
	288	#endif
	289
	290	/* Options are: TSEC[0-1] */
	291	#define CONFIG_ETHPRIME "TSEC1"
	292
	293	/*
	294	* Environment
	295	*/
	296	#define CONFIG_ENV_IS_IN_FLASH 1
be29fa71 JH	297	#define CONFIG_ENV_ADDR \
be29fa71 JH	298	(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
4e43b2e8 HS	299	#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
	300	#define CONFIG_ENV_SIZE 0x4000
	301	/* Address and size of Redundant Environment Sector */
be29fa71 JH	302	#define CONFIG_ENV_OFFSET_REDUND \
be29fa71 JH	303	(CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE)
4e43b2e8 HS	304	#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
	305
	306	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
	307	#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
	308
	309	/*
	310	* BOOTP options
	311	*/
	312	#define CONFIG_BOOTP_BOOTFILESIZE
	313	#define CONFIG_BOOTP_BOOTPATH
	314	#define CONFIG_BOOTP_GATEWAY
	315	#define CONFIG_BOOTP_HOSTNAME
	316
	317	/*
	318	* Command line configuration.
	319	*/
4e43b2e8 HS	320	#define CONFIG_CMD_PCI
	321
	322	#define CONFIG_CMDLINE_EDITING 1
	323	#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
	324
	325	/*
	326	* Miscellaneous configurable options
	327	*/
	328	#define CONFIG_SYS_LONGHELP /* undef to save memory */
	329	#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
4e43b2e8 HS	330	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
	331
	332	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
	333	#define CONFIG_SYS_MAXARGS 16 /* max number of cmd args */
	334	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot arg Buffer size */
4e43b2e8 HS	335
	336	/*
	337	* For booting Linux, the board info and command line data
9f530d59	338	* have to be in the first 256 MB of memory, since this is
4e43b2e8 HS	339	* the maximum mapped by the Linux kernel during initialization.
4e43b2e8 HS	340	*/
be29fa71 JH	341	/* Initial Memory map for Linux*/
be29fa71 JH	342	#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
4e43b2e8 HS	343
	344	/* 0x64050000 */
	345	#define CONFIG_SYS_HRCW_LOW (\
	346	0x20000000 /* reserved, must be set */ \|\
	347	HRCWL_DDRCM \|\
	348	HRCWL_CSB_TO_CLKIN_4X1 \| \
	349	HRCWL_CORE_TO_CSB_2_5X1)
	350
	351	/* 0xa0600004 */
	352	#define CONFIG_SYS_HRCW_HIGH (HRCWH_PCI_HOST \| \
	353	HRCWH_PCI_ARBITER_ENABLE \| \
	354	HRCWH_CORE_ENABLE \| \
	355	HRCWH_FROM_0X00000100 \| \
	356	HRCWH_BOOTSEQ_DISABLE \|\
	357	HRCWH_SW_WATCHDOG_DISABLE \|\
	358	HRCWH_ROM_LOC_LOCAL_16BIT \| \
	359	HRCWH_TSEC1M_IN_MII \| \
	360	HRCWH_BIG_ENDIAN \| \
	361	HRCWH_LALE_EARLY)
	362
	363	/* System IO Config */
	364	#define CONFIG_SYS_SICRH (0x01000000 \| \
	365	SICRH_ETSEC2_B \| \
	366	SICRH_ETSEC2_C \| \
	367	SICRH_ETSEC2_D \| \
	368	SICRH_ETSEC2_E \| \
	369	SICRH_ETSEC2_F \| \
	370	SICRH_ETSEC2_G \| \
	371	SICRH_TSOBI1 \| \
	372	SICRH_TSOBI2)
	373	/* 0x010fff03 */
	374	#define CONFIG_SYS_SICRL (SICRL_LBC \| \
	375	SICRL_SPI_A \| \
	376	SICRL_SPI_B \| \
	377	SICRL_SPI_C \| \
	378	SICRL_SPI_D \| \
	379	SICRL_ETSEC2_A)
	380	/* 0x33fc0003) */
	381
	382	#define CONFIG_SYS_HID0_INIT 0x000000000
	383	#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \| \
	384	HID0_ENABLE_INSTRUCTION_CACHE)
	385
	386	#define CONFIG_SYS_HID2 HID2_HBE
	387
	388	#define CONFIG_HIGH_BATS 1 /* High BATs supported */
	389
	390	/* DDR @ 0x00000000 */
72cd4087	391	#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \| BATL_PP_RW)
be29fa71 JH	392	#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
	393	\| BATU_BL_256M \
	394	\| BATU_VS \
	395	\| BATU_VP)
4e43b2e8 HS	396
	397	#if defined(CONFIG_PCI)
	398	/* PCI @ 0x80000000 */
72cd4087	399	#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \| BATL_PP_RW)
be29fa71 JH	400	#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \
	401	\| BATU_BL_256M \
	402	\| BATU_VS \
	403	\| BATU_VP)
	404	#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \
72cd4087	405	\| BATL_PP_RW \
be29fa71 JH	406	\| BATL_CACHEINHIBIT \
	407	\| BATL_GUARDEDSTORAGE)
	408	#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \
	409	\| BATU_BL_256M \
	410	\| BATU_VS \
	411	\| BATU_VP)
4e43b2e8 HS	412	#else
	413	#define CONFIG_SYS_IBAT1L (0)
	414	#define CONFIG_SYS_IBAT1U (0)
	415	#define CONFIG_SYS_IBAT2L (0)
	416	#define CONFIG_SYS_IBAT2U (0)
	417	#endif
	418
	419	/* PCI2 not supported on 8313 */
	420	#define CONFIG_SYS_IBAT3L (0)
	421	#define CONFIG_SYS_IBAT3U (0)
	422	#define CONFIG_SYS_IBAT4L (0)
	423	#define CONFIG_SYS_IBAT4U (0)
	424
	425	/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
be29fa71	426	#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \
72cd4087	427	\| BATL_PP_RW \
be29fa71 JH	428	\| BATL_CACHEINHIBIT \
	429	\| BATL_GUARDEDSTORAGE)
	430	#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \
	431	\| BATU_BL_256M \
	432	\| BATU_VS \
	433	\| BATU_VP)
4e43b2e8 HS	434
4e43b2e8 HS	435	/* stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
72cd4087	436	#define CONFIG_SYS_IBAT6L (0xF0000000 \| BATL_PP_RW \| BATL_GUARDEDSTORAGE)
4e43b2e8 HS	437	#define CONFIG_SYS_IBAT6U (0xF0000000 \| BATU_BL_256M \| BATU_VS \| BATU_VP)
	438
	439	/* FPGA, SRAM, NAND @ 0x60000000 */
72cd4087	440	#define CONFIG_SYS_IBAT7L (0x60000000 \| BATL_PP_RW \| BATL_GUARDEDSTORAGE)
4e43b2e8 HS	441	#define CONFIG_SYS_IBAT7U (0x60000000 \| BATU_BL_256M \| BATU_VS \| BATU_VP)
	442
	443	#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
	444	#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
	445	#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
	446	#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
	447	#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
	448	#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
	449	#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
	450	#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
	451	#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
	452	#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
	453	#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
	454	#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
	455	#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
	456	#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
	457	#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
	458	#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
	459
4e43b2e8 HS	460	#define CONFIG_NETDEV eth0
	461
	462	#define CONFIG_HOSTNAME ve8313
	463	#define CONFIG_UBOOTPATH ve8313/u-boot.bin
	464
4e43b2e8 HS	465	#define CONFIG_BAUDRATE 115200
4e43b2e8 HS	466
4e43b2e8	467	#define CONFIG_EXTRA_ENV_SETTINGS \
5368c55d MV	468	"netdev=" __stringify(CONFIG_NETDEV) "\0" \
	469	"ethprime=" __stringify(CONFIG_TSEC1_NAME) "\0" \
	470	"u-boot=" __stringify(CONFIG_UBOOTPATH) "\0" \
4e43b2e8 HS	471	"u-boot_addr_r=100000\0" \
4e43b2e8 HS	472	"load=tftp ${u-boot_addr_r} ${u-boot}\0" \
5368c55d MV	473	"update=protect off " __stringify(CONFIG_SYS_FLASH_BASE) \
	474	" +${filesize};" \
	475	"erase " __stringify(CONFIG_SYS_FLASH_BASE) " +${filesize};" \
	476	"cp.b ${u-boot_addr_r} " __stringify(CONFIG_SYS_FLASH_BASE) \
be29fa71	477	" ${filesize};" \
5368c55d	478	"protect on " __stringify(CONFIG_SYS_FLASH_BASE) " +${filesize}\0" \
4e43b2e8 HS	479
4e43b2e8 HS	480	#endif /* __CONFIG_H */