[people/ms/u-boot.git] / include / configs / versatile.h

/*
 * (C) Copyright 2003
 * Texas Instruments.
 * Kshitij Gupta <kshitij@ti.com>
 * Configuation settings for the TI OMAP Innovator board.
 *
 * (C) Copyright 2004
 * ARM Ltd.
 * Philippe Robin, <philippe.robin@arm.com>
 * Configuration for Versatile PB.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */
#define CONFIG_VERSATILE	1	/* This is Versatile Platform Board	*/
#define CONFIG_ARCH_VERSATILE	1	/* Specifically, a Versatile	*/

#define CONFIG_SYS_MEMTEST_START	0x100000
#define CONFIG_SYS_MEMTEST_END		0x10000000

#define CONFIG_SYS_TIMERBASE		0x101E2000	/* Timer 0 and 1 base */
#define CONFIG_SYS_TIMER_RATE		(1000000 / 256)
#define CONFIG_SYS_TIMER_COUNTER	(CONFIG_SYS_TIMERBASE + 0x4)
#define CONFIG_SYS_TIMER_COUNTS_DOWN

/*
 * control registers
 */
#define VERSATILE_SCTL_BASE		0x101E0000	/* System controller */

/*
 * System controller bit assignment
 */
#define VERSATILE_REFCLK	0
#define VERSATILE_TIMCLK	1

#define VERSATILE_TIMER1_EnSel	15
#define VERSATILE_TIMER2_EnSel	17
#define VERSATILE_TIMER3_EnSel	19
#define VERSATILE_TIMER4_EnSel	21

#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS	1
#define CONFIG_MISC_INIT_R		1
/*
 * Size of malloc() pool
 */
#define CONFIG_ENV_SIZE			8192
#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128 * 1024)

/*
 * Hardware drivers
 */

#define CONFIG_SMC91111
#define CONFIG_SMC_USE_32_BIT
#define CONFIG_SMC91111_BASE	0x10010000
#undef CONFIG_SMC91111_EXT_PHY

/*
 * NS16550 Configuration
 */
#define CONFIG_PL011_SERIAL
#define CONFIG_PL011_CLOCK	24000000
#define CONFIG_PL01x_PORTS				\
			{(void *)CONFIG_SYS_SERIAL0,	\
			 (void *)CONFIG_SYS_SERIAL1 }
#define CONFIG_CONS_INDEX	0

#define CONFIG_BAUDRATE			38400
#define CONFIG_SYS_SERIAL0		0x101F1000
#define CONFIG_SYS_SERIAL1		0x101F2000

/*
 * Command line configuration.
 */
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_PING

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_SUBNETMASK

#define CONFIG_BOOTDELAY	2
#define CONFIG_BOOTARGS		"root=/dev/nfs mem=128M ip=dhcp "\
				"netdev=25,0,0xf1010000,0xf1010010,eth0 "\
				"console=ttyAMA0,38400n1"

/*
 * Static configuration when assigning fixed address
 */
#define CONFIG_BOOTFILE		"/tftpboot/uImage" /* file to load */

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP	/* undef to save memory */
#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
/* Monitor Command Prompt	 */
#ifdef CONFIG_ARCH_VERSATILE_AB
# define CONFIG_SYS_PROMPT	"VersatileAB # "
#else
# define CONFIG_SYS_PROMPT	"VersatilePB # "
#endif
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE	\
			(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */

#define CONFIG_SYS_LOAD_ADDR	0x7fc0	/* default load address */

/*-----------------------------------------------------------------------
 * Physical Memory Map
 */
#define CONFIG_NR_DRAM_BANKS	1	/* we have 1 bank of DRAM */
#define PHYS_SDRAM_1		0x00000000	/* SDRAM Bank #1 */
#define PHYS_SDRAM_1_SIZE	0x08000000	/* 128 MB */
#define PHYS_FLASH_SIZE		0x04000000	/* 64MB */

#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_ADDR	0x00800000
#define CONFIG_SYS_INIT_RAM_SIZE	0x000FFFFF
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
						GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_INIT_RAM_ADDR + \
						CONFIG_SYS_GBL_DATA_OFFSET)

#define CONFIG_BOARD_EARLY_INIT_F

/*-----------------------------------------------------------------------
 * FLASH and environment organization
 */
#ifdef CONFIG_ARCH_VERSATILE_QEMU
#define CONFIG_SYS_TEXT_BASE		0x10000
#define CONFIG_SYS_NO_FLASH
#define CONFIG_ENV_IS_NOWHERE
#define CONFIG_SYS_MONITOR_LEN		0x80000
#else
#define CONFIG_SYS_TEXT_BASE		0x01000000
/*
 * Use the CFI flash driver for ease of use
 */
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_ENV_IS_IN_FLASH	1
/*
 *	System control register
 */
#define VERSATILE_SYS_BASE		0x10000000
#define VERSATILE_SYS_FLASH_OFFSET	0x4C
#define VERSATILE_FLASHCTRL		\
		(VERSATILE_SYS_BASE + VERSATILE_SYS_FLASH_OFFSET)
/* Enable writing to flash */
#define VERSATILE_FLASHPROG_FLVPPEN	(1 << 0)

/* timeout values are in ticks */
#define CONFIG_SYS_FLASH_ERASE_TOUT	(2 * CONFIG_SYS_HZ) /* Erase Timeout */
#define CONFIG_SYS_FLASH_WRITE_TOUT	(2 * CONFIG_SYS_HZ) /* Write Timeout */

/*
 * Note that CONFIG_SYS_MAX_FLASH_SECT allows for a parameter block
 * i.e.
 *	the bottom "sector" (bottom boot), or top "sector"
 *	(top boot), is a seperate erase region divided into
 *	4 (equal) smaller sectors. This, notionally, allows
 *	quicker erase/rewrire of the most frequently changed
 *	area......
 *	CONFIG_SYS_MAX_FLASH_SECT is padded up to a multiple of 4
 */

#ifdef CONFIG_ARCH_VERSATILE_AB
#define FLASH_SECTOR_SIZE		0x00020000	/* 128 KB sectors */
#define CONFIG_ENV_SECT_SIZE		(2 * FLASH_SECTOR_SIZE)
#define CONFIG_SYS_MAX_FLASH_SECT	(520)
#endif

#ifdef CONFIG_ARCH_VERSATILE_PB		/* Versatile PB is default	*/
#define FLASH_SECTOR_SIZE		0x00040000	/* 256 KB sectors */
#define CONFIG_ENV_SECT_SIZE		FLASH_SECTOR_SIZE
#define CONFIG_SYS_MAX_FLASH_SECT	(260)
#endif

#define CONFIG_SYS_FLASH_BASE		0x34000000
#define CONFIG_SYS_MAX_FLASH_BANKS	1

#define CONFIG_SYS_MONITOR_LEN		(4 * CONFIG_ENV_SECT_SIZE)

/* The ARM Boot Monitor is shipped in the lowest sector of flash */

#define FLASH_TOP			(CONFIG_SYS_FLASH_BASE + PHYS_FLASH_SIZE)
#define CONFIG_ENV_ADDR			(FLASH_TOP - CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_OFFSET		(CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
#define CONFIG_SYS_MONITOR_BASE		(CONFIG_ENV_ADDR - CONFIG_SYS_MONITOR_LEN)

#define CONFIG_SYS_FLASH_PROTECTION	/* The devices have real protection */
#define CONFIG_SYS_FLASH_EMPTY_INFO	/* flinfo indicates empty blocks */

#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* use buffered writes */
#endif

#endif	/* __CONFIG_H */
Commit	Line	Data
3d3befa7 WD	1	/*
	2	* (C) Copyright 2003
	3	* Texas Instruments.
	4	* Kshitij Gupta <kshitij@ti.com>
	5	* Configuation settings for the TI OMAP Innovator board.
	6	*
	7	* (C) Copyright 2004
	8	* ARM Ltd.
	9	* Philippe Robin, <philippe.robin@arm.com>
	10	* Configuration for Versatile PB.
	11	*
3765b3e7	12	* SPDX-License-Identifier: GPL-2.0+
3d3befa7 WD	13	*/
	14
	15	#ifndef __CONFIG_H
	16	#define __CONFIG_H
	17
	18	/*
	19	* High Level Configuration Options
	20	* (easy to change)
	21	*/
5d7b131d	22	#define CONFIG_VERSATILE 1 /* This is Versatile Platform Board */
2600b857	23	#define CONFIG_ARCH_VERSATILE 1 /* Specifically, a Versatile */
3d3befa7	24
2600b857 JCPV	25	#define CONFIG_SYS_MEMTEST_START 0x100000
2600b857 JCPV	26	#define CONFIG_SYS_MEMTEST_END 0x10000000
3d3befa7	27
5b6da283 RH	28	#define CONFIG_SYS_TIMERBASE 0x101E2000 /* Timer 0 and 1 base */
	29	#define CONFIG_SYS_TIMER_RATE (1000000 / 256)
	30	#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4)
	31	#define CONFIG_SYS_TIMER_COUNTS_DOWN
3d3befa7 WD	32
	33	/*
	34	* control registers
	35	*/
2600b857	36	#define VERSATILE_SCTL_BASE 0x101E0000 /* System controller */
3d3befa7 WD	37
	38	/*
	39	* System controller bit assignment
	40	*/
	41	#define VERSATILE_REFCLK 0
	42	#define VERSATILE_TIMCLK 1
	43
	44	#define VERSATILE_TIMER1_EnSel 15
	45	#define VERSATILE_TIMER2_EnSel 17
	46	#define VERSATILE_TIMER3_EnSel 19
	47	#define VERSATILE_TIMER4_EnSel 21
	48
2600b857	49	#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
3d3befa7	50	#define CONFIG_SETUP_MEMORY_TAGS 1
2600b857	51	#define CONFIG_MISC_INIT_R 1
3d3befa7 WD	52	/*
	53	* Size of malloc() pool
	54	*/
d388298a	55	#define CONFIG_ENV_SIZE 8192
2600b857	56	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024)
3d3befa7 WD	57
	58	/*
	59	* Hardware drivers
	60	*/
	61
7194ab80	62	#define CONFIG_SMC91111
3d3befa7	63	#define CONFIG_SMC_USE_32_BIT
53677ef1	64	#define CONFIG_SMC91111_BASE 0x10010000
3d3befa7 WD	65	#undef CONFIG_SMC91111_EXT_PHY
	66
	67	/*
	68	* NS16550 Configuration
	69	*/
48d0192f	70	#define CONFIG_PL011_SERIAL
6705d81e	71	#define CONFIG_PL011_CLOCK 24000000
2600b857 JCPV	72	#define CONFIG_PL01x_PORTS \
	73	{(void *)CONFIG_SYS_SERIAL0, \
	74	(void *)CONFIG_SYS_SERIAL1 }
3d3befa7	75	#define CONFIG_CONS_INDEX 0
6705d81e	76
2600b857	77	#define CONFIG_BAUDRATE 38400
6d0f6bcf JCPV	78	#define CONFIG_SYS_SERIAL0 0x101F1000
6d0f6bcf JCPV	79	#define CONFIG_SYS_SERIAL1 0x101F2000
3d3befa7	80
dca3b3d6 JL	81	/*
	82	* Command line configuration.
	83	*/
dca3b3d6	84	#define CONFIG_CMD_DHCP
dca3b3d6	85	#define CONFIG_CMD_PING
3d3befa7	86
d3b8c1a7 JL	87	/*
	88	* BOOTP options
	89	*/
2600b857	90	#define CONFIG_BOOTP_BOOTPATH
d3b8c1a7 JL	91	#define CONFIG_BOOTP_GATEWAY
d3b8c1a7 JL	92	#define CONFIG_BOOTP_HOSTNAME
2600b857	93	#define CONFIG_BOOTP_SUBNETMASK
3d3befa7 WD	94
3d3befa7 WD	95	#define CONFIG_BOOTDELAY 2
2600b857	96	#define CONFIG_BOOTARGS "root=/dev/nfs mem=128M ip=dhcp "\
7d7c497d LW	97	"netdev=25,0,0xf1010000,0xf1010010,eth0 "\
7d7c497d LW	98	"console=ttyAMA0,38400n1"
3d3befa7 WD	99
	100	/*
	101	* Static configuration when assigning fixed address
	102	*/
2600b857	103	#define CONFIG_BOOTFILE "/tftpboot/uImage" /* file to load */
3d3befa7 WD	104
	105	/*
	106	* Miscellaneous configurable options
	107	*/
2600b857	108	#define CONFIG_SYS_LONGHELP /* undef to save memory */
2600b857	109	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
d6e8ed83 JCPV	110	/* Monitor Command Prompt */
	111	#ifdef CONFIG_ARCH_VERSATILE_AB
	112	# define CONFIG_SYS_PROMPT "VersatileAB # "
	113	#else
	114	# define CONFIG_SYS_PROMPT "VersatilePB # "
	115	#endif
3d3befa7	116	/* Print Buffer Size */
2600b857 JCPV	117	#define CONFIG_SYS_PBSIZE \
	118	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
	119	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	120	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
3d3befa7	121
6d0f6bcf	122	#define CONFIG_SYS_LOAD_ADDR 0x7fc0 /* default load address */
3d3befa7	123
3d3befa7 WD	124	/*-----------------------------------------------------------------------
	125	* Physical Memory Map
	126	*/
2600b857 JCPV	127	#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
	128	#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */
	129	#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */
98692271	130	#define PHYS_FLASH_SIZE 0x04000000 /* 64MB */
3d3befa7	131
d388298a SB	132	#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
	133	#define CONFIG_SYS_INIT_RAM_ADDR 0x00800000
	134	#define CONFIG_SYS_INIT_RAM_SIZE 0x000FFFFF
	135	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
	136	GENERATED_GBL_DATA_SIZE)
	137	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
	138	CONFIG_SYS_GBL_DATA_OFFSET)
	139
	140	#define CONFIG_BOARD_EARLY_INIT_F
	141
3d3befa7 WD	142	/*-----------------------------------------------------------------------
	143	* FLASH and environment organization
	144	*/
d388298a SB	145	#ifdef CONFIG_ARCH_VERSATILE_QEMU
	146	#define CONFIG_SYS_TEXT_BASE 0x10000
	147	#define CONFIG_SYS_NO_FLASH
	148	#define CONFIG_ENV_IS_NOWHERE
	149	#define CONFIG_SYS_MONITOR_LEN 0x80000
	150	#else
	151	#define CONFIG_SYS_TEXT_BASE 0x01000000
98692271 JCPV	152	/*
	153	* Use the CFI flash driver for ease of use
	154	*/
	155	#define CONFIG_SYS_FLASH_CFI
	156	#define CONFIG_FLASH_CFI_DRIVER
	157	#define CONFIG_ENV_IS_IN_FLASH 1
	158	/*
	159	* System control register
	160	*/
2600b857 JCPV	161	#define VERSATILE_SYS_BASE 0x10000000
	162	#define VERSATILE_SYS_FLASH_OFFSET 0x4C
	163	#define VERSATILE_FLASHCTRL \
	164	(VERSATILE_SYS_BASE + VERSATILE_SYS_FLASH_OFFSET)
	165	/* Enable writing to flash */
	166	#define VERSATILE_FLASHPROG_FLVPPEN (1 << 0)
d407bf52	167
3d3befa7	168	/* timeout values are in ticks */
98692271 JCPV	169	#define CONFIG_SYS_FLASH_ERASE_TOUT (2 * CONFIG_SYS_HZ) /* Erase Timeout */
	170	#define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) /* Write Timeout */
	171
	172	/*
	173	* Note that CONFIG_SYS_MAX_FLASH_SECT allows for a parameter block
	174	* i.e.
	175	* the bottom "sector" (bottom boot), or top "sector"
	176	* (top boot), is a seperate erase region divided into
	177	* 4 (equal) smaller sectors. This, notionally, allows
	178	* quicker erase/rewrire of the most frequently changed
	179	* area......
	180	* CONFIG_SYS_MAX_FLASH_SECT is padded up to a multiple of 4
	181	*/
	182
	183	#ifdef CONFIG_ARCH_VERSATILE_AB
	184	#define FLASH_SECTOR_SIZE 0x00020000 /* 128 KB sectors */
	185	#define CONFIG_ENV_SECT_SIZE (2 * FLASH_SECTOR_SIZE)
	186	#define CONFIG_SYS_MAX_FLASH_SECT (520)
	187	#endif
	188
	189	#ifdef CONFIG_ARCH_VERSATILE_PB /* Versatile PB is default */
	190	#define FLASH_SECTOR_SIZE 0x00040000 /* 256 KB sectors */
	191	#define CONFIG_ENV_SECT_SIZE FLASH_SECTOR_SIZE
	192	#define CONFIG_SYS_MAX_FLASH_SECT (260)
	193	#endif
	194
	195	#define CONFIG_SYS_FLASH_BASE 0x34000000
	196	#define CONFIG_SYS_MAX_FLASH_BANKS 1
	197
	198	#define CONFIG_SYS_MONITOR_LEN (4 * CONFIG_ENV_SECT_SIZE)
	199
	200	/* The ARM Boot Monitor is shipped in the lowest sector of flash */
3d3befa7	201
98692271	202	#define FLASH_TOP (CONFIG_SYS_FLASH_BASE + PHYS_FLASH_SIZE)
98692271 JCPV	203	#define CONFIG_ENV_ADDR (FLASH_TOP - CONFIG_ENV_SECT_SIZE)
	204	#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
	205	#define CONFIG_SYS_MONITOR_BASE (CONFIG_ENV_ADDR - CONFIG_SYS_MONITOR_LEN)
3d3befa7	206
98692271 JCPV	207	#define CONFIG_SYS_FLASH_PROTECTION /* The devices have real protection */
98692271 JCPV	208	#define CONFIG_SYS_FLASH_EMPTY_INFO /* flinfo indicates empty blocks */
d407bf52	209
de1f9ac8	210	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* use buffered writes */
d388298a SB	211	#endif
d388298a SB	212
98692271	213	#endif /* __CONFIG_H */