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12916829 DF |
1 | /* |
2 | * Configuration for Versatile Express. Parts were derived from other ARM | |
3 | * configurations. | |
4 | * | |
5 | * SPDX-License-Identifier: GPL-2.0+ | |
6 | */ | |
7 | ||
8 | #ifndef __VEXPRESS_AEMV8A_H | |
9 | #define __VEXPRESS_AEMV8A_H | |
10 | ||
f91afc4d | 11 | #ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP |
261d2760 | 12 | #ifndef CONFIG_SEMIHOSTING |
f91afc4d | 13 | #error CONFIG_TARGET_VEXPRESS64_BASE_FVP requires CONFIG_SEMIHOSTING |
261d2760 | 14 | #endif |
261d2760 DR |
15 | #define CONFIG_ARMV8_SWITCH_TO_EL1 |
16 | #endif | |
17 | ||
12916829 DF |
18 | #define CONFIG_REMAKE_ELF |
19 | ||
12916829 | 20 | /* Link Definitions */ |
fc04b923 RH |
21 | #if defined(CONFIG_TARGET_VEXPRESS64_BASE_FVP) || \ |
22 | defined(CONFIG_TARGET_VEXPRESS64_BASE_FVP_DRAM) | |
261d2760 | 23 | /* ATF loads u-boot here for BASE_FVP model */ |
261d2760 | 24 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x03f00000) |
ffc10373 | 25 | #elif CONFIG_TARGET_VEXPRESS64_JUNO |
ffc10373 | 26 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) |
261d2760 | 27 | #endif |
12916829 | 28 | |
0d3012af RH |
29 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ |
30 | ||
12916829 DF |
31 | /* CS register bases for the original memory map. */ |
32 | #define V2M_PA_CS0 0x00000000 | |
33 | #define V2M_PA_CS1 0x14000000 | |
34 | #define V2M_PA_CS2 0x18000000 | |
35 | #define V2M_PA_CS3 0x1c000000 | |
36 | #define V2M_PA_CS4 0x0c000000 | |
37 | #define V2M_PA_CS5 0x10000000 | |
38 | ||
39 | #define V2M_PERIPH_OFFSET(x) (x << 16) | |
40 | #define V2M_SYSREGS (V2M_PA_CS3 + V2M_PERIPH_OFFSET(1)) | |
41 | #define V2M_SYSCTL (V2M_PA_CS3 + V2M_PERIPH_OFFSET(2)) | |
42 | #define V2M_SERIAL_BUS_PCI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(3)) | |
43 | ||
44 | #define V2M_BASE 0x80000000 | |
45 | ||
12916829 DF |
46 | /* Common peripherals relative to CS7. */ |
47 | #define V2M_AACI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(4)) | |
48 | #define V2M_MMCI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(5)) | |
49 | #define V2M_KMI0 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(6)) | |
50 | #define V2M_KMI1 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(7)) | |
51 | ||
ffc10373 LW |
52 | #ifdef CONFIG_TARGET_VEXPRESS64_JUNO |
53 | #define V2M_UART0 0x7ff80000 | |
54 | #define V2M_UART1 0x7ff70000 | |
55 | #else /* Not Juno */ | |
12916829 DF |
56 | #define V2M_UART0 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(9)) |
57 | #define V2M_UART1 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(10)) | |
58 | #define V2M_UART2 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(11)) | |
59 | #define V2M_UART3 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(12)) | |
ffc10373 | 60 | #endif |
12916829 DF |
61 | |
62 | #define V2M_WDT (V2M_PA_CS3 + V2M_PERIPH_OFFSET(15)) | |
63 | ||
64 | #define V2M_TIMER01 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(17)) | |
65 | #define V2M_TIMER23 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(18)) | |
66 | ||
67 | #define V2M_SERIAL_BUS_DVI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(22)) | |
68 | #define V2M_RTC (V2M_PA_CS3 + V2M_PERIPH_OFFSET(23)) | |
69 | ||
70 | #define V2M_CF (V2M_PA_CS3 + V2M_PERIPH_OFFSET(26)) | |
71 | ||
72 | #define V2M_CLCD (V2M_PA_CS3 + V2M_PERIPH_OFFSET(31)) | |
73 | ||
74 | /* System register offsets. */ | |
75 | #define V2M_SYS_CFGDATA (V2M_SYSREGS + 0x0a0) | |
76 | #define V2M_SYS_CFGCTRL (V2M_SYSREGS + 0x0a4) | |
77 | #define V2M_SYS_CFGSTAT (V2M_SYSREGS + 0x0a8) | |
78 | ||
79 | /* Generic Timer Definitions */ | |
80 | #define COUNTER_FREQUENCY (0x1800000) /* 24MHz */ | |
81 | ||
82 | /* Generic Interrupt Controller Definitions */ | |
c71645ad DF |
83 | #ifdef CONFIG_GICV3 |
84 | #define GICD_BASE (0x2f000000) | |
85 | #define GICR_BASE (0x2f100000) | |
86 | #else | |
261d2760 | 87 | |
fc04b923 RH |
88 | #if defined(CONFIG_TARGET_VEXPRESS64_BASE_FVP) || \ |
89 | defined(CONFIG_TARGET_VEXPRESS64_BASE_FVP_DRAM) | |
261d2760 DR |
90 | #define GICD_BASE (0x2f000000) |
91 | #define GICC_BASE (0x2c000000) | |
ffc10373 LW |
92 | #elif CONFIG_TARGET_VEXPRESS64_JUNO |
93 | #define GICD_BASE (0x2C010000) | |
94 | #define GICC_BASE (0x2C02f000) | |
261d2760 | 95 | #endif |
03314f0e | 96 | #endif /* !CONFIG_GICV3 */ |
12916829 | 97 | |
12916829 | 98 | /* Size of malloc() pool */ |
5bcae13e | 99 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (8 << 20)) |
12916829 | 100 | |
8daec2d9 | 101 | #ifndef CONFIG_TARGET_VEXPRESS64_JUNO |
b31f9d7a | 102 | /* The Vexpress64 simulators use SMSC91C111 */ |
3865ceb7 BS |
103 | #define CONFIG_SMC91111 1 |
104 | #define CONFIG_SMC91111_BASE (0x01A000000) | |
b31f9d7a | 105 | #endif |
12916829 DF |
106 | |
107 | /* PL011 Serial Configuration */ | |
d8bafe13 | 108 | #define CONFIG_CONS_INDEX 0 |
ffc10373 LW |
109 | #ifdef CONFIG_TARGET_VEXPRESS64_JUNO |
110 | #define CONFIG_PL011_CLOCK 7273800 | |
111 | #else | |
12916829 | 112 | #define CONFIG_PL011_CLOCK 24000000 |
ffc10373 | 113 | #endif |
12916829 | 114 | |
12916829 | 115 | /*#define CONFIG_MENU_SHOW*/ |
12916829 DF |
116 | |
117 | /* BOOTP options */ | |
118 | #define CONFIG_BOOTP_BOOTFILESIZE | |
12916829 DF |
119 | |
120 | /* Miscellaneous configurable options */ | |
121 | #define CONFIG_SYS_LOAD_ADDR (V2M_BASE + 0x10000000) | |
122 | ||
123 | /* Physical Memory Map */ | |
12916829 | 124 | #define PHYS_SDRAM_1 (V2M_BASE) /* SDRAM Bank #1 */ |
30355708 LW |
125 | /* Top 16MB reserved for secure world use */ |
126 | #define DRAM_SEC_SIZE 0x01000000 | |
127 | #define PHYS_SDRAM_1_SIZE 0x80000000 - DRAM_SEC_SIZE | |
128 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 | |
129 | ||
2c2b2183 RH |
130 | #ifdef CONFIG_TARGET_VEXPRESS64_JUNO |
131 | #define CONFIG_NR_DRAM_BANKS 2 | |
132 | #define PHYS_SDRAM_2 (0x880000000) | |
133 | #define PHYS_SDRAM_2_SIZE 0x180000000 | |
134 | #else | |
135 | #define CONFIG_NR_DRAM_BANKS 1 | |
136 | #endif | |
137 | ||
30355708 | 138 | /* Enable memtest */ |
30355708 LW |
139 | #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 |
140 | #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE) | |
12916829 DF |
141 | |
142 | /* Initial environment variables */ | |
10d1491b LW |
143 | #ifdef CONFIG_TARGET_VEXPRESS64_JUNO |
144 | /* | |
145 | * Defines where the kernel and FDT exist in NOR flash and where it will | |
146 | * be copied into DRAM | |
147 | */ | |
148 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
ecbed5d6 RH |
149 | "kernel_name=norkern\0" \ |
150 | "kernel_alt_name=Image\0" \ | |
7babe482 | 151 | "kernel_addr=0x80080000\0" \ |
4a6bdb59 RH |
152 | "initrd_name=ramdisk.img\0" \ |
153 | "initrd_addr=0x84000000\0" \ | |
da3e620d | 154 | "fdtfile=board.dtb\0" \ |
ecbed5d6 | 155 | "fdt_alt_name=juno\0" \ |
10d1491b LW |
156 | "fdt_addr=0x83000000\0" \ |
157 | "fdt_high=0xffffffffffffffff\0" \ | |
158 | "initrd_high=0xffffffffffffffff\0" \ | |
159 | ||
10d1491b LW |
160 | /* Copy the kernel and FDT to DRAM memory and boot */ |
161 | #define CONFIG_BOOTCOMMAND "afs load ${kernel_name} ${kernel_addr} ; " \ | |
ecbed5d6 RH |
162 | "if test $? -eq 1; then "\ |
163 | " echo Loading ${kernel_alt_name} instead of "\ | |
164 | "${kernel_name}; "\ | |
165 | " afs load ${kernel_alt_name} ${kernel_addr};"\ | |
166 | "fi ; "\ | |
da3e620d | 167 | "afs load ${fdtfile} ${fdt_addr} ; " \ |
ecbed5d6 RH |
168 | "if test $? -eq 1; then "\ |
169 | " echo Loading ${fdt_alt_name} instead of "\ | |
da3e620d | 170 | "${fdtfile}; "\ |
ecbed5d6 RH |
171 | " afs load ${fdt_alt_name} ${fdt_addr}; "\ |
172 | "fi ; "\ | |
10d1491b | 173 | "fdt addr ${fdt_addr}; fdt resize; " \ |
4a6bdb59 RH |
174 | "if afs load ${initrd_name} ${initrd_addr} ; "\ |
175 | "then "\ | |
176 | " setenv initrd_param ${initrd_addr}; "\ | |
177 | " else setenv initrd_param -; "\ | |
178 | "fi ; " \ | |
179 | "booti ${kernel_addr} ${initrd_param} ${fdt_addr}" | |
10d1491b | 180 | |
10d1491b LW |
181 | |
182 | #elif CONFIG_TARGET_VEXPRESS64_BASE_FVP | |
261d2760 | 183 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
1fd0f92e | 184 | "kernel_name=Image\0" \ |
7babe482 | 185 | "kernel_addr=0x80080000\0" \ |
261d2760 | 186 | "initrd_name=ramdisk.img\0" \ |
49995ffe | 187 | "initrd_addr=0x88000000\0" \ |
da3e620d | 188 | "fdtfile=devtree.dtb\0" \ |
49995ffe | 189 | "fdt_addr=0x83000000\0" \ |
261d2760 DR |
190 | "fdt_high=0xffffffffffffffff\0" \ |
191 | "initrd_high=0xffffffffffffffff\0" | |
192 | ||
49995ffe | 193 | #define CONFIG_BOOTCOMMAND "smhload ${kernel_name} ${kernel_addr}; " \ |
da3e620d | 194 | "smhload ${fdtfile} ${fdt_addr}; " \ |
c0ae9703 RH |
195 | "smhload ${initrd_name} ${initrd_addr} "\ |
196 | "initrd_end; " \ | |
1fd0f92e LW |
197 | "fdt addr ${fdt_addr}; fdt resize; " \ |
198 | "fdt chosen ${initrd_addr} ${initrd_end}; " \ | |
199 | "booti $kernel_addr - $fdt_addr" | |
261d2760 | 200 | |
261d2760 | 201 | |
fc04b923 RH |
202 | #elif CONFIG_TARGET_VEXPRESS64_BASE_FVP_DRAM |
203 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
204 | "kernel_addr=0x80080000\0" \ | |
205 | "initrd_addr=0x84000000\0" \ | |
206 | "fdt_addr=0x83000000\0" \ | |
207 | "fdt_high=0xffffffffffffffff\0" \ | |
208 | "initrd_high=0xffffffffffffffff\0" | |
209 | ||
fc04b923 RH |
210 | #define CONFIG_BOOTCOMMAND "booti $kernel_addr $initrd_addr $fdt_addr" |
211 | ||
fc04b923 | 212 | |
261d2760 | 213 | #endif |
12916829 | 214 | |
12916829 DF |
215 | /* Monitor Command Prompt */ |
216 | #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ | |
12916829 DF |
217 | #define CONFIG_SYS_MAXARGS 64 /* max command args */ |
218 | ||
f3c71c93 RH |
219 | #ifdef CONFIG_TARGET_VEXPRESS64_JUNO |
220 | #define CONFIG_SYS_FLASH_BASE 0x08000000 | |
221 | /* 255 x 256KiB sectors + 4 x 64KiB sectors at the end = 259 */ | |
222 | #define CONFIG_SYS_MAX_FLASH_SECT 259 | |
223 | /* Store environment at top of flash in the same location as blank.img */ | |
224 | /* in the Juno firmware. */ | |
225 | #define CONFIG_ENV_ADDR 0x0BFC0000 | |
226 | #define CONFIG_ENV_SECT_SIZE 0x00010000 | |
14f264e6 | 227 | #else |
f3c71c93 RH |
228 | #define CONFIG_SYS_FLASH_BASE 0x0C000000 |
229 | /* 256 x 256KiB sectors */ | |
230 | #define CONFIG_SYS_MAX_FLASH_SECT 256 | |
231 | /* Store environment at top of flash */ | |
232 | #define CONFIG_ENV_ADDR 0x0FFC0000 | |
233 | #define CONFIG_ENV_SECT_SIZE 0x00040000 | |
234 | #endif | |
235 | ||
14f264e6 LW |
236 | #define CONFIG_SYS_FLASH_CFI 1 |
237 | #define CONFIG_FLASH_CFI_DRIVER 1 | |
f19f389f | 238 | #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT |
f3c71c93 | 239 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 |
14f264e6 | 240 | |
14f264e6 LW |
241 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* use buffered writes */ |
242 | #define CONFIG_SYS_FLASH_PROTECTION /* The devices have real protection */ | |
243 | #define CONFIG_SYS_FLASH_EMPTY_INFO /* flinfo indicates empty blocks */ | |
f3c71c93 RH |
244 | #define FLASH_MAX_SECTOR_SIZE 0x00040000 |
245 | #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE | |
14f264e6 | 246 | |
12916829 | 247 | #endif /* __VEXPRESS_AEMV8A_H */ |