[people/ms/u-boot.git] / include / configs / vexpress_aemv8a.h

/*
 * Configuration for Versatile Express. Parts were derived from other ARM
 *   configurations.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __VEXPRESS_AEMV8A_H
#define __VEXPRESS_AEMV8A_H

/* We use generic board for v8 Versatile Express */
#define CONFIG_SYS_GENERIC_BOARD

#ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP
#ifndef CONFIG_SEMIHOSTING
#error CONFIG_TARGET_VEXPRESS64_BASE_FVP requires CONFIG_SEMIHOSTING
#endif
#define CONFIG_BOARD_LATE_INIT
#define CONFIG_ARMV8_SWITCH_TO_EL1
#endif

#define CONFIG_REMAKE_ELF

#ifndef CONFIG_TARGET_VEXPRESS64_BASE_FVP
/* Base FVP and Juno not using GICv3 yet */
#define CONFIG_GICV3
#endif

/*#define CONFIG_ARMV8_SWITCH_TO_EL1*/

#define CONFIG_SYS_NO_FLASH

#define CONFIG_SUPPORT_RAW_INITRD

/* Cache Definitions */
#define CONFIG_SYS_DCACHE_OFF
#define CONFIG_SYS_ICACHE_OFF

#define CONFIG_IDENT_STRING		" vexpress_aemv8a"
#define CONFIG_BOOTP_VCI_STRING		"U-boot.armv8.vexpress_aemv8a"

/* Link Definitions */
#ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP
/* ATF loads u-boot here for BASE_FVP model */
#define CONFIG_SYS_TEXT_BASE		0x88000000
#define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_SDRAM_BASE + 0x03f00000)
#else
#define CONFIG_SYS_TEXT_BASE		0x80000000
#define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
#endif

/* Flat Device Tree Definitions */
#define CONFIG_OF_LIBFDT


/* SMP Spin Table Definitions */
#ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP
#define CPU_RELEASE_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x03f00000)
#else
#define CPU_RELEASE_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x7fff0)
#endif

/* CS register bases for the original memory map. */
#define V2M_PA_CS0			0x00000000
#define V2M_PA_CS1			0x14000000
#define V2M_PA_CS2			0x18000000
#define V2M_PA_CS3			0x1c000000
#define V2M_PA_CS4			0x0c000000
#define V2M_PA_CS5			0x10000000

#define V2M_PERIPH_OFFSET(x)		(x << 16)
#define V2M_SYSREGS			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(1))
#define V2M_SYSCTL			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(2))
#define V2M_SERIAL_BUS_PCI		(V2M_PA_CS3 + V2M_PERIPH_OFFSET(3))

#define V2M_BASE			0x80000000

/*
 * Physical addresses, offset from V2M_PA_CS0-3
 */
#define V2M_NOR0			(V2M_PA_CS0)
#define V2M_NOR1			(V2M_PA_CS4)
#define V2M_SRAM			(V2M_PA_CS1)

/* Common peripherals relative to CS7. */
#define V2M_AACI			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(4))
#define V2M_MMCI			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(5))
#define V2M_KMI0			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(6))
#define V2M_KMI1			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(7))

#define V2M_UART0			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(9))
#define V2M_UART1			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(10))
#define V2M_UART2			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(11))
#define V2M_UART3			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(12))

#define V2M_WDT				(V2M_PA_CS3 + V2M_PERIPH_OFFSET(15))

#define V2M_TIMER01			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(17))
#define V2M_TIMER23			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(18))

#define V2M_SERIAL_BUS_DVI		(V2M_PA_CS3 + V2M_PERIPH_OFFSET(22))
#define V2M_RTC				(V2M_PA_CS3 + V2M_PERIPH_OFFSET(23))

#define V2M_CF				(V2M_PA_CS3 + V2M_PERIPH_OFFSET(26))

#define V2M_CLCD			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(31))

/* System register offsets. */
#define V2M_SYS_CFGDATA			(V2M_SYSREGS + 0x0a0)
#define V2M_SYS_CFGCTRL			(V2M_SYSREGS + 0x0a4)
#define V2M_SYS_CFGSTAT			(V2M_SYSREGS + 0x0a8)

/* Generic Timer Definitions */
#define COUNTER_FREQUENCY		(0x1800000)	/* 24MHz */

/* Generic Interrupt Controller Definitions */
#ifdef CONFIG_GICV3
#define GICD_BASE			(0x2f000000)
#define GICR_BASE			(0x2f100000)
#else

#ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP
#define GICD_BASE			(0x2f000000)
#define GICC_BASE			(0x2c000000)
#else
#define GICD_BASE			(0x2C001000)
#define GICC_BASE			(0x2C002000)
#endif
#endif

#define CONFIG_SYS_MEMTEST_START	V2M_BASE
#define CONFIG_SYS_MEMTEST_END		(V2M_BASE + 0x80000000)

/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (8 << 20))

/* SMSC91C111 Ethernet Configuration */
#define CONFIG_SMC91111			1
#define CONFIG_SMC91111_BASE		(0x01A000000)

/* PL011 Serial Configuration */
#define CONFIG_PL011_SERIAL
#define CONFIG_PL011_CLOCK		24000000
#define CONFIG_PL01x_PORTS		{(void *)CONFIG_SYS_SERIAL0, \
					 (void *)CONFIG_SYS_SERIAL1}
#define CONFIG_CONS_INDEX		0

#define CONFIG_BAUDRATE			115200
#define CONFIG_SYS_SERIAL0		V2M_UART0
#define CONFIG_SYS_SERIAL1		V2M_UART1

/* Command line configuration */
#define CONFIG_MENU
/*#define CONFIG_MENU_SHOW*/
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_BDI
#define CONFIG_CMD_BOOTI
#define CONFIG_CMD_UNZIP
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_PXE
#define CONFIG_CMD_ENV
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_IMI
#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_MII
#define CONFIG_CMD_NET
#define CONFIG_CMD_PING
#define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_RUN
#define CONFIG_CMD_BOOTD
#define CONFIG_CMD_ECHO
#define CONFIG_CMD_SOURCE
#define CONFIG_CMD_FAT
#define CONFIG_DOS_PARTITION

/* BOOTP options */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_PXE
#define CONFIG_BOOTP_PXE_CLIENTARCH	0x100

/* Miscellaneous configurable options */
#define CONFIG_SYS_LOAD_ADDR		(V2M_BASE + 0x10000000)

/* Physical Memory Map */
#define CONFIG_NR_DRAM_BANKS		1
#define PHYS_SDRAM_1			(V2M_BASE)	/* SDRAM Bank #1 */
#define PHYS_SDRAM_1_SIZE		0x80000000	/* 2048 MB */
#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1

/* Initial environment variables */
#ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP
#define CONFIG_EXTRA_ENV_SETTINGS	\
				"kernel_name=uImage\0"	\
				"kernel_addr_r=0x80000000\0"	\
				"initrd_name=ramdisk.img\0"	\
				"initrd_addr_r=0x88000000\0"	\
				"fdt_name=devtree.dtb\0"		\
				"fdt_addr_r=0x83000000\0"		\
				"fdt_high=0xffffffffffffffff\0"	\
				"initrd_high=0xffffffffffffffff\0"

#define CONFIG_BOOTARGS		"console=ttyAMA0 earlyprintk=pl011,"\
				"0x1c090000 debug user_debug=31 "\
				"loglevel=9"

#define CONFIG_BOOTCOMMAND	"fdt addr $fdt_addr_r; fdt resize; " \
				"fdt chosen $initrd_addr_r $initrd_end; " \
				"bootm $kernel_addr_r - $fdt_addr_r"

#define CONFIG_BOOTDELAY		1

#else

#define CONFIG_EXTRA_ENV_SETTINGS	\
					"kernel_addr_r=0x80000000\0"	\
					"initrd_addr_r=0x88000000\0"	\
					"fdt_addr_r=0x83000000\0"		\
					"fdt_high=0xa0000000\0"

#define CONFIG_BOOTARGS			"console=ttyAMA0 root=/dev/ram0"
#define CONFIG_BOOTCOMMAND		"bootm $kernel_addr_r " \
					"$initrd_addr_r:$initrd_size $fdt_addr_r"
#define CONFIG_BOOTDELAY		-1
#endif

/* Do not preserve environment */
#define CONFIG_ENV_IS_NOWHERE		1
#define CONFIG_ENV_SIZE			0x1000

/* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
#define CONFIG_SYS_PROMPT		"VExpress64# "
#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
					sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
#define CONFIG_SYS_LONGHELP
#define CONFIG_CMDLINE_EDITING
#define CONFIG_SYS_MAXARGS		64	/* max command args */

#endif /* __VEXPRESS_AEMV8A_H */
Commit	Line	Data
12916829 DF	1	/*
	2	* Configuration for Versatile Express. Parts were derived from other ARM
	3	* configurations.
	4	*
	5	* SPDX-License-Identifier: GPL-2.0+
	6	*/
	7
	8	#ifndef __VEXPRESS_AEMV8A_H
	9	#define __VEXPRESS_AEMV8A_H
	10
03ca6a39 LW	11	/* We use generic board for v8 Versatile Express */
	12	#define CONFIG_SYS_GENERIC_BOARD
	13
f91afc4d	14	#ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP
261d2760	15	#ifndef CONFIG_SEMIHOSTING
f91afc4d	16	#error CONFIG_TARGET_VEXPRESS64_BASE_FVP requires CONFIG_SEMIHOSTING
261d2760 DR	17	#endif
	18	#define CONFIG_BOARD_LATE_INIT
	19	#define CONFIG_ARMV8_SWITCH_TO_EL1
	20	#endif
	21
12916829 DF	22	#define CONFIG_REMAKE_ELF
12916829 DF	23
f91afc4d LW	24	#ifndef CONFIG_TARGET_VEXPRESS64_BASE_FVP
f91afc4d LW	25	/* Base FVP and Juno not using GICv3 yet */
c71645ad	26	#define CONFIG_GICV3
261d2760	27	#endif
c71645ad	28
12916829 DF	29	/#define CONFIG_ARMV8_SWITCH_TO_EL1/
12916829 DF	30
12916829 DF	31	#define CONFIG_SYS_NO_FLASH
	32
	33	#define CONFIG_SUPPORT_RAW_INITRD
	34
	35	/* Cache Definitions */
	36	#define CONFIG_SYS_DCACHE_OFF
	37	#define CONFIG_SYS_ICACHE_OFF
	38
	39	#define CONFIG_IDENT_STRING " vexpress_aemv8a"
	40	#define CONFIG_BOOTP_VCI_STRING "U-boot.armv8.vexpress_aemv8a"
	41
	42	/* Link Definitions */
f91afc4d	43	#ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP
261d2760 DR	44	/* ATF loads u-boot here for BASE_FVP model */
	45	#define CONFIG_SYS_TEXT_BASE 0x88000000
	46	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x03f00000)
	47	#else
12916829 DF	48	#define CONFIG_SYS_TEXT_BASE 0x80000000
12916829 DF	49	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
261d2760	50	#endif
12916829 DF	51
	52	/* Flat Device Tree Definitions */
	53	#define CONFIG_OF_LIBFDT
	54
12916829 DF	55
12916829 DF	56	/* SMP Spin Table Definitions */
f91afc4d	57	#ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP
261d2760 DR	58	#define CPU_RELEASE_ADDR (CONFIG_SYS_SDRAM_BASE + 0x03f00000)
261d2760 DR	59	#else
12916829	60	#define CPU_RELEASE_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
261d2760	61	#endif
12916829 DF	62
	63	/* CS register bases for the original memory map. */
	64	#define V2M_PA_CS0 0x00000000
	65	#define V2M_PA_CS1 0x14000000
	66	#define V2M_PA_CS2 0x18000000
	67	#define V2M_PA_CS3 0x1c000000
	68	#define V2M_PA_CS4 0x0c000000
	69	#define V2M_PA_CS5 0x10000000
	70
	71	#define V2M_PERIPH_OFFSET(x) (x << 16)
	72	#define V2M_SYSREGS (V2M_PA_CS3 + V2M_PERIPH_OFFSET(1))
	73	#define V2M_SYSCTL (V2M_PA_CS3 + V2M_PERIPH_OFFSET(2))
	74	#define V2M_SERIAL_BUS_PCI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(3))
	75
	76	#define V2M_BASE 0x80000000
	77
	78	/*
	79	* Physical addresses, offset from V2M_PA_CS0-3
	80	*/
	81	#define V2M_NOR0 (V2M_PA_CS0)
	82	#define V2M_NOR1 (V2M_PA_CS4)
	83	#define V2M_SRAM (V2M_PA_CS1)
	84
	85	/* Common peripherals relative to CS7. */
	86	#define V2M_AACI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(4))
	87	#define V2M_MMCI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(5))
	88	#define V2M_KMI0 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(6))
	89	#define V2M_KMI1 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(7))
	90
	91	#define V2M_UART0 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(9))
	92	#define V2M_UART1 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(10))
	93	#define V2M_UART2 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(11))
	94	#define V2M_UART3 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(12))
	95
	96	#define V2M_WDT (V2M_PA_CS3 + V2M_PERIPH_OFFSET(15))
	97
	98	#define V2M_TIMER01 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(17))
	99	#define V2M_TIMER23 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(18))
	100
	101	#define V2M_SERIAL_BUS_DVI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(22))
	102	#define V2M_RTC (V2M_PA_CS3 + V2M_PERIPH_OFFSET(23))
	103
	104	#define V2M_CF (V2M_PA_CS3 + V2M_PERIPH_OFFSET(26))
	105
	106	#define V2M_CLCD (V2M_PA_CS3 + V2M_PERIPH_OFFSET(31))
	107
	108	/* System register offsets. */
	109	#define V2M_SYS_CFGDATA (V2M_SYSREGS + 0x0a0)
	110	#define V2M_SYS_CFGCTRL (V2M_SYSREGS + 0x0a4)
	111	#define V2M_SYS_CFGSTAT (V2M_SYSREGS + 0x0a8)
	112
	113	/* Generic Timer Definitions */
	114	#define COUNTER_FREQUENCY (0x1800000) /* 24MHz */
	115
	116	/* Generic Interrupt Controller Definitions */
c71645ad DF	117	#ifdef CONFIG_GICV3
	118	#define GICD_BASE (0x2f000000)
	119	#define GICR_BASE (0x2f100000)
	120	#else
261d2760	121
f91afc4d	122	#ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP
261d2760 DR	123	#define GICD_BASE (0x2f000000)
	124	#define GICC_BASE (0x2c000000)
	125	#else
12916829 DF	126	#define GICD_BASE (0x2C001000)
12916829 DF	127	#define GICC_BASE (0x2C002000)
c71645ad	128	#endif
261d2760	129	#endif
12916829 DF	130
	131	#define CONFIG_SYS_MEMTEST_START V2M_BASE
	132	#define CONFIG_SYS_MEMTEST_END (V2M_BASE + 0x80000000)
	133
	134	/* Size of malloc() pool */
5bcae13e	135	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (8 << 20))
12916829	136
3865ceb7 BS	137	/* SMSC91C111 Ethernet Configuration */
	138	#define CONFIG_SMC91111 1
	139	#define CONFIG_SMC91111_BASE (0x01A000000)
12916829 DF	140
	141	/* PL011 Serial Configuration */
	142	#define CONFIG_PL011_SERIAL
	143	#define CONFIG_PL011_CLOCK 24000000
	144	#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0, \
	145	(void *)CONFIG_SYS_SERIAL1}
	146	#define CONFIG_CONS_INDEX 0
	147
	148	#define CONFIG_BAUDRATE 115200
12916829 DF	149	#define CONFIG_SYS_SERIAL0 V2M_UART0
	150	#define CONFIG_SYS_SERIAL1 V2M_UART1
	151
	152	/* Command line configuration */
	153	#define CONFIG_MENU
	154	/#define CONFIG_MENU_SHOW/
	155	#define CONFIG_CMD_CACHE
	156	#define CONFIG_CMD_BDI
67172528 TR	157	#define CONFIG_CMD_BOOTI
67172528 TR	158	#define CONFIG_CMD_UNZIP
12916829 DF	159	#define CONFIG_CMD_DHCP
	160	#define CONFIG_CMD_PXE
	161	#define CONFIG_CMD_ENV
	162	#define CONFIG_CMD_FLASH
	163	#define CONFIG_CMD_IMI
	164	#define CONFIG_CMD_MEMORY
	165	#define CONFIG_CMD_MII
	166	#define CONFIG_CMD_NET
	167	#define CONFIG_CMD_PING
	168	#define CONFIG_CMD_SAVEENV
	169	#define CONFIG_CMD_RUN
	170	#define CONFIG_CMD_BOOTD
	171	#define CONFIG_CMD_ECHO
	172	#define CONFIG_CMD_SOURCE
	173	#define CONFIG_CMD_FAT
	174	#define CONFIG_DOS_PARTITION
	175
	176	/* BOOTP options */
	177	#define CONFIG_BOOTP_BOOTFILESIZE
	178	#define CONFIG_BOOTP_BOOTPATH
	179	#define CONFIG_BOOTP_GATEWAY
	180	#define CONFIG_BOOTP_HOSTNAME
	181	#define CONFIG_BOOTP_PXE
	182	#define CONFIG_BOOTP_PXE_CLIENTARCH 0x100
	183
	184	/* Miscellaneous configurable options */
	185	#define CONFIG_SYS_LOAD_ADDR (V2M_BASE + 0x10000000)
	186
	187	/* Physical Memory Map */
	188	#define CONFIG_NR_DRAM_BANKS 1
	189	#define PHYS_SDRAM_1 (V2M_BASE) /* SDRAM Bank #1 */
	190	#define PHYS_SDRAM_1_SIZE 0x80000000 /* 2048 MB */
	191	#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
	192
	193	/* Initial environment variables */
f91afc4d	194	#ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP
261d2760 DR	195	#define CONFIG_EXTRA_ENV_SETTINGS \
	196	"kernel_name=uImage\0" \
	197	"kernel_addr_r=0x80000000\0" \
	198	"initrd_name=ramdisk.img\0" \
	199	"initrd_addr_r=0x88000000\0" \
	200	"fdt_name=devtree.dtb\0" \
	201	"fdt_addr_r=0x83000000\0" \
	202	"fdt_high=0xffffffffffffffff\0" \
	203	"initrd_high=0xffffffffffffffff\0"
	204
	205	#define CONFIG_BOOTARGS "console=ttyAMA0 earlyprintk=pl011,"\
	206	"0x1c090000 debug user_debug=31 "\
	207	"loglevel=9"
	208
	209	#define CONFIG_BOOTCOMMAND "fdt addr $fdt_addr_r; fdt resize; " \
	210	"fdt chosen $initrd_addr_r $initrd_end; " \
	211	"bootm $kernel_addr_r - $fdt_addr_r"
	212
	213	#define CONFIG_BOOTDELAY 1
	214
	215	#else
	216
12916829	217	#define CONFIG_EXTRA_ENV_SETTINGS \
5bcae13e TR	218	"kernel_addr_r=0x80000000\0" \
	219	"initrd_addr_r=0x88000000\0" \
	220	"fdt_addr_r=0x83000000\0" \
12916829 DF	221	"fdt_high=0xa0000000\0"
	222
	223	#define CONFIG_BOOTARGS "console=ttyAMA0 root=/dev/ram0"
261d2760 DR	224	#define CONFIG_BOOTCOMMAND "bootm $kernel_addr_r " \
261d2760 DR	225	"$initrd_addr_r:$initrd_size $fdt_addr_r"
12916829	226	#define CONFIG_BOOTDELAY -1
261d2760	227	#endif
12916829 DF	228
	229	/* Do not preserve environment */
	230	#define CONFIG_ENV_IS_NOWHERE 1
	231	#define CONFIG_ENV_SIZE 0x1000
	232
	233	/* Monitor Command Prompt */
	234	#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
	235	#define CONFIG_SYS_PROMPT "VExpress64# "
	236	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
	237	sizeof(CONFIG_SYS_PROMPT) + 16)
	238	#define CONFIG_SYS_HUSH_PARSER
12916829 DF	239	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
12916829 DF	240	#define CONFIG_SYS_LONGHELP
5bcae13e	241	#define CONFIG_CMDLINE_EDITING
12916829 DF	242	#define CONFIG_SYS_MAXARGS 64 /* max command args */
	243
	244	#endif /* __VEXPRESS_AEMV8A_H */