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8c653124 AW |
1 | /* |
2 | * Copyright 2013 Freescale Semiconductor, Inc. | |
3 | * | |
4 | * Configuration settings for the Freescale Vybrid vf610twr board. | |
5 | * | |
1a459660 | 6 | * SPDX-License-Identifier: GPL-2.0+ |
8c653124 AW |
7 | */ |
8 | ||
9 | #ifndef __CONFIG_H | |
10 | #define __CONFIG_H | |
11 | ||
12 | #include <asm/arch/imx-regs.h> | |
8c653124 | 13 | |
18fb0e3c | 14 | #define CONFIG_SYS_FSL_CLK |
8c653124 AW |
15 | |
16 | #define CONFIG_MACH_TYPE 4146 | |
17 | ||
18 | #define CONFIG_SKIP_LOWLEVEL_INIT | |
19 | ||
20 | /* Enable passing of ATAGs */ | |
21 | #define CONFIG_CMDLINE_TAG | |
22 | ||
8c653124 AW |
23 | #ifdef CONFIG_CMD_FUSE |
24 | #define CONFIG_MXC_OCOTP | |
25 | #endif | |
26 | ||
27 | /* Size of malloc() pool */ | |
28 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024) | |
29 | ||
8c653124 AW |
30 | /* Allow to overwrite serial and ethaddr */ |
31 | #define CONFIG_ENV_OVERWRITE | |
8c653124 | 32 | |
d6d07a9b SA |
33 | /* NAND support */ |
34 | #define CONFIG_CMD_NAND | |
35 | #define CONFIG_CMD_NAND_TRIMFFS | |
8fca2d8c | 36 | #define CONFIG_SYS_NAND_ONFI_DETECTION |
d6d07a9b SA |
37 | |
38 | #ifdef CONFIG_CMD_NAND | |
d6d07a9b SA |
39 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 |
40 | #define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR | |
41 | ||
d6d07a9b | 42 | /* Dynamic MTD partition support */ |
d6d07a9b SA |
43 | #define CONFIG_MTD_PARTITIONS |
44 | #define CONFIG_MTD_DEVICE | |
45 | #define MTDIDS_DEFAULT "nand0=fsl_nfc" | |
46 | #define MTDPARTS_DEFAULT "mtdparts=fsl_nfc:" \ | |
47 | "128k(vf-bcb)ro," \ | |
48 | "1408k(u-boot)ro," \ | |
49 | "512k(u-boot-env)," \ | |
50 | "4m(kernel)," \ | |
51 | "512k(fdt)," \ | |
52 | "-(rootfs)" | |
53 | #endif | |
54 | ||
8c653124 AW |
55 | #define CONFIG_FSL_ESDHC |
56 | #define CONFIG_SYS_FSL_ESDHC_ADDR 0 | |
57 | #define CONFIG_SYS_FSL_ESDHC_NUM 1 | |
58 | ||
8c653124 AW |
59 | #define CONFIG_FEC_MXC |
60 | #define CONFIG_MII | |
61 | #define IMX_FEC_BASE ENET_BASE_ADDR | |
62 | #define CONFIG_FEC_XCV_TYPE RMII | |
63 | #define CONFIG_FEC_MXC_PHYADDR 0 | |
64 | #define CONFIG_PHYLIB | |
65 | #define CONFIG_PHY_MICREL | |
66 | ||
cb6d04d6 | 67 | /* QSPI Configs*/ |
cb6d04d6 CF |
68 | |
69 | #ifdef CONFIG_FSL_QSPI | |
cb6d04d6 CF |
70 | #define FSL_QSPI_FLASH_SIZE (1 << 24) |
71 | #define FSL_QSPI_FLASH_NUM 2 | |
72 | #define CONFIG_SYS_FSL_QSPI_LE | |
73 | #endif | |
74 | ||
1221b3d7 | 75 | /* I2C Configs */ |
b089d039 | 76 | #define CONFIG_SYS_I2C |
77 | #define CONFIG_SYS_I2C_MXC | |
03544c66 AA |
78 | #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ |
79 | #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ | |
b089d039 | 80 | #define CONFIG_SYS_SPD_BUS_NUM 0 |
1221b3d7 | 81 | |
8c653124 | 82 | |
cf04ad32 | 83 | #define CONFIG_SYS_LOAD_ADDR 0x82000000 |
b188067f SA |
84 | |
85 | /* We boot from the gfxRAM area of the OCRAM. */ | |
86 | #define CONFIG_SYS_TEXT_BASE 0x3f408000 | |
87 | #define CONFIG_BOARD_SIZE_LIMIT 524288 | |
8c653124 | 88 | |
cf04ad32 SA |
89 | /* |
90 | * We do have 128MB of memory on the Vybrid Tower board. Leave the last | |
91 | * 16MB alone to avoid conflicts with Cortex-M4 firmwares running from | |
92 | * DDR3. Hence, limit the memory range for image processing to 112MB | |
93 | * using bootm_size. All of the following must be within this range. | |
94 | * We have the default load at 32MB into DDR (for the kernel), FDT at | |
95 | * 64MB and the ramdisk 512KB above that (allowing for hopefully never | |
96 | * seen large trees). This allows a reasonable split between ramdisk | |
97 | * and kernel size, where the ram disk can be a bit larger. | |
98 | */ | |
99 | #define MEM_LAYOUT_ENV_SETTINGS \ | |
100 | "bootm_size=0x07000000\0" \ | |
101 | "loadaddr=0x82000000\0" \ | |
102 | "kernel_addr_r=0x82000000\0" \ | |
103 | "fdt_addr=0x84000000\0" \ | |
104 | "fdt_addr_r=0x84000000\0" \ | |
105 | "rdaddr=0x84080000\0" \ | |
106 | "ramdisk_addr_r=0x84080000\0" | |
107 | ||
ca21f61e | 108 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
cf04ad32 | 109 | MEM_LAYOUT_ENV_SETTINGS \ |
ca21f61e | 110 | "script=boot.scr\0" \ |
c0a5b081 | 111 | "image=zImage\0" \ |
ca21f61e | 112 | "console=ttyLP1\0" \ |
ca21f61e | 113 | "fdt_file=vf610-twr.dtb\0" \ |
ca21f61e OS |
114 | "boot_fdt=try\0" \ |
115 | "ip_dyn=yes\0" \ | |
116 | "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ | |
117 | "mmcpart=1\0" \ | |
118 | "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \ | |
119 | "update_sd_firmware_filename=u-boot.imx\0" \ | |
120 | "update_sd_firmware=" \ | |
121 | "if test ${ip_dyn} = yes; then " \ | |
122 | "setenv get_cmd dhcp; " \ | |
123 | "else " \ | |
124 | "setenv get_cmd tftp; " \ | |
125 | "fi; " \ | |
126 | "if mmc dev ${mmcdev}; then " \ | |
127 | "if ${get_cmd} ${update_sd_firmware_filename}; then " \ | |
128 | "setexpr fw_sz ${filesize} / 0x200; " \ | |
129 | "setexpr fw_sz ${fw_sz} + 1; " \ | |
130 | "mmc write ${loadaddr} 0x2 ${fw_sz}; " \ | |
131 | "fi; " \ | |
132 | "fi\0" \ | |
133 | "mmcargs=setenv bootargs console=${console},${baudrate} " \ | |
134 | "root=${mmcroot}\0" \ | |
135 | "loadbootscript=" \ | |
136 | "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ | |
137 | "bootscript=echo Running bootscript from mmc ...; " \ | |
138 | "source\0" \ | |
c0a5b081 | 139 | "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ |
ca21f61e OS |
140 | "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ |
141 | "mmcboot=echo Booting from mmc ...; " \ | |
142 | "run mmcargs; " \ | |
143 | "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ | |
144 | "if run loadfdt; then " \ | |
c0a5b081 | 145 | "bootz ${loadaddr} - ${fdt_addr}; " \ |
ca21f61e OS |
146 | "else " \ |
147 | "if test ${boot_fdt} = try; then " \ | |
c0a5b081 | 148 | "bootz; " \ |
ca21f61e OS |
149 | "else " \ |
150 | "echo WARN: Cannot load the DT; " \ | |
151 | "fi; " \ | |
152 | "fi; " \ | |
153 | "else " \ | |
c0a5b081 | 154 | "bootz; " \ |
ca21f61e OS |
155 | "fi;\0" \ |
156 | "netargs=setenv bootargs console=${console},${baudrate} " \ | |
157 | "root=/dev/nfs " \ | |
158 | "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ | |
159 | "netboot=echo Booting from net ...; " \ | |
160 | "run netargs; " \ | |
161 | "if test ${ip_dyn} = yes; then " \ | |
162 | "setenv get_cmd dhcp; " \ | |
163 | "else " \ | |
164 | "setenv get_cmd tftp; " \ | |
165 | "fi; " \ | |
c0a5b081 | 166 | "${get_cmd} ${image}; " \ |
ca21f61e OS |
167 | "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ |
168 | "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ | |
c0a5b081 | 169 | "bootz ${loadaddr} - ${fdt_addr}; " \ |
ca21f61e OS |
170 | "else " \ |
171 | "if test ${boot_fdt} = try; then " \ | |
c0a5b081 | 172 | "bootz; " \ |
ca21f61e OS |
173 | "else " \ |
174 | "echo WARN: Cannot load the DT; " \ | |
175 | "fi; " \ | |
176 | "fi; " \ | |
177 | "else " \ | |
c0a5b081 | 178 | "bootz; " \ |
ca21f61e OS |
179 | "fi;\0" |
180 | ||
181 | #define CONFIG_BOOTCOMMAND \ | |
182 | "mmc dev ${mmcdev}; if mmc rescan; then " \ | |
183 | "if run loadbootscript; then " \ | |
184 | "run bootscript; " \ | |
185 | "else " \ | |
c0a5b081 | 186 | "if run loadimage; then " \ |
ca21f61e OS |
187 | "run mmcboot; " \ |
188 | "else run netboot; " \ | |
189 | "fi; " \ | |
190 | "fi; " \ | |
191 | "else run netboot; fi" | |
192 | ||
8c653124 AW |
193 | /* Miscellaneous configurable options */ |
194 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
8c653124 AW |
195 | #undef CONFIG_AUTO_COMPLETE |
196 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
197 | #define CONFIG_SYS_PBSIZE \ | |
198 | (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) | |
199 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
200 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE | |
201 | ||
8c653124 AW |
202 | #define CONFIG_SYS_MEMTEST_START 0x80010000 |
203 | #define CONFIG_SYS_MEMTEST_END 0x87C00000 | |
204 | ||
8c653124 AW |
205 | /* Physical memory map */ |
206 | #define CONFIG_NR_DRAM_BANKS 1 | |
207 | #define PHYS_SDRAM (0x80000000) | |
208 | #define PHYS_SDRAM_SIZE (128 * 1024 * 1024) | |
209 | ||
210 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM | |
211 | #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR | |
212 | #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE | |
213 | ||
214 | #define CONFIG_SYS_INIT_SP_OFFSET \ | |
215 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) | |
216 | #define CONFIG_SYS_INIT_SP_ADDR \ | |
217 | (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) | |
218 | ||
d6d07a9b | 219 | #ifdef CONFIG_ENV_IS_IN_MMC |
8c653124 | 220 | #define CONFIG_ENV_SIZE (8 * 1024) |
8c653124 AW |
221 | |
222 | #define CONFIG_ENV_OFFSET (12 * 64 * 1024) | |
223 | #define CONFIG_SYS_MMC_ENV_DEV 0 | |
d6d07a9b SA |
224 | #endif |
225 | ||
226 | #ifdef CONFIG_ENV_IS_IN_NAND | |
227 | #define CONFIG_ENV_SIZE (64 * 2048) | |
228 | #define CONFIG_ENV_SECT_SIZE (64 * 2048) | |
229 | #define CONFIG_ENV_RANGE (512 * 1024) | |
230 | #define CONFIG_ENV_OFFSET 0x180000 | |
231 | #endif | |
8c653124 | 232 | |
8c653124 | 233 | #endif |