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f8f8acd7 SB |
1 | /* |
2 | * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de> | |
3 | * | |
4 | * (C) Copyright 2009 Freescale Semiconductor, Inc. | |
5 | * | |
6 | * Configuration settings for the MX51-3Stack Freescale board. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | #ifndef __CONFIG_H | |
25 | #define __CONFIG_H | |
26 | ||
f8f8acd7 SB |
27 | |
28 | #define CONFIG_MX51 /* in a mx51 */ | |
c02d8280 | 29 | #define CONFIG_SYS_TEXT_BASE 0x97800000 |
f8f8acd7 | 30 | |
595f3e56 LHR |
31 | #include <asm/arch/imx-regs.h> |
32 | ||
ff9f475d JL |
33 | #define CONFIG_SYS_MX5_HCLK 24000000 |
34 | #define CONFIG_SYS_MX5_CLK32 32768 | |
f8f8acd7 SB |
35 | #define CONFIG_DISPLAY_CPUINFO |
36 | #define CONFIG_DISPLAY_BOARDINFO | |
37 | ||
38 | #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ | |
39 | #define CONFIG_REVISION_TAG | |
40 | #define CONFIG_SETUP_MEMORY_TAGS | |
41 | #define CONFIG_INITRD_TAG | |
9660e442 | 42 | #define CONFIG_BOARD_LATE_INIT |
f8f8acd7 | 43 | |
db545e49 FE |
44 | #define CONFIG_MACH_TYPE MACH_TYPE_TTC_VISION2 |
45 | ||
f8f8acd7 SB |
46 | /* |
47 | * Size of malloc() pool | |
48 | */ | |
e9934f0b | 49 | #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) |
f8f8acd7 | 50 | |
f8f8acd7 SB |
51 | /* |
52 | * Hardware drivers | |
53 | */ | |
54 | #define CONFIG_MXC_UART | |
55 | #define CONFIG_SYS_MX51_UART3 | |
56 | #define CONFIG_MXC_GPIO | |
57 | #define CONFIG_MXC_SPI | |
58 | #define CONFIG_HW_WATCHDOG | |
59 | ||
60 | /* | |
61 | * SPI Configs | |
62 | * */ | |
63 | #define CONFIG_FSL_SF | |
64 | #define CONFIG_CMD_SF | |
65 | ||
66 | #define CONFIG_SPI_FLASH | |
67 | #define CONFIG_SPI_FLASH_STMICRO | |
68 | ||
69 | /* | |
70 | * Use gpio 4 pin 25 as chip select for SPI flash | |
71 | * This corresponds to gpio 121 | |
72 | */ | |
73 | #define CONFIG_SPI_FLASH_CS (1 | (121 << 8)) | |
74 | #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 | |
75 | #define CONFIG_SF_DEFAULT_SPEED 25000000 | |
76 | ||
77 | #define CONFIG_ENV_SPI_CS (1 | (121 << 8)) | |
78 | #define CONFIG_ENV_SPI_BUS 0 | |
79 | #define CONFIG_ENV_SPI_MAX_HZ 25000000 | |
80 | #define CONFIG_ENV_SPI_MODE SPI_MODE_0 | |
81 | ||
82 | #define CONFIG_ENV_OFFSET (6 * 64 * 1024) | |
83 | #define CONFIG_ENV_SECT_SIZE (1 * 64 * 1024) | |
84 | #define CONFIG_ENV_SIZE (4 * 1024) | |
85 | ||
86 | #define CONFIG_FSL_ENV_IN_SF | |
87 | #define CONFIG_ENV_IS_IN_SPI_FLASH | |
88 | ||
89 | /* PMIC Controller */ | |
bac395ee SB |
90 | #define CONFIG_PMIC |
91 | #define CONFIG_PMIC_SPI | |
92 | #define CONFIG_PMIC_FSL | |
f8f8acd7 SB |
93 | #define CONFIG_FSL_PMIC_BUS 0 |
94 | #define CONFIG_FSL_PMIC_CS 0 | |
95 | #define CONFIG_FSL_PMIC_CLK 2500000 | |
96 | #define CONFIG_FSL_PMIC_MODE SPI_MODE_0 | |
bac395ee | 97 | #define CONFIG_FSL_PMIC_BITLEN 32 |
4e8b7544 | 98 | #define CONFIG_RTC_MC13XXX |
f8f8acd7 SB |
99 | |
100 | /* | |
101 | * MMC Configs | |
102 | */ | |
103 | #define CONFIG_FSL_ESDHC | |
104 | #ifdef CONFIG_FSL_ESDHC | |
105 | #define CONFIG_SYS_FSL_ESDHC_ADDR (0x70004000) | |
106 | #define CONFIG_SYS_FSL_ESDHC_NUM 1 | |
107 | ||
108 | #define CONFIG_MMC | |
109 | ||
110 | #define CONFIG_CMD_MMC | |
111 | #define CONFIG_GENERIC_MMC | |
112 | #define CONFIG_CMD_FAT | |
113 | #define CONFIG_DOS_PARTITION | |
114 | #endif | |
115 | ||
116 | #define CONFIG_CMD_DATE | |
117 | ||
118 | /* | |
119 | * Eth Configs | |
120 | */ | |
121 | #define CONFIG_HAS_ETH1 | |
f8f8acd7 SB |
122 | #define CONFIG_MII |
123 | #define CONFIG_DISCOVER_PHY | |
124 | ||
125 | #define CONFIG_FEC_MXC | |
126 | #define IMX_FEC_BASE FEC_BASE_ADDR | |
127 | #define CONFIG_FEC_MXC_PHYADDR 0x1F | |
128 | ||
129 | #define CONFIG_CMD_PING | |
130 | #define CONFIG_CMD_MII | |
131 | #define CONFIG_CMD_NET | |
132 | ||
133 | /* allow to overwrite serial and ethaddr */ | |
134 | #define CONFIG_ENV_OVERWRITE | |
135 | #define CONFIG_CONS_INDEX 3 | |
136 | #define CONFIG_BAUDRATE 115200 | |
137 | #define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200} | |
138 | ||
139 | /*********************************************************** | |
140 | * Command definition | |
141 | ***********************************************************/ | |
142 | ||
143 | #include <config_cmd_default.h> | |
144 | ||
145 | #define CONFIG_CMD_SPI | |
146 | #undef CONFIG_CMD_IMLS | |
147 | ||
148 | #define CONFIG_BOOTDELAY 3 | |
149 | ||
150 | #define CONFIG_LOADADDR 0x90800000 /* loadaddr env var */ | |
151 | ||
152 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
153 | "netdev=eth0\0" \ | |
154 | "loadaddr=0x90800000\0" | |
155 | ||
156 | /* | |
157 | * Miscellaneous configurable options | |
158 | */ | |
159 | #define CONFIG_SYS_LONGHELP | |
160 | #define CONFIG_SYS_PROMPT "Vision II U-boot > " | |
161 | #define CONFIG_AUTO_COMPLETE | |
162 | #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ | |
163 | ||
164 | /* Print Buffer Size */ | |
165 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ | |
166 | sizeof(CONFIG_SYS_PROMPT) + 16) | |
167 | #define CONFIG_SYS_MAXARGS 64 /* max number of command args */ | |
168 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE | |
169 | ||
170 | #define CONFIG_SYS_MEMTEST_START 0x90000000 | |
171 | #define CONFIG_SYS_MEMTEST_END 0x10000 | |
172 | ||
173 | #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR | |
174 | ||
175 | #define CONFIG_SYS_HZ 1000 | |
176 | #define CONFIG_CMDLINE_EDITING | |
177 | #define CONFIG_SYS_HUSH_PARSER | |
178 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "Vision II U-boot > " | |
179 | ||
180 | /* | |
181 | * Stack sizes | |
182 | */ | |
183 | #define CONFIG_STACKSIZE (128 * 1024) /* regular stack */ | |
184 | ||
185 | /* | |
186 | * Physical Memory Map | |
187 | */ | |
188 | #define CONFIG_NR_DRAM_BANKS 2 | |
189 | #define PHYS_SDRAM_1 CSD0_BASE_ADDR | |
190 | #define PHYS_SDRAM_1_SIZE (256 * 1024 * 1024) | |
191 | #define PHYS_SDRAM_2 CSD1_BASE_ADDR | |
192 | #define PHYS_SDRAM_2_SIZE (256 * 1024 * 1024) | |
43883dc3 SB |
193 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 |
194 | #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR | |
195 | #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE | |
196 | ||
197 | #define CONFIG_SYS_INIT_SP_OFFSET \ | |
198 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) | |
199 | #define CONFIG_SYS_INIT_SP_ADDR \ | |
200 | (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) | |
201 | ||
f8f8acd7 SB |
202 | #define CONFIG_BOARD_EARLY_INIT_F |
203 | ||
204 | /* 166 MHz DDR RAM */ | |
205 | #define CONFIG_SYS_DDR_CLKSEL 0 | |
206 | #define CONFIG_SYS_CLKTL_CBCDR 0x19239100 | |
207 | ||
208 | #define CONFIG_SYS_NO_FLASH | |
209 | ||
a0152c4b SB |
210 | /* |
211 | * Framebuffer and LCD | |
212 | */ | |
213 | #define CONFIG_PREBOOT | |
e9934f0b | 214 | #define CONFIG_VIDEO |
a0152c4b | 215 | #define CONFIG_VIDEO_MX5 |
e9934f0b SB |
216 | #define CONFIG_CFB_CONSOLE |
217 | #define CONFIG_VGA_AS_SINGLE_DEVICE | |
218 | #define CONFIG_VIDEO_BMP_RLE8 | |
a0152c4b SB |
219 | #define CONFIG_SPLASH_SCREEN |
220 | #define CONFIG_CMD_BMP | |
221 | #define CONFIG_BMP_16BPP | |
222 | ||
f8f8acd7 | 223 | #endif /* __CONFIG_H */ |