| 4324c75f |
1 | /* |
| 2 | * (C) Copyright 2009-2012 |
| 3 | * Jens Scharsig <esw@bus-elekronik.de> |
| 4 | * BuS Elektronik GmbH & Co. KG |
| 5 | * |
| 6 | * Configuation settings for the VL_MA2SC board. |
| 7 | * |
| 1a459660 |
8 | * SPDX-License-Identifier: GPL-2.0+ |
| 4324c75f |
9 | */ |
| 10 | |
| 11 | #ifndef __CONFIG_H |
| 12 | #define __CONFIG_H |
| 13 | |
| 14 | /*--------------------------------------------------------------------------*/ |
| 15 | |
| 4324c75f |
16 | #define CONFIG_ARM926EJS /* This is an ARM926EJS Core */ |
| 17 | #define CONFIG_AT91FAMILY |
| 18 | #define CONFIG_AT91SAM9263 /* It's an Atmel AT91SAM9263 SoC*/ |
| 19 | #define CONFIG_VL_MA2SC /* on an VL_MA2SC Board */ |
| 20 | #define CONFIG_ARCH_CPU_INIT |
| 21 | #define CONFIG_MISC_INIT_R |
| 22 | |
| 23 | #include <asm/hardware.h> |
| 24 | |
| 25 | #define MACH_TYPE_VL_MA2SC 2412 |
| 26 | #define CONFIG_MACH_TYPE MACH_TYPE_VL_MA2SC |
| 27 | |
| 28 | #define CONFIG_SYS_DCACHE_OFF |
| 29 | |
| 30 | #ifdef CONFIG_RAMLOAD |
| 31 | #define CONFIG_SYS_TEXT_BASE 0x21000000 |
| 32 | #else |
| 33 | #define CONFIG_SYS_TEXT_BASE 0x00000000 |
| 34 | #endif |
| 35 | #define CONFIG_SYS_LOAD_ADDR 0x21000000 /* default load address */ |
| 36 | |
| 37 | #define CONFIG_IDENT_STRING " on MiS Activ 2" |
| 38 | #define CONFIG_VERSION_VARIABLE |
| 39 | #define CONFIG_AT91_GPIO |
| 40 | |
| 41 | #if !defined(CONFIG_SYS_USE_NANDFLASH) && !defined(CONFIG_RAMLOAD) |
| 42 | #define CONFIG_SYS_USE_NORFLASH |
| 43 | #define CONFIG_SYS_USE_BOOT_NORFLASH |
| 44 | #endif |
| 45 | |
| 46 | #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ |
| 47 | #define CONFIG_SETUP_MEMORY_TAGS |
| 48 | #define CONFIG_INITRD_TAG |
| 49 | |
| 50 | #ifndef CONFIG_SYS_USE_BOOT_NORFLASH |
| 51 | #define CONFIG_SKIP_LOWLEVEL_INIT |
| 52 | #endif |
| 53 | |
| 54 | /* |
| 55 | * Hardware drivers |
| 56 | */ |
| 57 | |
| 58 | #define CONFIG_BOARD_EARLY_INIT_F |
| 59 | |
| 60 | #define CONFIG_WATCHDOG |
| 61 | |
| 62 | #define CONFIG_ATMEL_USART |
| 63 | #define CONFIG_USART_BASE ATMEL_BASE_DBGU |
| 64 | #define CONFIG_USART_ID ATMEL_ID_SYS |
| 65 | |
| 66 | /* LCD */ |
| 67 | #define CONFIG_LCD |
| 68 | #define CONFIG_ATMEL_LCD |
| 69 | #define CONFIG_SPLASH_SCREEN |
| 70 | #define CONFIG_SYS_BLACK_ON_WHITE |
| 71 | #define LCD_BPP LCD_COLOR8 |
| 72 | #define CONFIG_ATMEL_LCD_BGR555 |
| 73 | |
| 74 | #define CONFIG_SYS_CONSOLE_IS_IN_ENV |
| 75 | #define CONFIG_BOOTDELAY 3 |
| 76 | |
| 77 | /* |
| 78 | * BOOTP options |
| 79 | */ |
| 80 | #define CONFIG_BOOTP_BOOTFILESIZE |
| 81 | #define CONFIG_BOOTP_BOOTPATH |
| 82 | #define CONFIG_BOOTP_GATEWAY |
| 83 | #define CONFIG_BOOTP_HOSTNAME |
| 84 | |
| 85 | /* |
| 86 | * Command line configuration. |
| 87 | */ |
| 88 | #include <config_cmd_default.h> |
| 89 | #undef CONFIG_CMD_BDI |
| 90 | #undef CONFIG_CMD_FPGA |
| 91 | #undef CONFIG_CMD_IMI |
| 92 | #undef CONFIG_CMD_LOADS |
| 93 | |
| 94 | #define CONFIG_CMD_BMP |
| 95 | #define CONFIG_CMD_DATE |
| 96 | #define CONFIG_CMD_DHCP |
| 97 | #define CONFIG_CMD_I2C |
| 98 | #define CONFIG_CMD_NAND |
| 99 | #define CONFIG_CMD_MII |
| 100 | #define CONFIG_CMD_PING |
| 101 | #define CONFIG_CMD_MD5SUM |
| 102 | #define CONFIG_CMD_SHA1SUM |
| 103 | /* |
| 104 | #define CONFIG_CMD_SPI |
| 105 | */ |
| 106 | #define CONFIG_CMD_FAT |
| 107 | #define CONFIG_CMD_USB |
| 108 | |
| 109 | #define CONFIG_SYS_LONGHELP |
| 110 | #define CONFIG_MD5 |
| 111 | #define CONFIG_SHA1 |
| 112 | |
| 113 | /*---------------------------------------------------------------------------- |
| 114 | * Hardware confuguration |
| 115 | *---------------------------------------------------------------------------*/ |
| 116 | |
| 117 | /* USB */ |
| 118 | #define CONFIG_USB_ATMEL |
| 119 | #define CONFIG_USB_OHCI_NEW |
| 120 | #define CONFIG_DOS_PARTITION |
| 121 | #define CONFIG_SYS_USB_OHCI_CPU_INIT |
| 122 | #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* UHP_BASE */ |
| 123 | #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9263" |
| 124 | #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 |
| 125 | #define CONFIG_USB_STORAGE |
| 126 | #define CONFIG_AT91C_PQFP_UHPBUG |
| 127 | |
| 128 | /* I2C-Bus */ |
| 129 | |
| 130 | #define CONFIG_SYS_I2C_SPEED 50000 |
| 131 | #define CONFIG_SYS_I2C_SLAVE 0 /* not used */ |
| 132 | |
| 133 | #ifndef CONFIG_HARD_I2C |
| 134 | #define CONFIG_SOFT_I2C |
| 135 | |
| 136 | /* Software I2C driver configuration */ |
| 137 | |
| 138 | #define I2C_DELAY udelay(2500000/CONFIG_SYS_I2C_SPEED) |
| 139 | |
| 140 | #define AT91_PIN_SDA (1<<4) /* AT91C_PIO_PB4 */ |
| 141 | #define AT91_PIN_SCL (1<<5) /* AT91C_PIO_PB5 */ |
| 142 | |
| 143 | #define I2C_INIT i2c_init_board(); |
| 144 | #define I2C_ACTIVE writel(AT91_PIN_SDA, &pio->piob.mddr); |
| 145 | #define I2C_TRISTATE writel(AT91_PIN_SDA, &pio->piob.mder); |
| 146 | #define I2C_READ ((readl(&pio->piob.pdsr) & AT91_PIN_SDA) != 0) |
| 147 | #define I2C_SDA(bit) \ |
| 148 | do { \ |
| 149 | if (bit) \ |
| 150 | writel(AT91_PIN_SDA, &pio->piob.sodr); \ |
| 151 | else \ |
| 152 | writel(AT91_PIN_SDA, &pio->piob.codr); \ |
| 153 | } while (0); |
| 154 | #define I2C_SCL(bit) \ |
| 155 | do { \ |
| 156 | if (bit) \ |
| 157 | writel(AT91_PIN_SCL, &pio->piob.sodr); \ |
| 158 | else \ |
| 159 | writel(AT91_PIN_SCL, &pio->piob.codr); \ |
| 160 | } while (0); |
| 161 | #endif |
| 162 | |
| 163 | /* I2C-RTC */ |
| 164 | |
| 165 | #ifdef CONFIG_CMD_DATE |
| 166 | #define CONFIG_RTC_DS1338 |
| 167 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 |
| 168 | #endif |
| 169 | |
| 170 | /* EEPROM */ |
| 171 | |
| 172 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 |
| 173 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 |
| 174 | |
| 175 | /* define PDC[31:16] as DATA[31:16] */ |
| 176 | #define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000 |
| 177 | #define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000 |
| 178 | |
| 179 | /* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */ |
| 180 | #define CONFIG_SYS_MATRIX_EBI0CSA_VAL \ |
| 181 | (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_VDDIOMSEL_3_3V | \ |
| 182 | AT91_MATRIX_CSA_EBI_CS1A) |
| 183 | |
| 184 | /* user reset enable */ |
| 185 | #define CONFIG_SYS_RSTC_RMR_VAL \ |
| 186 | (AT91_RSTC_KEY | \ |
| 187 | AT91_RSTC_MR_URSTEN | \ |
| 188 | AT91_RSTC_MR_ERSTL(15)) |
| 189 | |
| 190 | /* Disable Watchdog */ |
| 191 | #define CONFIG_SYS_WDTC_WDMR_VAL \ |
| 192 | (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \ |
| 193 | AT91_WDT_MR_WDV(0xFFF) | \ |
| 194 | AT91_WDT_MR_WDDIS | \ |
| 195 | AT91_WDT_MR_WDD(0xFFF)) |
| 196 | |
| 197 | /* clocks */ |
| 198 | |
| 199 | #define CONFIG_SYS_HZ 1000 |
| 200 | #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock */ |
| 201 | |
| 202 | #define MHZ180 |
| 203 | #if defined(MHZ199) |
| 204 | /* 199,8994 MHZ */ |
| 205 | #define MASTER_PLL_MUL 911 |
| 206 | #define MASTER_PLL_DIV 56 |
| 207 | #define MASTER_PLL_OUT 2 |
| 208 | #elif defined(MHZ180) |
| 209 | /* 180 MHZ */ |
| 210 | #define MASTER_PLL_MUL 1875 |
| 211 | #define MASTER_PLL_DIV 128 |
| 212 | #define MASTER_PLL_OUT 2 |
| 213 | #elif defined(MHZTEST) |
| 214 | /* Test MHZ */ |
| 215 | #define CONFIG_DISPLAY_CPUINFO |
| 216 | #define MASTER_PLL_MUL 8 |
| 217 | #define MASTER_PLL_DIV 1 |
| 218 | #define MASTER_PLL_OUT 2 |
| 219 | #else |
| 220 | /* 176.9472 MHZ */ |
| 221 | #define MASTER_PLL_MUL 72 |
| 222 | #define MASTER_PLL_DIV 5 |
| 223 | #define MASTER_PLL_OUT 2 |
| 224 | #endif |
| 225 | |
| 226 | #define CONFIG_SYS_MOR_VAL \ |
| 227 | (AT91_PMC_MOR_MOSCEN | AT91_PMC_MOR_OSCOUNT(255)) |
| 228 | |
| 229 | #define CONFIG_SYS_PLLAR_VAL \ |
| 230 | (AT91_PMC_PLLAR_29 | \ |
| 231 | AT91_PMC_PLLXR_OUT(MASTER_PLL_OUT) | \ |
| 232 | AT91_PMC_PLLXR_PLLCOUNT(63) | \ |
| 233 | AT91_PMC_PLLXR_MUL(MASTER_PLL_MUL - 1) | \ |
| 234 | AT91_PMC_PLLXR_DIV(MASTER_PLL_DIV)) |
| 235 | |
| 236 | /* PCK/2 = MCK Master Clock from PLLA */ |
| 237 | #define CONFIG_SYS_MCKR1_VAL \ |
| 238 | (AT91_PMC_MCKR_CSS_SLOW | AT91_PMC_MCKR_PRES_1 | \ |
| 239 | AT91_PMC_MCKR_MDIV_2) |
| 240 | |
| 241 | /* PCK/2 = MCK Master Clock from PLLA */ |
| 242 | #define CONFIG_SYS_MCKR2_VAL \ |
| 243 | (AT91_PMC_MCKR_CSS_PLLA | AT91_PMC_MCKR_PRES_1 | \ |
| 244 | AT91_PMC_MCKR_MDIV_2) |
| 245 | |
| 246 | /* SDRAM */ |
| 247 | #define CONFIG_NR_DRAM_BANKS 1 |
| 248 | #define CONFIG_SYS_SDRAM_BASE 0x20000000 |
| 249 | #define CONFIG_SYS_SDRAM_SIZE 0x04000000 /* 64 megs */ |
| 250 | #define CONFIG_SYS_INIT_SP_ADDR 0x00504000 /* use internal SRAM0 */ |
| 251 | |
| 252 | #define CONFIG_SYS_SDRC_MR_VAL1 0 |
| 253 | #define CONFIG_SYS_SDRC_TR_VAL1 700 |
| 254 | #define CONFIG_SYS_SDRC_CR_VAL \ |
| 255 | (AT91_SDRAMC_NC_9 | \ |
| 256 | AT91_SDRAMC_NR_13 | \ |
| 257 | AT91_SDRAMC_NB_4 | \ |
| 258 | AT91_SDRAMC_CAS_3 | \ |
| 259 | AT91_SDRAMC_DBW_32 | \ |
| 260 | (2 << 8) | /* Write Recovery Delay */ \ |
| 261 | (7 << 12) | /* Row Cycle Delay */ \ |
| 262 | (2 << 16) | /* Row Precharge Delay */ \ |
| 263 | (2 << 20) | /* Row to Column Delay */ \ |
| 264 | (5 << 24) | /* Active to Precharge Delay */ \ |
| 265 | (8 << 28)) /* Exit Self Refresh to Active Delay */ |
| 266 | |
| 267 | #define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM |
| 268 | #define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE |
| 269 | #define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */ |
| 270 | #define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH |
| 271 | #define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */ |
| 272 | #define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */ |
| 273 | #define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */ |
| 274 | #define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */ |
| 275 | #define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */ |
| 276 | #define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */ |
| 277 | #define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */ |
| 278 | #define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */ |
| 279 | #define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR |
| 280 | #define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */ |
| 281 | #define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL |
| 282 | #define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */ |
| 283 | #define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */ |
| 284 | #define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */ |
| 285 | |
| 286 | /* NOR flash */ |
| 287 | |
| 288 | #define CONFIG_FLASH_SHOW_PROGRESS 45 |
| 289 | #define CONFIG_SYS_FLASH_CFI |
| 290 | #define CONFIG_FLASH_CFI_DRIVER |
| 291 | #define PHYS_FLASH_1 0x10000000 |
| 292 | #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 |
| 293 | #define CONFIG_SYS_MAX_FLASH_SECT 256 |
| 294 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 |
| 295 | |
| 296 | #define CONFIG_ENV_IS_IN_FLASH |
| 297 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00060000) |
| 298 | |
| 299 | /* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */ |
| 300 | #define CONFIG_SYS_SMC0_SETUP0_VAL \ |
| 301 | (AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) | \ |
| 302 | AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10)) |
| 303 | #define CONFIG_SYS_SMC0_PULSE0_VAL \ |
| 304 | (AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) | \ |
| 305 | AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11)) |
| 306 | #define CONFIG_SYS_SMC0_CYCLE0_VAL \ |
| 307 | (AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22)) |
| 308 | #define CONFIG_SYS_SMC0_MODE0_VAL \ |
| 309 | (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \ |
| 310 | AT91_SMC_MODE_DBW_16 | \ |
| 311 | AT91_SMC_MODE_TDF | AT91_SMC_MODE_TDF_CYCLE(6)) |
| 312 | |
| 313 | /* NAND flash */ |
| 314 | #ifdef CONFIG_CMD_NAND |
| 315 | #define CONFIG_NAND_ATMEL |
| 316 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 |
| 317 | #define CONFIG_SYS_NAND_BASE 0x40000000 |
| 318 | #define CONFIG_SYS_NAND_DBW_8 1 |
| 319 | #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) /* our ALE is AD21 */ |
| 320 | #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) /* our CLE is AD22 */ |
| 321 | #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIO_PORTD, 15 |
| 322 | #define CONFIG_SYS_NAND_READY_PIN AT91_PIO_PORTB, 0 |
| 323 | #define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ |
| 324 | #endif |
| 325 | |
| 326 | /* Ethernet */ |
| 327 | #define CONFIG_MACB |
| 328 | #define CONFIG_RMII |
| 329 | #define CONFIG_NET_MULTI |
| 330 | #define CONFIG_NET_RETRY_COUNT 5 |
| 331 | |
| 332 | #define CONFIG_OVERWRITE_ETHADDR_ONCE |
| 333 | |
| 334 | #define CONFIG_SYS_LOAD_ADDR 0x21000000 /* default load address */ |
| 335 | |
| 336 | #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE |
| 337 | #define CONFIG_SYS_MEMTEST_END 0x21e00000 |
| 338 | |
| 339 | /* Address and size of Primary Environment Sector */ |
| 340 | #ifdef CONFIG_ENV_IS_IN_FLASH |
| 341 | #define CONFIG_ENV_SIZE 0x20000 |
| 342 | #else |
| 343 | #define CONFIG_ENV_SIZE 0x2000 |
| 344 | #endif |
| 345 | |
| 346 | #define CONFIG_BAUDRATE 115200 |
| 347 | #define CONFIG_SYS_BAUDRATE_TABLE {312500, 230400, 115200, 19200, \ |
| 348 | 38400, 57600, 9600 } |
| 349 | |
| 350 | #define CONFIG_SYS_PROMPT "U-Boot> " |
| 351 | #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ |
| 352 | #define CONFIG_SYS_MAXARGS 32 /* max number of command args */ |
| 353 | #define CONFIG_SYS_PBSIZE \ |
| 354 | (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
| 355 | #define CONFIG_CMDLINE_EDITING |
| 356 | #define CONFIG_AUTO_COMPLETE |
| 357 | |
| 358 | /* |
| 359 | * Size of malloc() pool |
| 360 | */ |
| 361 | #define CONFIG_SYS_MALLOC_LEN \ |
| 362 | ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000) |
| 363 | #define CONFIG_SYS_GBL_DATA_SIZE 128 /* 128 bytes for initial data */ |
| 364 | |
| 4324c75f |
365 | #ifndef CONFIG_RAMLOAD |
| 366 | #define CONFIG_BOOTCOMMAND "run nfsboot" |
| 367 | #endif |
| 368 | #define CONFIG_BOOT_RETRY_TIME -1 |
| 369 | #define CONFIG_BOOT_RETRY_MIN 15 |
| 370 | |
| 371 | #define CONFIG_NFSBOOTCOMMAND \ |
| 372 | "dhcp $(copy_addr) $(kernelname);" \ |
| 373 | "run bootargsdefaults;" \ |
| 374 | "set bootargs $(bootargs) boot=nfs " \ |
| 375 | ";echo $(bootargs)" \ |
| 376 | ";bootm" |
| 377 | |
| 378 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 379 | "ubootaddr=10000000\0" \ |
| 380 | "splashimage=10080000\0" \ |
| 381 | "kerneladdr=100A0000\0" \ |
| 382 | "kernelsize=00800000\0" \ |
| 383 | "minifsaddr=108A0000\0" \ |
| 384 | "minifssize=00060000\0" \ |
| 385 | "rootfsaddr=10900000\0" \ |
| 386 | "copy_addr=20200000\0" \ |
| 387 | "rootfssize=01700000\0" \ |
| 388 | "kernelname=uImage_vl_ma2sc\0" \ |
| 389 | "bootargsdefaults=set bootargs " \ |
| 390 | "console=ttyS0,115200 " \ |
| 391 | "video=atmel_lcdfb " \ |
| 392 | "mem=62M " \ |
| 393 | "panic=10 " \ |
| 394 | "boardrevison=\\\"${revision}\\\" " \ |
| 395 | "uboot=\\\"${ver}\\\" " \ |
| 396 | "\0" \ |
| 397 | "update_all=run update_kernel;run update_root;" \ |
| 398 | "run update_splash; run update_uboot\0" \ |
| 399 | "update_kernel=protect off $(kerneladdr) +$(kernelsize);" \ |
| 400 | "dhcp $(copy_addr) $(kernelname);" \ |
| 401 | "erase $(kerneladdr) +$(kernelsize);" \ |
| 402 | "cp.b $(fileaddr) $(kerneladdr) $(filesize);" \ |
| 403 | "protect on $(kerneladdr) +$(kernelsize)" \ |
| 404 | "\0" \ |
| 405 | "update_root=protect off $(rootfsaddr) +$(rootfssize);" \ |
| 406 | "dhcp $(copy_addr) vl_ma2sc.root;" \ |
| 407 | "erase $(rootfsaddr) +$(rootfssize);" \ |
| 408 | "cp.b $(fileaddr) $(rootfsaddr) $(filesize);" \ |
| 409 | "\0" \ |
| 410 | "update_splash=protect off $(splashimage) +20000;" \ |
| 411 | "dhcp $(copy_addr) splash_vl_ma2sc.bmp;" \ |
| 412 | "erase $(splashimage) +20000;" \ |
| 413 | "cp.b $(fileaddr) 10080000 $(filesize);" \ |
| 414 | "protect on $(splashimage) +20000\0" \ |
| 415 | "update_uboot=protect off 10000000 1005FFFF;" \ |
| 416 | "dhcp $(copy_addr) u-boot_vl_ma2sc;" \ |
| 417 | "erase 10000000 1005FFFF;" \ |
| 418 | "cp.b $(fileaddr) $(ubootaddr) $(filesize);" \ |
| 419 | "protect on 10000000 1005FFFF;reset\0" \ |
| 420 | "emergency=run bootargsdefaults;" \ |
| 421 | "set bootargs $(bootargs) root=initramfs boot=emergency " \ |
| 422 | ";bootm $(kerneladdr)\0" \ |
| 423 | "netemergency=run bootargsdefaults;" \ |
| 424 | "dhcp $(copy_addr) $(kernelname);" \ |
| 425 | "set bootargs $(bootargs) root=initramfs boot=emergency " \ |
| 426 | ";bootm $(copy_addr)\0" \ |
| 427 | "norboot=run bootargsdefaults;" \ |
| 428 | "set bootargs $(bootargs) root=initramfs boot=local quiet " \ |
| 429 | ";bootm $(kerneladdr)\0" \ |
| 430 | "nandboot=run bootargsdefaults;" \ |
| 431 | "set bootargs $(bootargs) root=initramfs boot=nand " \ |
| 432 | ";bootm $(kerneladdr)\0" \ |
| 433 | "setnorboot=set bootcmd 'run norboot'; set bootdelay 1;save\0" \ |
| 434 | "clearenv=protect off 10060000 1007FFFF;" \ |
| 435 | "erase 10060000 1007FFFF;reset\0" \ |
| 436 | " " |
| 437 | |
| 4324c75f |
438 | #endif |
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