[people/ms/u-boot.git] / include / configs / vme8349.h

/*
 * esd vme8349 U-Boot configuration file
 * Copyright (c) 2008, 2009 esd gmbh Hannover Germany
 *
 * (C) Copyright 2006
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * reinhard.arlt@esd-electronics.de
 * Based on the MPC8349EMDS config.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * vme8349 board configuration file.
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 */
#define CONFIG_E300		1	/* E300 Family */
#define CONFIG_MPC83xx		1	/* MPC83xx family */
#define CONFIG_MPC834x		1	/* MPC834x family */
#define CONFIG_MPC8349		1	/* MPC8349 specific */
#define CONFIG_VME8349		1	/* ESD VME8349 board specific */

#define CONFIG_PCI
/* Don't enable PCI2 on vme834x - it doesn't exist physically. */
#undef CONFIG_MPC83XX_PCI2		/* support for 2nd PCI controller */

#define PCI_66M
#ifdef PCI_66M
#define CONFIG_83XX_CLKIN	66000000	/* in Hz */
#else
#define CONFIG_83XX_CLKIN	33000000	/* in Hz */
#endif

#ifndef CONFIG_SYS_CLK_FREQ
#ifdef PCI_66M
#define CONFIG_SYS_CLK_FREQ	66000000
#define HRCWL_CSB_TO_CLKIN	HRCWL_CSB_TO_CLKIN_4X1
#else
#define CONFIG_SYS_CLK_FREQ	33000000
#define HRCWL_CSB_TO_CLKIN	HRCWL_CSB_TO_CLKIN_8X1
#endif
#endif

#define CONFIG_SYS_IMMR		0xE0000000

#undef CONFIG_SYS_DRAM_TEST			/* memory test, takes time */
#define CONFIG_SYS_MEMTEST_START	0x00000000	/* memtest region */
#define CONFIG_SYS_MEMTEST_END		0x00100000

/*
 * DDR Setup
 */
#define CONFIG_DDR_ECC			/* only for ECC DDR module */
#define CONFIG_DDR_ECC_CMD		/* use DDR ECC user commands */
#undef CONFIG_SPD_EEPROM		/* dont use SPD EEPROM for DDR setup*/
#define CONFIG_SYS_83XX_DDR_USES_CS0	/* esd; Fsl board uses CS2/CS3 */

/*
 * 32-bit data path mode.
 *
 * Please note that using this mode for devices with the real density of 64-bit
 * effectively reduces the amount of available memory due to the effect of
 * wrapping around while translating address to row/columns, for example in the
 * 256MB module the upper 128MB get aliased with contents of the lower
 * 128MB); normally this define should be used for devices with real 32-bit
 * data path.
 */
#undef CONFIG_DDR_32BIT

#define CONFIG_SYS_DDR_BASE		0x00000000	/* DDR is sys memory*/
#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
#define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE
#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	(DDR_SDRAM_CLK_CNTL_SS_EN | \
					 DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
#define CONFIG_DDR_2T_TIMING

/*
 * Manually set up DDR parameters
 */
#define CONFIG_SYS_DDR_SIZE		512	/* MB */

#if (CONFIG_SYS_DDR_SIZE == 512)
#define CONFIG_SYS_DDR_CONFIG		(CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | \
					 CSCONFIG_COL_BIT_10 | \
					 CSCONFIG_BANK_BIT_3)
#endif

/*
 * Manually set up DDR parameters
 */
#define CONFIG_SYS_DDR_TIMING_0	        0x00220802
#define CONFIG_SYS_DDR_TIMING_1	        0x39377322
#define CONFIG_SYS_DDR_TIMING_2	        0x2f9848ca	/* P9-45, tuning? */
#define CONFIG_SYS_DDR_TIMING_3	        0x00000000
#define CONFIG_SYS_DDR_CONTROL		0xc2000000	/* unbuf,no DYN_PWR */
#define CONFIG_SYS_DDR_MODE		0x07940242
#define CONFIG_SYS_DDR_MODE2		0x00000000
/* autocharge,no open page */
#define CONFIG_SYS_DDR_INTERVAL	        0x04060100
#define CONFIG_SYS_DDR_SDRAM_CFG	0x63000000
#define CONFIG_SYS_DDR_SDRAM_CFG2	0x04061000

/*
 * FLASH on the Local Bus
 */
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_FLASH_CFI_DRIVER			        /* use the CFI driver */
#define CONFIG_SYS_FLASH_BASE		0xf8000000	/* start of FLASH   */
#define CONFIG_SYS_FLASH_SIZE           128		/* flash size in MB */
/* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */

#define CONFIG_SYS_BR0_PRELIM		(CONFIG_SYS_FLASH_BASE | \
					 (2 << BR_PS_SHIFT) |	/*  32bit */ \
					 BR_V)			/* valid */

#define CONFIG_SYS_OR0_PRELIM		0xF8006FF7	/* 128 MB flash size */
#define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_LBLAWAR0_PRELIM	0x8000001A	/* 128 MB window size */

#define CONFIG_SYS_BR1_PRELIM		(0xf0000000 | 0x00001801)
#define CONFIG_SYS_OR1_PRELIM		(0xffff8000 | 0x00000200)
#define CONFIG_SYS_LBLAWBAR1_PRELIM	0xf0000000
#define CONFIG_SYS_LBLAWAR1_PRELIM	(0x80000000 | 0x0000000e)

#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT	1024	/* sectors per device*/

#undef CONFIG_SYS_FLASH_CHECKSUM
#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase TO (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write TO (ms) */

#define CONFIG_SYS_MONITOR_BASE	        TEXT_BASE	/* start of monitor */

#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#define CONFIG_SYS_RAMBOOT
#else
#undef  CONFIG_SYS_RAMBOOT
#endif

#define CONFIG_SYS_INIT_RAM_LOCK	1
#define CONFIG_SYS_INIT_RAM_ADDR	0xF7000000	/* Initial RAM addr */
#define CONFIG_SYS_INIT_RAM_END		0x1000		/* size */

#define CONFIG_SYS_GBL_DATA_SIZE	0x100		/* size init data */
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - \
					 CONFIG_SYS_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB */
#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)	/* Malloc size */

/*
 * Local Bus LCRR and LBCR regs
 *    LCRR:  DLL bypass, Clock divider is 4
 * External Local Bus rate is
 *    CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
 */
#define CONFIG_SYS_LCRR_DBYP	LCRR_DBYP
#define CONFIG_SYS_LCRR_CLKDIV	LCRR_CLKDIV_4
#define CONFIG_SYS_LBC_LBCR	0x00000000

#undef CONFIG_SYS_LB_SDRAM	/* if board has SDRAM on local bus */

/*
 * Serial Port
 */
#define CONFIG_CONS_INDEX	1
#undef CONFIG_SERIAL_SOFTWARE_FIFO
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)

#define CONFIG_SYS_BAUDRATE_TABLE  \
	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}

#define CONFIG_SYS_NS16550_COM1		(CONFIG_SYS_IMMR + 0x4500)
#define CONFIG_SYS_NS16550_COM2		(CONFIG_SYS_IMMR + 0x4600)

#define CONFIG_CMDLINE_EDITING		/* add command line history	*/
/* Use the HUSH parser */
#define CONFIG_SYS_HUSH_PARSER
#ifdef CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#endif

/* pass open firmware flat tree */
#define CONFIG_OF_LIBFDT
#define CONFIG_OF_BOARD_SETUP
#define CONFIG_OF_STDOUT_VIA_ALIAS

/* I2C */
#define CONFIG_I2C_MULTI_BUS
#define CONFIG_HARD_I2C		/* I2C with hardware support*/
#undef CONFIG_SOFT_I2C		/* I2C bit-banged */
#define CONFIG_FSL_I2C
#define CONFIG_I2C_CMD_TREE
#define CONFIG_SYS_I2C_SPEED	400000	/* I2C speed and slave address */
#define CONFIG_SYS_I2C_SLAVE	0x7F
#define CONFIG_SYS_I2C_NOPROBES	{{0, 0x69}} /* Don't probe these addrs */
#define CONFIG_SYS_I2C1_OFFSET	0x3000
#define CONFIG_SYS_I2C2_OFFSET	0x3100
#define CONFIG_SYS_I2C_OFFSET	CONFIG_SYS_I2C1_OFFSET
/* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SYS_SPD_BUS_NUM... */

#define CONFIG_SYS_I2C_8574_ADDR2       0x20    /* I2C1, PCF8574 */

/* TSEC */
#define CONFIG_SYS_TSEC1_OFFSET	0x24000
#define CONFIG_SYS_TSEC1	(CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
#define CONFIG_SYS_TSEC2_OFFSET 0x25000
#define CONFIG_SYS_TSEC2	(CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET)

/*
 * General PCI
 * Addresses are mapped 1-1.
 */
#define CONFIG_SYS_PCI1_MEM_BASE	0x80000000
#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
#define CONFIG_SYS_PCI1_MEM_SIZE	0x10000000	/* 256M */
#define CONFIG_SYS_PCI1_MMIO_BASE	0x90000000
#define CONFIG_SYS_PCI1_MMIO_PHYS	CONFIG_SYS_PCI1_MMIO_BASE
#define CONFIG_SYS_PCI1_MMIO_SIZE	0x10000000	/* 256M */
#define CONFIG_SYS_PCI1_IO_BASE		0x00000000
#define CONFIG_SYS_PCI1_IO_PHYS		0xE2000000
#define CONFIG_SYS_PCI1_IO_SIZE		0x00100000	/* 1M */

#define CONFIG_SYS_PCI2_MEM_BASE	0xA0000000
#define CONFIG_SYS_PCI2_MEM_PHYS	CONFIG_SYS_PCI2_MEM_BASE
#define CONFIG_SYS_PCI2_MEM_SIZE	0x10000000	/* 256M */
#define CONFIG_SYS_PCI2_MMIO_BASE	0xB0000000
#define CONFIG_SYS_PCI2_MMIO_PHYS	CONFIG_SYS_PCI2_MMIO_BASE
#define CONFIG_SYS_PCI2_MMIO_SIZE	0x10000000	/* 256M */
#define CONFIG_SYS_PCI2_IO_BASE		0x00000000
#define CONFIG_SYS_PCI2_IO_PHYS		0xE2100000
#define CONFIG_SYS_PCI2_IO_SIZE		0x00100000	/* 1M */

#if defined(CONFIG_PCI)

#define PCI_64BIT
#define PCI_ONE_PCI1
#if defined(PCI_64BIT)
#undef PCI_ALL_PCI1
#undef PCI_TWO_PCI1
#undef PCI_ONE_PCI1
#endif

#define CONFIG_PCI_PNP			/* do pci plug-and-play */
#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */

#define CONFIG_NET_MULTI

#undef CONFIG_EEPRO100
#undef CONFIG_TULIP

#if !defined(CONFIG_PCI_PNP)
	#define PCI_ENET0_IOADDR	0xFIXME
	#define PCI_ENET0_MEMADDR	0xFIXME
	#define PCI_IDSEL_NUMBER	0xFIXME
#endif

#endif	/* CONFIG_PCI */

/*
 * TSEC configuration
 */
#define CONFIG_TSEC_ENET		/* TSEC ethernet support */

#if defined(CONFIG_TSEC_ENET)
#ifndef CONFIG_NET_MULTI
#define CONFIG_NET_MULTI
#endif

#define CONFIG_GMII		       /* MII PHY management */
#define CONFIG_TSEC1
#define CONFIG_TSEC1_NAME	"TSEC0"
#define CONFIG_TSEC2
#define CONFIG_TSEC2_NAME	"TSEC1"
#define CONFIG_PHY_M88E1111
#define TSEC1_PHY_ADDR		0x08
#define TSEC2_PHY_ADDR		0x10
#define TSEC1_PHYIDX		0
#define TSEC2_PHYIDX		0
#define TSEC1_FLAGS		TSEC_GIGABIT
#define TSEC2_FLAGS		TSEC_GIGABIT

/* Options are: TSEC[0-1] */
#define CONFIG_ETHPRIME		"TSEC0"

#endif	/* CONFIG_TSEC_ENET */

/*
 * Environment
 */
#ifndef CONFIG_SYS_RAMBOOT
	#define CONFIG_ENV_IS_IN_FLASH
	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + 0xc0000)
	#define CONFIG_ENV_SECT_SIZE	0x20000	/* 128K(one sector) for env */
	#define CONFIG_ENV_SIZE		0x2000

/* Address and size of Redundant Environment Sector	*/
#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)

#else
	#define CONFIG_SYS_NO_FLASH		/* Flash is not usable now */
	#define CONFIG_ENV_IS_NOWHERE		/* Store ENV in memory only */
	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
	#define CONFIG_ENV_SIZE		0x2000
#endif

#define CONFIG_LOADS_ECHO		/* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change */

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME

/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_I2C
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
#define CONFIG_CMD_DATE
#define CONFIG_SYS_RTC_BUS_NUM  0x01
#define CONFIG_SYS_I2C_RTC_ADDR	0x32
#define CONFIG_RTC_RX8025
#define CONFIG_CMD_TSI148

#if defined(CONFIG_PCI)
    #define CONFIG_CMD_PCI
#endif

#if defined(CONFIG_SYS_RAMBOOT)
    #undef CONFIG_CMD_ENV
    #undef CONFIG_CMD_LOADS
#endif

#define CONFIG_CMD_ELF
/* Pass Ethernet MAC to VxWorks */
#define CONFIG_SYS_VXWORKS_MAC_PTR	0x000043f0

#undef CONFIG_WATCHDOG			/* watchdog disabled */

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP			/* undef to save memory */
#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */

#if defined(CONFIG_CMD_KGDB)
	#define CONFIG_SYS_CBSIZE	1024	/* Console I/O Buffer Size */
#else
	#define CONFIG_SYS_CBSIZE	256	/* Console I/O Buffer Size */
#endif

#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS	16		/* max num of command args */
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE /* Boot Argument Buf Size */
#define CONFIG_SYS_HZ		1000		/* decr freq: 1ms ticks */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ	(8 << 20)	/* Init Memory map for Linux*/

#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST  */

#define CONFIG_SYS_HRCW_LOW (\
	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
	HRCWL_DDR_TO_SCB_CLK_1X1 |\
	HRCWL_CSB_TO_CLKIN |\
	HRCWL_VCO_1X2 |\
	HRCWL_CORE_TO_CSB_2X1)

#if defined(PCI_64BIT)
#define CONFIG_SYS_HRCW_HIGH (\
	HRCWH_PCI_HOST |\
	HRCWH_64_BIT_PCI |\
	HRCWH_PCI1_ARBITER_ENABLE |\
	HRCWH_PCI2_ARBITER_DISABLE |\
	HRCWH_CORE_ENABLE |\
	HRCWH_FROM_0X00000100 |\
	HRCWH_BOOTSEQ_DISABLE |\
	HRCWH_SW_WATCHDOG_DISABLE |\
	HRCWH_ROM_LOC_LOCAL_16BIT |\
	HRCWH_TSEC1M_IN_GMII |\
	HRCWH_TSEC2M_IN_GMII)
#else
#define CONFIG_SYS_HRCW_HIGH (\
	HRCWH_PCI_HOST |\
	HRCWH_32_BIT_PCI |\
	HRCWH_PCI1_ARBITER_ENABLE |\
	HRCWH_PCI2_ARBITER_ENABLE |\
	HRCWH_CORE_ENABLE |\
	HRCWH_FROM_0X00000100 |\
	HRCWH_BOOTSEQ_DISABLE |\
	HRCWH_SW_WATCHDOG_DISABLE |\
	HRCWH_ROM_LOC_LOCAL_16BIT |\
	HRCWH_TSEC1M_IN_GMII |\
	HRCWH_TSEC2M_IN_GMII)
#endif

/* System IO Config */
#define CONFIG_SYS_SICRH 0
#define CONFIG_SYS_SICRL SICRL_LDP_A

#define CONFIG_SYS_HID0_INIT	0x000000000
#define CONFIG_SYS_HID0_FINAL	HID0_ENABLE_MACHINE_CHECK

#define CONFIG_SYS_HID2		HID2_HBE

#define CONFIG_SYS_GPIO1_PRELIM
#define CONFIG_SYS_GPIO1_DIR	0x00100000
#define CONFIG_SYS_GPIO1_DAT	0x00100000

#define CONFIG_SYS_GPIO2_PRELIM
#define CONFIG_SYS_GPIO2_DIR	0x78900000
#define CONFIG_SYS_GPIO2_DAT	0x70100000

#define CONFIG_HIGH_BATS		/* High BATs supported */

/* DDR @ 0x00000000 */
#define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | \
				 BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \
				 BATU_VS | BATU_VP)

/* PCI @ 0x80000000 */
#ifdef CONFIG_PCI
#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10 | \
				 BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT1U	(CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | \
				 BATU_VS | BATU_VP)
#define CONFIG_SYS_IBAT2L	(CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | \
				 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT2U	(CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | \
				 BATU_VS | BATU_VP)
#else
#define CONFIG_SYS_IBAT1L	(0)
#define CONFIG_SYS_IBAT1U	(0)
#define CONFIG_SYS_IBAT2L	(0)
#define CONFIG_SYS_IBAT2U	(0)
#endif

#ifdef CONFIG_MPC83XX_PCI2
#define CONFIG_SYS_IBAT3L	(CONFIG_SYS_PCI2_MEM_BASE | BATL_PP_10 | \
				 BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT3U	(CONFIG_SYS_PCI2_MEM_BASE | BATU_BL_256M | \
				 BATU_VS | BATU_VP)
#define CONFIG_SYS_IBAT4L	(CONFIG_SYS_PCI2_MMIO_BASE | BATL_PP_10 | \
				 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT4U	(CONFIG_SYS_PCI2_MMIO_BASE | BATU_BL_256M | \
				 BATU_VS | BATU_VP)
#else
#define CONFIG_SYS_IBAT3L	(0)
#define CONFIG_SYS_IBAT3U	(0)
#define CONFIG_SYS_IBAT4L	(0)
#define CONFIG_SYS_IBAT4U	(0)
#endif

/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */
#define CONFIG_SYS_IBAT5L	(CONFIG_SYS_IMMR | BATL_PP_10 | \
				 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT5U	(CONFIG_SYS_IMMR | BATU_BL_256M | \
				 BATU_VS | BATU_VP)

#define CONFIG_SYS_IBAT6L	(0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT6U	(0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)

#if (CONFIG_SYS_DDR_SIZE == 512)
#define CONFIG_SYS_IBAT7L	(CONFIG_SYS_SDRAM_BASE+0x10000000 | \
				 BATL_PP_10 | BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT7U	(CONFIG_SYS_SDRAM_BASE+0x10000000 | \
				 BATU_BL_256M | BATU_VS | BATU_VP)
#else
#define CONFIG_SYS_IBAT7L	(0)
#define CONFIG_SYS_IBAT7U	(0)
#endif

#define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
#define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
#define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
#define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
#define CONFIG_SYS_DBAT2L	CONFIG_SYS_IBAT2L
#define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
#define CONFIG_SYS_DBAT3L	CONFIG_SYS_IBAT3L
#define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
#define CONFIG_SYS_DBAT4L	CONFIG_SYS_IBAT4L
#define CONFIG_SYS_DBAT4U	CONFIG_SYS_IBAT4U
#define CONFIG_SYS_DBAT5L	CONFIG_SYS_IBAT5L
#define CONFIG_SYS_DBAT5U	CONFIG_SYS_IBAT5U
#define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
#define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
#define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
#define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U

/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define BOOTFLAG_COLD	0x01	/* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM	0x02	/* Software reboot */

#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
#endif

/*
 * Environment Configuration
 */
#define CONFIG_ENV_OVERWRITE

#if defined(CONFIG_TSEC_ENET)
#define CONFIG_HAS_ETH0
#define CONFIG_HAS_ETH1
#endif

#define CONFIG_HOSTNAME		VME8349
#define CONFIG_ROOTPATH		/tftpboot/rootfs
#define CONFIG_BOOTFILE		uImage

#define CONFIG_LOADADDR		800000	/* def location for tftp and bootm */

#define CONFIG_BOOTDELAY	6	/* -1 disables auto-boot */
#undef  CONFIG_BOOTARGS			/* boot command will set bootargs */

#define CONFIG_BAUDRATE	 115200

#define	CONFIG_EXTRA_ENV_SETTINGS					\
	"netdev=eth0\0"							\
	"hostname=vme8349\0"						\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=${serverip}:${rootpath}\0"			\
	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
	"addip=setenv bootargs ${bootargs} "				\
		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
		":${hostname}:${netdev}:off panic=1\0"			\
	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
	"flash_nfs=run nfsargs addip addtty;"				\
		"bootm ${kernel_addr}\0"				\
	"flash_self=run ramargs addip addtty;"				\
		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"	\
		"bootm\0"						\
	"load=tftp 100000 /tftpboot/bdi2000/vme8349.bin\0"		\
	"update=protect off fff00000 fff3ffff; "			\
		"era fff00000 fff3ffff; cp.b 100000 fff00000 ${filesize}\0" \
	"upd=run load update\0"						\
	"fdtaddr=780000\0"						\
	"fdtfile=vme8349.dtb\0"						\
	""

#define CONFIG_NFSBOOTCOMMAND	                                        \
   "setenv bootargs root=/dev/nfs rw "                                  \
      "nfsroot=$serverip:$rootpath "                                    \
      "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
      "console=$consoledev,$baudrate $othbootargs;"                     \
   "tftp $loadaddr $bootfile;"                                          \
   "tftp $fdtaddr $fdtfile;"						\
   "bootm $loadaddr - $fdtaddr"

#define CONFIG_RAMBOOTCOMMAND						\
   "setenv bootargs root=/dev/ram rw "                                  \
      "console=$consoledev,$baudrate $othbootargs;"                     \
   "tftp $ramdiskaddr $ramdiskfile;"                                    \
   "tftp $loadaddr $bootfile;"                                          \
   "tftp $fdtaddr $fdtfile;"						\
   "bootm $loadaddr $ramdiskaddr $fdtaddr"

#define CONFIG_BOOTCOMMAND	"run flash_self"

#endif	/* __CONFIG_H */
Commit	Line	Data
c2e49f70 RA	1	/*
	2	* esd vme8349 U-Boot configuration file
	3	* Copyright (c) 2008, 2009 esd gmbh Hannover Germany
	4	*
	5	* (C) Copyright 2006
	6	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	7	*
	8	* reinhard.arlt@esd-electronics.de
	9	* Based on the MPC8349EMDS config.
	10	*
	11	* See file CREDITS for list of people who contributed to this
	12	* project.
	13	*
	14	* This program is free software; you can redistribute it and/or
	15	* modify it under the terms of the GNU General Public License as
	16	* published by the Free Software Foundation; either version 2 of
	17	* the License, or (at your option) any later version.
	18	*
	19	* This program is distributed in the hope that it will be useful,
	20	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	21	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	22	* GNU General Public License for more details.
	23	*
	24	* You should have received a copy of the GNU General Public License
	25	* along with this program; if not, write to the Free Software
	26	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	27	* MA 02111-1307 USA
	28	*/
	29
	30	/*
	31	* vme8349 board configuration file.
	32	*/
	33
	34	#ifndef __CONFIG_H
	35	#define __CONFIG_H
	36
	37	/*
	38	* High Level Configuration Options
	39	*/
	40	#define CONFIG_E300 1 /* E300 Family */
	41	#define CONFIG_MPC83xx 1 /* MPC83xx family */
	42	#define CONFIG_MPC834x 1 /* MPC834x family */
	43	#define CONFIG_MPC8349 1 /* MPC8349 specific */
	44	#define CONFIG_VME8349 1 /* ESD VME8349 board specific */
	45
	46	#define CONFIG_PCI
	47	/* Don't enable PCI2 on vme834x - it doesn't exist physically. */
	48	#undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */
	49
	50	#define PCI_66M
	51	#ifdef PCI_66M
	52	#define CONFIG_83XX_CLKIN 66000000 /* in Hz */
	53	#else
	54	#define CONFIG_83XX_CLKIN 33000000 /* in Hz */
	55	#endif
	56
	57	#ifndef CONFIG_SYS_CLK_FREQ
	58	#ifdef PCI_66M
	59	#define CONFIG_SYS_CLK_FREQ 66000000
	60	#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1
	61	#else
	62	#define CONFIG_SYS_CLK_FREQ 33000000
	63	#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1
	64	#endif
65	#endif
66
67	#define CONFIG_SYS_IMMR 0xE0000000
68
69	#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
70	#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
71	#define CONFIG_SYS_MEMTEST_END 0x00100000
72
73	/*
74	* DDR Setup
75	*/
76	#define CONFIG_DDR_ECC /* only for ECC DDR module */
77	#define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */
78	#undef CONFIG_SPD_EEPROM /* dont use SPD EEPROM for DDR setup*/
79	#define CONFIG_SYS_83XX_DDR_USES_CS0 /* esd; Fsl board uses CS2/CS3 */
80
81	/*
82	* 32-bit data path mode.
83	*
84	* Please note that using this mode for devices with the real density of 64-bit
85	* effectively reduces the amount of available memory due to the effect of
86	* wrapping around while translating address to row/columns, for example in the
87	* 256MB module the upper 128MB get aliased with contents of the lower
88	* 128MB); normally this define should be used for devices with real 32-bit
89	* data path.
90	*/
91	#undef CONFIG_DDR_32BIT
92
93	#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is sys memory*/
94	#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
95	#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
96	#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \| \
97	DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
98	#define CONFIG_DDR_2T_TIMING
99
100	/*
101	* Manually set up DDR parameters
102	*/
103	#define CONFIG_SYS_DDR_SIZE 512 /* MB */
104
105	#if (CONFIG_SYS_DDR_SIZE == 512)
106	#define CONFIG_SYS_DDR_CONFIG (CSCONFIG_EN \| CSCONFIG_ROW_BIT_13 \| \
107	CSCONFIG_COL_BIT_10 \| \
108	CSCONFIG_BANK_BIT_3)
109	#endif
110
111	/*
112	* Manually set up DDR parameters
113	*/
114	#define CONFIG_SYS_DDR_TIMING_0 0x00220802
115	#define CONFIG_SYS_DDR_TIMING_1 0x39377322
116	#define CONFIG_SYS_DDR_TIMING_2 0x2f9848ca /* P9-45, tuning? */
117	#define CONFIG_SYS_DDR_TIMING_3 0x00000000
118	#define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuf,no DYN_PWR */
119	#define CONFIG_SYS_DDR_MODE 0x07940242
120	#define CONFIG_SYS_DDR_MODE2 0x00000000
121	/* autocharge,no open page */
122	#define CONFIG_SYS_DDR_INTERVAL 0x04060100
123	#define CONFIG_SYS_DDR_SDRAM_CFG 0x63000000
124	#define CONFIG_SYS_DDR_SDRAM_CFG2 0x04061000
125
126	/*
127	* FLASH on the Local Bus
128	*/
129	#define CONFIG_SYS_FLASH_CFI
130	#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
131	#define CONFIG_SYS_FLASH_BASE 0xf8000000 /* start of FLASH */
132	#define CONFIG_SYS_FLASH_SIZE 128 /* flash size in MB */
133	/* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
134
135	#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \| \
136	(2 << BR_PS_SHIFT) \| /* 32bit */ \
137	BR_V) /* valid */
138
139	#define CONFIG_SYS_OR0_PRELIM 0xF8006FF7 /* 128 MB flash size */
140	#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
141	#define CONFIG_SYS_LBLAWAR0_PRELIM 0x8000001A /* 128 MB window size */
142
143	#define CONFIG_SYS_BR1_PRELIM (0xf0000000 \| 0x00001801)
144	#define CONFIG_SYS_OR1_PRELIM (0xffff8000 \| 0x00000200)
145	#define CONFIG_SYS_LBLAWBAR1_PRELIM 0xf0000000
146	#define CONFIG_SYS_LBLAWAR1_PRELIM (0x80000000 \| 0x0000000e)
147
148	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
149	#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device*/
150
151	#undef CONFIG_SYS_FLASH_CHECKSUM
152	#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase TO (ms) */
153	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write TO (ms) */
154
c2e49f70 RA	155	#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
	156
	157	#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
	158	#define CONFIG_SYS_RAMBOOT
	159	#else
	160	#undef CONFIG_SYS_RAMBOOT
	161	#endif
	162
	163	#define CONFIG_SYS_INIT_RAM_LOCK 1
	164	#define CONFIG_SYS_INIT_RAM_ADDR 0xF7000000 /* Initial RAM addr */
	165	#define CONFIG_SYS_INIT_RAM_END 0x1000 /* size */
	166
	167	#define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* size init data */
	168	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \
	169	CONFIG_SYS_GBL_DATA_SIZE)
	170	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
	171
	172	#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB */
	173	#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Malloc size */
	174
	175	/*
	176	* Local Bus LCRR and LBCR regs
	177	* LCRR: DLL bypass, Clock divider is 4
	178	* External Local Bus rate is
	179	* CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
	180	*/
c7190f02 KP	181	#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
c7190f02 KP	182	#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
c2e49f70 RA	183	#define CONFIG_SYS_LBC_LBCR 0x00000000
	184
	185	#undef CONFIG_SYS_LB_SDRAM /* if board has SDRAM on local bus */
	186
	187	/*
	188	* Serial Port
	189	*/
	190	#define CONFIG_CONS_INDEX 1
	191	#undef CONFIG_SERIAL_SOFTWARE_FIFO
	192	#define CONFIG_SYS_NS16550
	193	#define CONFIG_SYS_NS16550_SERIAL
	194	#define CONFIG_SYS_NS16550_REG_SIZE 1
	195	#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
	196
	197	#define CONFIG_SYS_BAUDRATE_TABLE \
	198	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
	199
	200	#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
	201	#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
	202
	203	#define CONFIG_CMDLINE_EDITING /* add command line history */
	204	/* Use the HUSH parser */
	205	#define CONFIG_SYS_HUSH_PARSER
	206	#ifdef CONFIG_SYS_HUSH_PARSER
	207	#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
	208	#endif
	209
	210	/* pass open firmware flat tree */
	211	#define CONFIG_OF_LIBFDT
	212	#define CONFIG_OF_BOARD_SETUP
	213	#define CONFIG_OF_STDOUT_VIA_ALIAS
	214
	215	/* I2C */
	216	#define CONFIG_I2C_MULTI_BUS
	217	#define CONFIG_HARD_I2C /* I2C with hardware support*/
	218	#undef CONFIG_SOFT_I2C /* I2C bit-banged */
	219	#define CONFIG_FSL_I2C
	220	#define CONFIG_I2C_CMD_TREE
	221	#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
	222	#define CONFIG_SYS_I2C_SLAVE 0x7F
	223	#define CONFIG_SYS_I2C_NOPROBES {{0, 0x69}} /* Don't probe these addrs */
	224	#define CONFIG_SYS_I2C1_OFFSET 0x3000
	225	#define CONFIG_SYS_I2C2_OFFSET 0x3100
	226	#define CONFIG_SYS_I2C_OFFSET CONFIG_SYS_I2C1_OFFSET
efaf6f1b	227	/* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SYS_SPD_BUS_NUM... */
c2e49f70 RA	228
	229	#define CONFIG_SYS_I2C_8574_ADDR2 0x20 /* I2C1, PCF8574 */
	230
	231	/* TSEC */
	232	#define CONFIG_SYS_TSEC1_OFFSET 0x24000
	233	#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
	234	#define CONFIG_SYS_TSEC2_OFFSET 0x25000
	235	#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET)
	236
	237	/*
	238	* General PCI
	239	* Addresses are mapped 1-1.
	240	*/
	241	#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
	242	#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
	243	#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
	244	#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
	245	#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
	246	#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
	247	#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
	248	#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
	249	#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
	250
	251	#define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000
	252	#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
	253	#define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */
	254	#define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000
	255	#define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE
	256	#define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */
	257	#define CONFIG_SYS_PCI2_IO_BASE 0x00000000
	258	#define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000
	259	#define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */
	260
	261	#if defined(CONFIG_PCI)
	262
	263	#define PCI_64BIT
	264	#define PCI_ONE_PCI1
	265	#if defined(PCI_64BIT)
	266	#undef PCI_ALL_PCI1
	267	#undef PCI_TWO_PCI1
	268	#undef PCI_ONE_PCI1
	269	#endif
	270
	271	#define CONFIG_PCI_PNP /* do pci plug-and-play */
	272	#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
	273
	274	#define CONFIG_NET_MULTI
	275
	276	#undef CONFIG_EEPRO100
	277	#undef CONFIG_TULIP
	278
	279	#if !defined(CONFIG_PCI_PNP)
	280	#define PCI_ENET0_IOADDR 0xFIXME
	281	#define PCI_ENET0_MEMADDR 0xFIXME
	282	#define PCI_IDSEL_NUMBER 0xFIXME
	283	#endif
	284
	285	#endif /* CONFIG_PCI */
	286
	287	/*
	288	* TSEC configuration
	289	*/
	290	#define CONFIG_TSEC_ENET /* TSEC ethernet support */
	291
292	#if defined(CONFIG_TSEC_ENET)
293	#ifndef CONFIG_NET_MULTI
294	#define CONFIG_NET_MULTI
295	#endif
296
297	#define CONFIG_GMII /* MII PHY management */
298	#define CONFIG_TSEC1
299	#define CONFIG_TSEC1_NAME "TSEC0"
300	#define CONFIG_TSEC2
301	#define CONFIG_TSEC2_NAME "TSEC1"
302	#define CONFIG_PHY_M88E1111
303	#define TSEC1_PHY_ADDR 0x08
304	#define TSEC2_PHY_ADDR 0x10
305	#define TSEC1_PHYIDX 0
306	#define TSEC2_PHYIDX 0
307	#define TSEC1_FLAGS TSEC_GIGABIT
308	#define TSEC2_FLAGS TSEC_GIGABIT
309
310	/* Options are: TSEC[0-1] */
311	#define CONFIG_ETHPRIME "TSEC0"
312
313	#endif /* CONFIG_TSEC_ENET */
314
315	/*
316	* Environment
317	*/
318	#ifndef CONFIG_SYS_RAMBOOT
319	#define CONFIG_ENV_IS_IN_FLASH
320	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0xc0000)
321	#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
322	#define CONFIG_ENV_SIZE 0x2000
323
324	/* Address and size of Redundant Environment Sector */
325	#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
326	#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
327
328	#else
329	#define CONFIG_SYS_NO_FLASH /* Flash is not usable now */
330	#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
331	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
332	#define CONFIG_ENV_SIZE 0x2000
333	#endif
334
335	#define CONFIG_LOADS_ECHO /* echo on for serial download */
336	#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
337
338	/*
339	* BOOTP options
340	*/
341	#define CONFIG_BOOTP_BOOTFILESIZE
342	#define CONFIG_BOOTP_BOOTPATH
343	#define CONFIG_BOOTP_GATEWAY
344	#define CONFIG_BOOTP_HOSTNAME
345
346	/*
347	* Command line configuration.
348	*/
349	#include <config_cmd_default.h>
350
351	#define CONFIG_CMD_I2C
352	#define CONFIG_CMD_MII
353	#define CONFIG_CMD_PING
354	#define CONFIG_CMD_DATE
355	#define CONFIG_SYS_RTC_BUS_NUM 0x01
356	#define CONFIG_SYS_I2C_RTC_ADDR 0x32
357	#define CONFIG_RTC_RX8025
358	#define CONFIG_CMD_TSI148
359
360	#if defined(CONFIG_PCI)
361	#define CONFIG_CMD_PCI
362	#endif
363
364	#if defined(CONFIG_SYS_RAMBOOT)
365	#undef CONFIG_CMD_ENV
366	#undef CONFIG_CMD_LOADS
367	#endif
368
369	#define CONFIG_CMD_ELF
370	/* Pass Ethernet MAC to VxWorks */
371	#define CONFIG_SYS_VXWORKS_MAC_PTR 0x000043f0
372
373	#undef CONFIG_WATCHDOG /* watchdog disabled */
374
375	/*
376	* Miscellaneous configurable options
377	*/
378	#define CONFIG_SYS_LONGHELP /* undef to save memory */
379	#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
380	#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
381
382	#if defined(CONFIG_CMD_KGDB)
383	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
384	#else
385	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
386	#endif
387
388	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
389	#define CONFIG_SYS_MAXARGS 16 /* max num of command args */
390	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buf Size */
391	#define CONFIG_SYS_HZ 1000 /* decr freq: 1ms ticks */
392
393	/*
394	* For booting Linux, the board info and command line data
395	* have to be in the first 8 MB of memory, since this is
396	* the maximum mapped by the Linux kernel during initialization.
397	*/
398	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Init Memory map for Linux*/
399
400	#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
401
402	#define CONFIG_SYS_HRCW_LOW (\
403	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 \|\
404	HRCWL_DDR_TO_SCB_CLK_1X1 \|\
405	HRCWL_CSB_TO_CLKIN \|\
406	HRCWL_VCO_1X2 \|\
407	HRCWL_CORE_TO_CSB_2X1)
408
409	#if defined(PCI_64BIT)
410	#define CONFIG_SYS_HRCW_HIGH (\
411	HRCWH_PCI_HOST \|\
412	HRCWH_64_BIT_PCI \|\
413	HRCWH_PCI1_ARBITER_ENABLE \|\
414	HRCWH_PCI2_ARBITER_DISABLE \|\
415	HRCWH_CORE_ENABLE \|\
416	HRCWH_FROM_0X00000100 \|\
417	HRCWH_BOOTSEQ_DISABLE \|\
418	HRCWH_SW_WATCHDOG_DISABLE \|\
419	HRCWH_ROM_LOC_LOCAL_16BIT \|\
420	HRCWH_TSEC1M_IN_GMII \|\
421	HRCWH_TSEC2M_IN_GMII)
422	#else
423	#define CONFIG_SYS_HRCW_HIGH (\
424	HRCWH_PCI_HOST \|\
425	HRCWH_32_BIT_PCI \|\
426	HRCWH_PCI1_ARBITER_ENABLE \|\
427	HRCWH_PCI2_ARBITER_ENABLE \|\
428	HRCWH_CORE_ENABLE \|\
429	HRCWH_FROM_0X00000100 \|\
430	HRCWH_BOOTSEQ_DISABLE \|\
431	HRCWH_SW_WATCHDOG_DISABLE \|\
432	HRCWH_ROM_LOC_LOCAL_16BIT \|\
433	HRCWH_TSEC1M_IN_GMII \|\
434	HRCWH_TSEC2M_IN_GMII)
435	#endif
436
437	/* System IO Config */
438	#define CONFIG_SYS_SICRH 0
439	#define CONFIG_SYS_SICRL SICRL_LDP_A
440
441	#define CONFIG_SYS_HID0_INIT 0x000000000
442	#define CONFIG_SYS_HID0_FINAL HID0_ENABLE_MACHINE_CHECK
443
444	#define CONFIG_SYS_HID2 HID2_HBE
445
446	#define CONFIG_SYS_GPIO1_PRELIM
447	#define CONFIG_SYS_GPIO1_DIR 0x00100000
448	#define CONFIG_SYS_GPIO1_DAT 0x00100000
449
450	#define CONFIG_SYS_GPIO2_PRELIM
451	#define CONFIG_SYS_GPIO2_DIR 0x78900000
452	#define CONFIG_SYS_GPIO2_DAT 0x70100000
453
454	#define CONFIG_HIGH_BATS /* High BATs supported */
455
456	/* DDR @ 0x00000000 */
457	#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \| BATL_PP_10 \| \
458	BATL_MEMCOHERENCE)
459	#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \| BATU_BL_256M \| \
460	BATU_VS \| BATU_VP)
461
462	/* PCI @ 0x80000000 */
463	#ifdef CONFIG_PCI
464	#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \| BATL_PP_10 \| \
465	BATL_MEMCOHERENCE)
466	#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \| BATU_BL_256M \| \
467	BATU_VS \| BATU_VP)
468	#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \| BATL_PP_10 \| \
469	BATL_CACHEINHIBIT \| BATL_GUARDEDSTORAGE)
470	#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \| BATU_BL_256M \| \
471	BATU_VS \| BATU_VP)
472	#else
473	#define CONFIG_SYS_IBAT1L (0)
474	#define CONFIG_SYS_IBAT1U (0)
475	#define CONFIG_SYS_IBAT2L (0)
476	#define CONFIG_SYS_IBAT2U (0)
477	#endif
478
479	#ifdef CONFIG_MPC83XX_PCI2
480	#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE \| BATL_PP_10 \| \
481	BATL_MEMCOHERENCE)
482	#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE \| BATU_BL_256M \| \
483	BATU_VS \| BATU_VP)
484	#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE \| BATL_PP_10 \| \
485	BATL_CACHEINHIBIT \| BATL_GUARDEDSTORAGE)
486	#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE \| BATU_BL_256M \| \
487	BATU_VS \| BATU_VP)
488	#else
489	#define CONFIG_SYS_IBAT3L (0)
490	#define CONFIG_SYS_IBAT3U (0)
491	#define CONFIG_SYS_IBAT4L (0)
492	#define CONFIG_SYS_IBAT4U (0)
493	#endif
494
495	/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */
496	#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \| BATL_PP_10 \| \
497	BATL_CACHEINHIBIT \| BATL_GUARDEDSTORAGE)
498	#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \| BATU_BL_256M \| \
499	BATU_VS \| BATU_VP)
500
501	#define CONFIG_SYS_IBAT6L (0xF0000000 \| BATL_PP_10 \| BATL_MEMCOHERENCE)
502	#define CONFIG_SYS_IBAT6U (0xF0000000 \| BATU_BL_256M \| BATU_VS \| BATU_VP)
503
504	#if (CONFIG_SYS_DDR_SIZE == 512)
505	#define CONFIG_SYS_IBAT7L (CONFIG_SYS_SDRAM_BASE+0x10000000 \| \
506	BATL_PP_10 \| BATL_MEMCOHERENCE)
507	#define CONFIG_SYS_IBAT7U (CONFIG_SYS_SDRAM_BASE+0x10000000 \| \
508	BATU_BL_256M \| BATU_VS \| BATU_VP)
509	#else
510	#define CONFIG_SYS_IBAT7L (0)
511	#define CONFIG_SYS_IBAT7U (0)
512	#endif
513
514	#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
515	#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
516	#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
517	#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
518	#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
519	#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
520	#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
521	#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
522	#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
523	#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
524	#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
525	#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
526	#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
527	#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
528	#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
529	#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
530
531	/*
532	* Internal Definitions
533	*
534	* Boot Flags
535	*/
536	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
537	#define BOOTFLAG_WARM 0x02 /* Software reboot */
538
539	#if defined(CONFIG_CMD_KGDB)
540	#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
541	#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
542	#endif
543
544	/*
545	* Environment Configuration
546	*/
547	#define CONFIG_ENV_OVERWRITE
548
549	#if defined(CONFIG_TSEC_ENET)
550	#define CONFIG_HAS_ETH0
551	#define CONFIG_HAS_ETH1
552	#endif
553
554	#define CONFIG_HOSTNAME VME8349
555	#define CONFIG_ROOTPATH /tftpboot/rootfs
556	#define CONFIG_BOOTFILE uImage
557
79f516bc	558	#define CONFIG_LOADADDR 800000 /* def location for tftp and bootm */
c2e49f70 RA	559
	560	#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
	561	#undef CONFIG_BOOTARGS /* boot command will set bootargs */
	562
	563	#define CONFIG_BAUDRATE 115200
	564
	565	#define CONFIG_EXTRA_ENV_SETTINGS \
	566	"netdev=eth0\0" \
	567	"hostname=vme8349\0" \
	568	"nfsargs=setenv bootargs root=/dev/nfs rw " \
	569	"nfsroot=${serverip}:${rootpath}\0" \
	570	"ramargs=setenv bootargs root=/dev/ram rw\0" \
	571	"addip=setenv bootargs ${bootargs} " \
	572	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
	573	":${hostname}:${netdev}:off panic=1\0" \
	574	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
	575	"flash_nfs=run nfsargs addip addtty;" \
	576	"bootm ${kernel_addr}\0" \
	577	"flash_self=run ramargs addip addtty;" \
	578	"bootm ${kernel_addr} ${ramdisk_addr}\0" \
	579	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
	580	"bootm\0" \
	581	"load=tftp 100000 /tftpboot/bdi2000/vme8349.bin\0" \
	582	"update=protect off fff00000 fff3ffff; " \
	583	"era fff00000 fff3ffff; cp.b 100000 fff00000 ${filesize}\0" \
	584	"upd=run load update\0" \
79f516bc	585	"fdtaddr=780000\0" \
c2e49f70 RA	586	"fdtfile=vme8349.dtb\0" \
	587	""
	588
	589	#define CONFIG_NFSBOOTCOMMAND \
	590	"setenv bootargs root=/dev/nfs rw " \
	591	"nfsroot=$serverip:$rootpath " \
	592	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
	593	"console=$consoledev,$baudrate $othbootargs;" \
	594	"tftp $loadaddr $bootfile;" \
	595	"tftp $fdtaddr $fdtfile;" \
	596	"bootm $loadaddr - $fdtaddr"
	597
	598	#define CONFIG_RAMBOOTCOMMAND \
	599	"setenv bootargs root=/dev/ram rw " \
	600	"console=$consoledev,$baudrate $othbootargs;" \
	601	"tftp $ramdiskaddr $ramdiskfile;" \
	602	"tftp $loadaddr $bootfile;" \
	603	"tftp $fdtaddr $fdtfile;" \
	604	"bootm $loadaddr $ramdiskaddr $fdtaddr"
	605
	606	#define CONFIG_BOOTCOMMAND "run flash_self"
	607
	608	#endif /* __CONFIG_H */