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0f8c9768 | 1 | /* |
8a316c9b SR |
2 | * (C) Copyright 2000-2005 |
3 | * Stefan Roese, DENX Software Engineering, sr@denx.de. | |
0f8c9768 | 4 | * |
3765b3e7 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
0f8c9768 WD |
6 | */ |
7 | ||
8 | /* | |
9 | * board/config.h - configuration options, board specific | |
10 | */ | |
11 | ||
12 | #ifndef __CONFIG_H | |
13 | #define __CONFIG_H | |
14 | ||
15 | /* | |
16 | * High Level Configuration Options | |
17 | * (easy to change) | |
18 | */ | |
19 | ||
20 | #define CONFIG_405GP 1 /* This is a PPC405 CPU */ | |
095b8a37 | 21 | #define CONFIG_WALNUT 1 /* ...on a WALNUT board */ |
2ae18241 WD |
22 | /* ...or on a SYCAMORE board */ |
23 | ||
24 | #define CONFIG_SYS_TEXT_BASE 0xFFFC0000 | |
0f8c9768 | 25 | |
72675dc6 SR |
26 | /* |
27 | * Include common defines/options for all AMCC eval boards | |
28 | */ | |
29 | #define CONFIG_HOSTNAME walnut | |
30 | #include "amcc-common.h" | |
31 | ||
095b8a37 | 32 | #define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ |
0f8c9768 | 33 | |
72675dc6 SR |
34 | /* |
35 | * Default environment variables | |
36 | */ | |
37 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
38 | CONFIG_AMCC_DEF_ENV \ | |
39 | CONFIG_AMCC_DEF_ENV_POWERPC \ | |
40 | CONFIG_AMCC_DEF_ENV_PPC_OLD \ | |
41 | CONFIG_AMCC_DEF_ENV_NOR_UPD \ | |
8a316c9b SR |
42 | "kernel_addr=fff80000\0" \ |
43 | "ramdisk_addr=fff80000\0" \ | |
8a316c9b | 44 | "" |
0f8c9768 | 45 | |
095b8a37 | 46 | #define CONFIG_PHY_ADDR 1 /* PHY address */ |
a00eccfe | 47 | #define CONFIG_HAS_ETH0 1 |
4f92ed5f | 48 | |
0f8c9768 WD |
49 | #define CONFIG_RTC_DS174x 1 /* use DS1743 RTC in Walnut */ |
50 | ||
dca3b3d6 | 51 | /* |
72675dc6 | 52 | * Commands additional to the ones defined in amcc-common.h |
dca3b3d6 | 53 | */ |
dca3b3d6 | 54 | #define CONFIG_CMD_DATE |
dca3b3d6 | 55 | #define CONFIG_CMD_PCI |
dca3b3d6 | 56 | #define CONFIG_CMD_SDRAM |
dca3b3d6 | 57 | |
0f8c9768 WD |
58 | #define CONFIG_SPD_EEPROM 1 /* use SPD EEPROM for setup */ |
59 | ||
0f8c9768 | 60 | /* |
6d0f6bcf JCPV |
61 | * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1. |
62 | * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31. | |
63 | * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD value. | |
0f8c9768 WD |
64 | * The Linux BASE_BAUD define should match this configuration. |
65 | * baseBaud = cpuClock/(uartDivisor*16) | |
6d0f6bcf | 66 | * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock, |
0f8c9768 WD |
67 | * set Linux BASE_BAUD to 403200. |
68 | */ | |
550650dd | 69 | #define CONFIG_CONS_INDEX 1 /* Use UART0 */ |
6d0f6bcf JCPV |
70 | #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */ |
71 | #undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */ | |
72 | #define CONFIG_SYS_BASE_BAUD 691200 | |
0f8c9768 | 73 | |
8a316c9b SR |
74 | /*----------------------------------------------------------------------- |
75 | * I2C stuff | |
76 | *----------------------------------------------------------------------- | |
77 | */ | |
880540de | 78 | #define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 |
0f8c9768 | 79 | |
6d0f6bcf JCPV |
80 | #define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1) |
81 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
82 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 | |
83 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 | |
4f92ed5f | 84 | |
0f8c9768 WD |
85 | /*----------------------------------------------------------------------- |
86 | * PCI stuff | |
87 | *----------------------------------------------------------------------- | |
88 | */ | |
095b8a37 WD |
89 | #define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ |
90 | #define PCI_HOST_FORCE 1 /* configure as pci host */ | |
91 | #define PCI_HOST_AUTO 2 /* detected via arbiter enable */ | |
92 | ||
842033e6 | 93 | #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ |
095b8a37 | 94 | #define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ |
095b8a37 | 95 | /* resource configuration */ |
8a316c9b | 96 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
0f8c9768 | 97 | |
6d0f6bcf JCPV |
98 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ |
99 | #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */ | |
100 | #define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */ | |
101 | #define CONFIG_SYS_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */ | |
102 | #define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ | |
103 | #define CONFIG_SYS_PCI_PTM2LA 0x00000000 /* disabled */ | |
104 | #define CONFIG_SYS_PCI_PTM2MS 0x00000000 /* disabled */ | |
105 | #define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ | |
0f8c9768 | 106 | |
0f8c9768 WD |
107 | /*----------------------------------------------------------------------- |
108 | * Start addresses for the final memory configuration | |
109 | * (Set up by the startup code) | |
0f8c9768 | 110 | */ |
6d0f6bcf | 111 | #define CONFIG_SYS_FLASH_BASE 0xFFF80000 |
8a316c9b SR |
112 | |
113 | /* | |
114 | * Define here the location of the environment variables (FLASH or NVRAM). | |
115 | * Note: DENX encourages to use redundant environment in FLASH. NVRAM is only | |
095b8a37 | 116 | * supported for backward compatibility. |
8a316c9b SR |
117 | */ |
118 | #if 1 | |
5a1aceb0 | 119 | #define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ |
8a316c9b | 120 | #else |
9314cee6 | 121 | #define CONFIG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */ |
8a316c9b | 122 | #endif |
0f8c9768 | 123 | |
0f8c9768 WD |
124 | /*----------------------------------------------------------------------- |
125 | * FLASH organization | |
126 | */ | |
6d0f6bcf | 127 | #define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* FLASH bank #0 */ |
095b8a37 | 128 | #define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */ |
8a316c9b | 129 | |
6d0f6bcf JCPV |
130 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
131 | #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ | |
0f8c9768 | 132 | |
6d0f6bcf JCPV |
133 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
134 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ | |
0f8c9768 | 135 | |
6d0f6bcf | 136 | #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ |
8a316c9b | 137 | |
6d0f6bcf JCPV |
138 | #define CONFIG_SYS_FLASH_ADDR0 0x5555 |
139 | #define CONFIG_SYS_FLASH_ADDR1 0x2aaa | |
140 | #define CONFIG_SYS_FLASH_WORD_SIZE unsigned char | |
8a316c9b | 141 | |
5a1aceb0 | 142 | #ifdef CONFIG_ENV_IS_IN_FLASH |
0e8d1586 | 143 | #define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ |
6d0f6bcf | 144 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE) |
0e8d1586 | 145 | #define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ |
8a316c9b SR |
146 | |
147 | /* Address and size of Redundant Environment Sector */ | |
0e8d1586 JCPV |
148 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE) |
149 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) | |
5a1aceb0 | 150 | #endif /* CONFIG_ENV_IS_IN_FLASH */ |
8a316c9b | 151 | |
0f8c9768 WD |
152 | /*----------------------------------------------------------------------- |
153 | * NVRAM organization | |
154 | */ | |
6d0f6bcf JCPV |
155 | #define CONFIG_SYS_NVRAM_BASE_ADDR 0xf0000000 /* NVRAM base address */ |
156 | #define CONFIG_SYS_NVRAM_SIZE 0x1ff8 /* NVRAM size */ | |
0f8c9768 | 157 | |
9314cee6 | 158 | #ifdef CONFIG_ENV_IS_IN_NVRAM |
0e8d1586 JCPV |
159 | #define CONFIG_ENV_SIZE 0x1000 /* Size of Environment vars */ |
160 | #define CONFIG_ENV_ADDR \ | |
6d0f6bcf | 161 | (CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE) /* Env */ |
0f8c9768 | 162 | #endif |
8a316c9b | 163 | |
8a316c9b SR |
164 | /*----------------------------------------------------------------------- |
165 | * External Bus Controller (EBC) Setup | |
0f8c9768 WD |
166 | */ |
167 | ||
8a316c9b | 168 | /* Memory Bank 0 (Flash Bank 0) initialization */ |
6d0f6bcf JCPV |
169 | #define CONFIG_SYS_EBC_PB0AP 0x9B015480 |
170 | #define CONFIG_SYS_EBC_PB0CR 0xFFF18000 /* BAS=0xFFF,BS=1MB,BU=R/W,BW=8bit */ | |
8a316c9b | 171 | |
6d0f6bcf JCPV |
172 | #define CONFIG_SYS_EBC_PB1AP 0x02815480 |
173 | #define CONFIG_SYS_EBC_PB1CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ | |
8a316c9b | 174 | |
6d0f6bcf JCPV |
175 | #define CONFIG_SYS_EBC_PB2AP 0x04815A80 |
176 | #define CONFIG_SYS_EBC_PB2CR 0xF0118000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit */ | |
0f8c9768 | 177 | |
6d0f6bcf JCPV |
178 | #define CONFIG_SYS_EBC_PB3AP 0x01815280 |
179 | #define CONFIG_SYS_EBC_PB3CR 0xF0218000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit */ | |
0f8c9768 | 180 | |
6d0f6bcf JCPV |
181 | #define CONFIG_SYS_EBC_PB7AP 0x01815280 |
182 | #define CONFIG_SYS_EBC_PB7CR 0xF0318000 /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit */ | |
8a316c9b SR |
183 | |
184 | /*----------------------------------------------------------------------- | |
185 | * External peripheral base address | |
186 | *----------------------------------------------------------------------- | |
187 | */ | |
6d0f6bcf JCPV |
188 | #define CONFIG_SYS_KEY_REG_BASE_ADDR 0xF0100000 |
189 | #define CONFIG_SYS_IR_REG_BASE_ADDR 0xF0200000 | |
190 | #define CONFIG_SYS_FPGA_REG_BASE_ADDR 0xF0300000 | |
0f8c9768 WD |
191 | |
192 | /*----------------------------------------------------------------------- | |
8a316c9b | 193 | * Definitions for initial stack pointer and data area |
0f8c9768 | 194 | */ |
6d0f6bcf | 195 | #define CONFIG_SYS_INIT_DCACHE_CS 4 /* use cs # 4 for data cache memory */ |
0f8c9768 | 196 | |
6d0f6bcf | 197 | #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 /* inside of SDRAM */ |
553f0982 | 198 | #define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */ |
25ddd1fb | 199 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 200 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
0f8c9768 WD |
201 | |
202 | /*----------------------------------------------------------------------- | |
203 | * Definitions for Serial Presence Detect EEPROM address | |
204 | * (to get SDRAM settings) | |
205 | */ | |
095b8a37 | 206 | #define SPD_EEPROM_ADDRESS 0x50 |
0f8c9768 | 207 | |
0f8c9768 | 208 | #endif /* __CONFIG_H */ |