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1 | /* |
2 | * Configuation settings for the WB45N CPU Module. | |
3 | * | |
4 | * SPDX-License-Identifier: GPL-2.0+ | |
5 | */ | |
6 | ||
7 | #ifndef __CONFIG_H__ | |
8 | #define __CONFIG_H__ | |
9 | ||
10 | #include <asm/hardware.h> | |
11 | ||
12 | #define CONFIG_SYS_TEXT_BASE 0x23f00000 | |
13 | ||
14 | /* ARM asynchronous clock */ | |
15 | #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 | |
16 | #define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */ | |
17 | ||
18 | #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ | |
19 | #define CONFIG_SETUP_MEMORY_TAGS | |
20 | #define CONFIG_INITRD_TAG | |
21 | #define CONFIG_SKIP_LOWLEVEL_INIT | |
22 | ||
23 | /* general purpose I/O */ | |
24 | #define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ | |
25 | #define CONFIG_AT91_GPIO | |
26 | ||
27 | /* serial console */ | |
28 | #define CONFIG_ATMEL_USART | |
29 | #define CONFIG_USART_BASE ATMEL_BASE_DBGU | |
30 | #define CONFIG_USART_ID ATMEL_ID_SYS | |
31 | ||
32 | /* | |
33 | * BOOTP options | |
34 | */ | |
35 | #define CONFIG_BOOTP_BOOTFILESIZE | |
36 | #define CONFIG_BOOTP_BOOTPATH | |
37 | #define CONFIG_BOOTP_GATEWAY | |
38 | #define CONFIG_BOOTP_HOSTNAME | |
39 | ||
40 | /* SDRAM */ | |
41 | #define CONFIG_NR_DRAM_BANKS 1 | |
42 | #define CONFIG_SYS_SDRAM_BASE 0x20000000 | |
43 | #define CONFIG_SYS_SDRAM_SIZE 0x04000000 /* 64 MB */ | |
44 | ||
45 | #define CONFIG_SYS_INIT_SP_ADDR \ | |
46 | (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE) | |
47 | ||
48 | /* NAND flash */ | |
49 | #define CONFIG_NAND_ATMEL | |
50 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
51 | #define CONFIG_SYS_NAND_BASE 0x40000000 | |
52 | /* our ALE is AD21 */ | |
53 | #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) | |
54 | /* our CLE is AD22 */ | |
55 | #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) | |
56 | #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD4 | |
57 | #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD5 | |
58 | ||
59 | /* PMECC & PMERRLOC */ | |
60 | #define CONFIG_ATMEL_NAND_HWECC 1 | |
61 | #define CONFIG_ATMEL_NAND_HW_PMECC 1 | |
62 | #define CONFIG_PMECC_CAP 4 | |
63 | #define CONFIG_PMECC_SECTOR_SIZE 512 | |
64 | ||
65 | #define CONFIG_MTD_DEVICE | |
66 | #define CONFIG_CMD_MTDPARTS | |
67 | #define CONFIG_MTD_PARTITIONS | |
68 | #define CONFIG_RBTREE | |
69 | #define CONFIG_LZO | |
70 | ||
71 | /* Ethernet */ | |
72 | #define CONFIG_MACB | |
73 | #define CONFIG_RMII | |
74 | #define CONFIG_NET_RETRY_COUNT 20 | |
75 | #define CONFIG_MACB_SEARCH_PHY | |
76 | #define CONFIG_ETHADDR C0:EE:40:00:00:00 | |
77 | #define CONFIG_ENV_OVERWRITE 1 | |
78 | ||
79 | /* System */ | |
80 | #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ | |
81 | #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE | |
82 | #define CONFIG_SYS_MEMTEST_END 0x23e00000 | |
83 | ||
84 | #ifdef CONFIG_SYS_USE_NANDFLASH | |
85 | /* bootstrap + u-boot + env + linux in nandflash */ | |
86 | #define CONFIG_ENV_OFFSET 0xa0000 | |
87 | #define CONFIG_ENV_OFFSET_REDUND 0xc0000 | |
88 | #define CONFIG_ENV_SIZE 0x20000 /* 1 block = 128 kB */ | |
89 | ||
90 | #define CONFIG_BOOTCOMMAND "nand read 0x22000000 0xe0000 0x280000; " \ | |
91 | "run _mtd; bootm" | |
92 | ||
93 | #define MTDIDS_DEFAULT "nand0=atmel_nand" | |
94 | #define MTDPARTS_DEFAULT "mtdparts=atmel_nand:" \ | |
95 | "128K(at91bs)," \ | |
96 | "512K(u-boot)," \ | |
97 | "128K(u-boot-env)," \ | |
98 | "128K(redund-env)," \ | |
99 | "2560K(kernel-a)," \ | |
100 | "2560K(kernel-b)," \ | |
101 | "38912K(rootfs-a)," \ | |
102 | "38912K(rootfs-b)," \ | |
103 | "46208K(user)," \ | |
104 | "512K(logs)" | |
105 | ||
106 | #else | |
107 | #error No boot method selected, please select 'CONFIG_SYS_USE_NANDFLASH' | |
108 | #endif | |
109 | ||
110 | #define CONFIG_BOOTARGS "console=ttyS0,115200 earlyprintk " \ | |
111 | "rw noinitrd mem=64M " \ | |
112 | "rootfstype=ubifs root=ubi0:rootfs ubi.mtd=6" | |
113 | ||
114 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
115 | "_mtd=mtdparts default; setenv bootargs ${bootargs} ${mtdparts}\0" \ | |
116 | "autoload=no\0" \ | |
117 | "autostart=no\0" \ | |
118 | "ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \ | |
119 | "\0" | |
120 | ||
121 | #define CONFIG_SYS_CBSIZE 256 | |
122 | #define CONFIG_SYS_MAXARGS 16 | |
123 | #define CONFIG_SYS_LONGHELP | |
124 | #define CONFIG_CMDLINE_EDITING | |
125 | #define CONFIG_AUTO_COMPLETE | |
126 | ||
127 | /* | |
128 | * Size of malloc() pool | |
129 | */ | |
130 | #define CONFIG_SYS_MALLOC_LEN (512 * 1024 + 0x1000) | |
131 | ||
132 | /* SPL */ | |
133 | #define CONFIG_SPL_FRAMEWORK | |
134 | #define CONFIG_SPL_TEXT_BASE 0x300000 | |
135 | #define CONFIG_SPL_MAX_SIZE 0x6000 | |
136 | #define CONFIG_SPL_STACK 0x308000 | |
137 | ||
138 | #define CONFIG_SPL_BSS_START_ADDR 0x20000000 | |
139 | #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 | |
140 | #define CONFIG_SYS_SPL_MALLOC_START 0x20080000 | |
141 | #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 | |
142 | ||
143 | #define CONFIG_SYS_MONITOR_LEN (512 << 10) | |
144 | ||
145 | #define CONFIG_SYS_MASTER_CLOCK 132096000 | |
146 | #define CONFIG_SYS_AT91_PLLA 0x20c73f03 | |
147 | #define CONFIG_SYS_MCKR 0x1301 | |
148 | #define CONFIG_SYS_MCKR_CSS 0x1302 | |
149 | ||
150 | #define CONFIG_SPL_NAND_DRIVERS | |
151 | #define CONFIG_SPL_NAND_BASE | |
152 | #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000 | |
153 | #define CONFIG_SYS_NAND_5_ADDR_CYCLE | |
154 | #define CONFIG_SYS_NAND_PAGE_SIZE 0x800 | |
155 | #define CONFIG_SYS_NAND_PAGE_COUNT 64 | |
156 | #define CONFIG_SYS_NAND_OOBSIZE 64 | |
157 | #define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000 | |
158 | #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0 | |
159 | #define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER | |
160 | ||
161 | #endif /* __CONFIG_H__ */ |