[people/ms/u-boot.git] / include / configs / woodburn_common.h

/*
 * (C) Copyright 2011, Stefano Babic <sbabic@denx.de>
 *
 * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
 *
 * Configuration for the woodburn board.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __WOODBURN_COMMON_CONFIG_H
#define __WOODBURN_COMMON_CONFIG_H

#include <asm/arch/imx-regs.h>

 /* High Level Configuration Options */
#define CONFIG_MX35
#define CONFIG_MX35_HCLK_FREQ	24000000
#define CONFIG_SYS_FSL_CLK

#define CONFIG_SYS_DCACHE_OFF
#define CONFIG_SYS_CACHELINE_SIZE	32

#define CONFIG_DISPLAY_CPUINFO

/* Only in case the value is not present in mach-types.h */
#ifndef MACH_TYPE_FLEA3
#define MACH_TYPE_FLEA3                3668
#endif

#define CONFIG_MACH_TYPE		MACH_TYPE_FLEA3

/* This is required to setup the ESDC controller */

#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs */
#define CONFIG_REVISION_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG

/*
 * Size of malloc() pool
 */
#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 1024 * 1024)

/*
 * Hardware drivers
 */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
#define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
#define CONFIG_SYS_SPD_BUS_NUM		0
#define CONFIG_MXC_SPI
#define CONFIG_MXC_GPIO

/* PMIC Controller */
#define CONFIG_POWER
#define CONFIG_POWER_I2C
#define CONFIG_POWER_FSL
#define CONFIG_POWER_FSL_MC13892
#define CONFIG_SYS_FSL_PMIC_I2C_ADDR	0x8
#define CONFIG_RTC_MC13XXX


/* mmc driver */
#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR	0
#define CONFIG_SYS_FSL_ESDHC_NUM	1

/*
 * UART (console)
 */
#define CONFIG_MXC_UART
#define CONFIG_MXC_UART_BASE	UART1_BASE

/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_CONS_INDEX	1
#define CONFIG_BAUDRATE		115200

/*
 * Command definition
 */
#define CONFIG_CMD_DATE
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_DNS

#define CONFIG_CMD_NAND
#define CONFIG_CMD_CACHE

#define CONFIG_CMD_MII

#define CONFIG_CMD_MMC
#define CONFIG_DOS_PARTITION
#define CONFIG_EFI_PARTITION
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT

#define CONFIG_MXC_GPIO

#define CONFIG_NET_RETRY_COUNT	100

#define CONFIG_BOOTDELAY	3

#define CONFIG_LOADADDR		0x80800000	/* loadaddr env var */


/*
 * Ethernet on SOC (FEC)
 */
#define CONFIG_FEC_MXC
#define IMX_FEC_BASE	FEC_BASE_ADDR
#define CONFIG_PHYLIB
#define CONFIG_PHY_MICREL
#define CONFIG_FEC_MXC_PHYADDR	0x1

#define CONFIG_MII
#define CONFIG_DISCOVER_PHY

#define CONFIG_ARP_TIMEOUT	200UL

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP	/* undef to save memory */
#define CONFIG_CMDLINE_EDITING

#define CONFIG_AUTO_COMPLETE
#define CONFIG_SYS_CBSIZE	256	/* Console I/O Buffer Size */
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS	16	/* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */

#define CONFIG_SYS_MEMTEST_START	0	/* memtest works on */
#define CONFIG_SYS_MEMTEST_END		0x10000

#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR

/*
 * Stack sizes
 *
 * The stack sizes are set up in start.S using the settings below
 */
#define CONFIG_STACKSIZE	(128 * 1024)	/* regular stack */

/*
 * Physical Memory Map
 */
#define CONFIG_NR_DRAM_BANKS	1
#define PHYS_SDRAM_1		CSD0_BASE_ADDR
#define PHYS_SDRAM_1_SIZE	(256 * 1024 * 1024)

#define CONFIG_SYS_SDRAM_BASE		CSD0_BASE_ADDR

#define CONFIG_SYS_GBL_DATA_OFFSET	(LOW_LEVEL_SRAM_STACK - \
						IRAM_BASE_ADDR - \
						GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR		(IRAM_BASE_ADDR + \
					CONFIG_SYS_GBL_DATA_OFFSET)

/*
 * MTD Command for mtdparts
 */
#define CONFIG_CMD_MTDPARTS
#define CONFIG_MTD_DEVICE
#define CONFIG_FLASH_CFI_MTD
#define CONFIG_MTD_PARTITIONS
#define MTDIDS_DEFAULT		"nand0=mxc_nand,nor0=physmap-flash.0"
#define MTDPARTS_DEFAULT	"mtdparts=mxc_nand:50m(root1)," \
				"32m(rootfb)," \
				"64m(pcache)," \
				"64m(app1)," \
				"10m(app2),-(spool);" \
				"physmap-flash.0:512k(u-boot),64k(env1)," \
				"64k(env2),3776k(kernel1),3776k(kernel2)"

/*
 * FLASH and environment organization
 */
#define CONFIG_SYS_FLASH_BASE		CS0_BASE_ADDR
#define CONFIG_SYS_MAX_FLASH_BANKS 1	/* max number of memory banks */
#define CONFIG_SYS_MAX_FLASH_SECT 512	/* max number of sectors on one chip */
/* Monitor at beginning of flash */
#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)

#define CONFIG_ENV_SECT_SIZE	(128 * 1024)
#define CONFIG_ENV_SIZE		CONFIG_ENV_SECT_SIZE

/* Address and size of Redundant Environment Sector	*/
#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
#define CONFIG_ENV_SIZE_REDUND	CONFIG_ENV_SIZE

#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + \
				CONFIG_SYS_MONITOR_LEN)

#define CONFIG_ENV_IS_IN_FLASH

/*
 * CFI FLASH driver setup
 */
#define CONFIG_SYS_FLASH_CFI		/* Flash memory is CFI compliant */
#define CONFIG_FLASH_CFI_DRIVER

/* A non-standard buffered write algorithm */
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	/* faster */
#define CONFIG_SYS_FLASH_PROTECTION	/* Use hardware sector protection */

/*
 * NAND FLASH driver setup
 */
#define CONFIG_NAND_MXC
#define CONFIG_NAND_MXC_V1_1
#define CONFIG_MXC_NAND_REGS_BASE	(NFC_BASE_ADDR)
#define CONFIG_SYS_MAX_NAND_DEVICE	1
#define CONFIG_SYS_NAND_BASE		(NFC_BASE_ADDR)
#define CONFIG_MXC_NAND_HWECC
#define CONFIG_SYS_NAND_LARGEPAGE

#if 0
#define CONFIG_MTD_DEBUG
#define CONFIG_MTD_DEBUG_VERBOSE	7
#endif
#define CONFIG_SYS_NAND_ONFI_DETECTION

/*
 * Default environment and default scripts
 * to update uboot and load kernel
 */

#define CONFIG_HOSTNAME woodburn
#define	CONFIG_EXTRA_ENV_SETTINGS					\
	"netdev=eth0\0"							\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=${serverip}:${rootpath}\0"			\
	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
	"addip_sta=setenv bootargs ${bootargs} "			\
		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
		":${hostname}:${netdev}:off panic=1\0"			\
	"addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0"		\
	"addip=if test -n ${ipdyn};then run addip_dyn;"			\
		"else run addip_sta;fi\0"	\
	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"		\
	"addtty=setenv bootargs ${bootargs}"				\
		" console=ttymxc0,${baudrate}\0"			\
	"addmisc=setenv bootargs ${bootargs} ${misc}\0"			\
	"loadaddr=80800000\0"						\
	"kernel_addr_r=80800000\0"					\
	"hostname=" __stringify(CONFIG_HOSTNAME) "\0"			\
	"bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage\0"		\
	"ramdisk_file=" __stringify(CONFIG_HOSTNAME) "/uRamdisk\0"	\
	"flash_self=run ramargs addip addtty addmtd addmisc;"		\
		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
	"flash_nfs=run nfsargs addip addtty addmtd addmisc;"		\
		"bootm ${kernel_addr}\0"				\
	"net_nfs=tftp ${kernel_addr_r} ${bootfile}; "			\
		"run nfsargs addip addtty addmtd addmisc;"		\
		"bootm ${kernel_addr_r}\0"				\
	"net_self_load=tftp ${kernel_addr_r} ${bootfile};"		\
		"tftp ${ramdisk_addr_r} ${ramdisk_file};\0"		\
	"net_self=if run net_self_load;then "				\
		"run ramargs addip addtty addmtd addmisc;"		\
		"bootm ${kernel_addr_r} ${ramdisk_addr_r};"		\
		"else echo Images not loades;fi\0"			\
	"u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.bin\0"		\
	"load=tftp ${loadaddr} ${u-boot}\0"				\
	"uboot_addr=" __stringify(CONFIG_SYS_MONITOR_BASE) "\0"		\
	"update=protect off ${uboot_addr} +80000;"			\
		"erase ${uboot_addr} +80000;"				\
		"cp.b ${loadaddr} ${uboot_addr} ${filesize}\0"		\
	"upd=if run load;then echo Updating u-boot;if run update;"	\
		"then echo U-Boot updated;"				\
			"else echo Error updating u-boot !;"		\
			"echo Board without bootloader !!;"		\
		"fi;"							\
		"else echo U-Boot not downloaded..exiting;fi\0"		\
	"bootcmd=run net_nfs\0"

#endif				/* __CONFIG_H */
Commit	Line	Data
d81b27a2 SB	1	/*
	2	* (C) Copyright 2011, Stefano Babic <sbabic@denx.de>
	3	*
	4	* (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
	5	*
	6	* Configuration for the woodburn board.
	7	*
3765b3e7	8	* SPDX-License-Identifier: GPL-2.0+
d81b27a2 SB	9	*/
	10
	11	#ifndef __WOODBURN_COMMON_CONFIG_H
	12	#define __WOODBURN_COMMON_CONFIG_H
	13
	14	#include <asm/arch/imx-regs.h>
	15
	16	/* High Level Configuration Options */
d81b27a2 SB	17	#define CONFIG_MX35
d81b27a2 SB	18	#define CONFIG_MX35_HCLK_FREQ 24000000
18fb0e3c	19	#define CONFIG_SYS_FSL_CLK
d81b27a2 SB	20
	21	#define CONFIG_SYS_DCACHE_OFF
	22	#define CONFIG_SYS_CACHELINE_SIZE 32
	23
	24	#define CONFIG_DISPLAY_CPUINFO
	25
	26	/* Only in case the value is not present in mach-types.h */
	27	#ifndef MACH_TYPE_FLEA3
	28	#define MACH_TYPE_FLEA3 3668
	29	#endif
	30
	31	#define CONFIG_MACH_TYPE MACH_TYPE_FLEA3
	32
	33	/* This is required to setup the ESDC controller */
	34
	35	#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
	36	#define CONFIG_REVISION_TAG
	37	#define CONFIG_SETUP_MEMORY_TAGS
	38	#define CONFIG_INITRD_TAG
	39
	40	/*
	41	* Size of malloc() pool
	42	*/
	43	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024)
	44
	45	/*
	46	* Hardware drivers
	47	*/
b089d039	48	#define CONFIG_SYS_I2C
b089d039	49	#define CONFIG_SYS_I2C_MXC
03544c66 AA	50	#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
03544c66 AA	51	#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
f8cb101e	52	#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
b089d039	53	#define CONFIG_SYS_SPD_BUS_NUM 0
d81b27a2 SB	54	#define CONFIG_MXC_SPI
	55	#define CONFIG_MXC_GPIO
	56
	57	/* PMIC Controller */
05a860c2 SB	58	#define CONFIG_POWER
	59	#define CONFIG_POWER_I2C
	60	#define CONFIG_POWER_FSL
913702ca	61	#define CONFIG_POWER_FSL_MC13892
d81b27a2 SB	62	#define CONFIG_SYS_FSL_PMIC_I2C_ADDR 0x8
	63	#define CONFIG_RTC_MC13XXX
	64
	65
	66	/* mmc driver */
	67	#define CONFIG_MMC
	68	#define CONFIG_GENERIC_MMC
	69	#define CONFIG_FSL_ESDHC
	70	#define CONFIG_SYS_FSL_ESDHC_ADDR 0
	71	#define CONFIG_SYS_FSL_ESDHC_NUM 1
	72
	73	/*
	74	* UART (console)
	75	*/
	76	#define CONFIG_MXC_UART
	77	#define CONFIG_MXC_UART_BASE UART1_BASE
	78
	79	/* allow to overwrite serial and ethaddr */
	80	#define CONFIG_ENV_OVERWRITE
	81	#define CONFIG_CONS_INDEX 1
	82	#define CONFIG_BAUDRATE 115200
	83
	84	/*
	85	* Command definition
	86	*/
d81b27a2	87	#define CONFIG_CMD_DATE
d81b27a2 SB	88	#define CONFIG_BOOTP_SUBNETMASK
	89	#define CONFIG_BOOTP_GATEWAY
	90	#define CONFIG_BOOTP_DNS
	91
	92	#define CONFIG_CMD_NAND
	93	#define CONFIG_CMD_CACHE
	94
d81b27a2	95	#define CONFIG_CMD_MII
d81b27a2 SB	96
	97	#define CONFIG_CMD_MMC
	98	#define CONFIG_DOS_PARTITION
	99	#define CONFIG_EFI_PARTITION
	100	#define CONFIG_CMD_EXT2
	101	#define CONFIG_CMD_FAT
	102
d81b27a2 SB	103	#define CONFIG_MXC_GPIO
	104
	105	#define CONFIG_NET_RETRY_COUNT 100
	106
	107	#define CONFIG_BOOTDELAY 3
	108
	109	#define CONFIG_LOADADDR 0x80800000 /* loadaddr env var */
	110
	111
	112	/*
	113	* Ethernet on SOC (FEC)
	114	*/
	115	#define CONFIG_FEC_MXC
	116	#define IMX_FEC_BASE FEC_BASE_ADDR
	117	#define CONFIG_PHYLIB
	118	#define CONFIG_PHY_MICREL
	119	#define CONFIG_FEC_MXC_PHYADDR 0x1
	120
	121	#define CONFIG_MII
	122	#define CONFIG_DISCOVER_PHY
	123
	124	#define CONFIG_ARP_TIMEOUT 200UL
	125
	126	/*
	127	* Miscellaneous configurable options
	128	*/
	129	#define CONFIG_SYS_LONGHELP /* undef to save memory */
d81b27a2	130	#define CONFIG_CMDLINE_EDITING
d81b27a2 SB	131
	132	#define CONFIG_AUTO_COMPLETE
	133	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
	134	/* Print Buffer Size */
	135	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
	136	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	137	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
	138
	139	#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */
	140	#define CONFIG_SYS_MEMTEST_END 0x10000
	141
d81b27a2 SB	142	#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
d81b27a2 SB	143
d81b27a2 SB	144	/*
	145	* Stack sizes
	146	*
	147	* The stack sizes are set up in start.S using the settings below
	148	*/
	149	#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
	150
	151	/*
	152	* Physical Memory Map
	153	*/
	154	#define CONFIG_NR_DRAM_BANKS 1
	155	#define PHYS_SDRAM_1 CSD0_BASE_ADDR
	156	#define PHYS_SDRAM_1_SIZE (256 * 1024 * 1024)
	157
	158	#define CONFIG_SYS_SDRAM_BASE CSD0_BASE_ADDR
	159
	160	#define CONFIG_SYS_GBL_DATA_OFFSET (LOW_LEVEL_SRAM_STACK - \
	161	IRAM_BASE_ADDR - \
	162	GENERATED_GBL_DATA_SIZE)
	163	#define CONFIG_SYS_INIT_SP_ADDR (IRAM_BASE_ADDR + \
	164	CONFIG_SYS_GBL_DATA_OFFSET)
	165
	166	/*
	167	* MTD Command for mtdparts
	168	*/
	169	#define CONFIG_CMD_MTDPARTS
	170	#define CONFIG_MTD_DEVICE
	171	#define CONFIG_FLASH_CFI_MTD
	172	#define CONFIG_MTD_PARTITIONS
	173	#define MTDIDS_DEFAULT "nand0=mxc_nand,nor0=physmap-flash.0"
	174	#define MTDPARTS_DEFAULT "mtdparts=mxc_nand:50m(root1)," \
	175	"32m(rootfb)," \
	176	"64m(pcache)," \
	177	"64m(app1)," \
	178	"10m(app2),-(spool);" \
	179	"physmap-flash.0:512k(u-boot),64k(env1)," \
	180	"64k(env2),3776k(kernel1),3776k(kernel2)"
	181
	182	/*
	183	* FLASH and environment organization
	184	*/
	185	#define CONFIG_SYS_FLASH_BASE CS0_BASE_ADDR
	186	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
	187	#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
	188	/* Monitor at beginning of flash */
	189	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
	190	#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
	191
	192	#define CONFIG_ENV_SECT_SIZE (128 * 1024)
	193	#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
	194
	195	/* Address and size of Redundant Environment Sector */
	196	#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
	197	#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
	198
	199	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
	200	CONFIG_SYS_MONITOR_LEN)
	201
	202	#define CONFIG_ENV_IS_IN_FLASH
	203
	204	/*
	205	* CFI FLASH driver setup
	206	*/
	207	#define CONFIG_SYS_FLASH_CFI /* Flash memory is CFI compliant */
208	#define CONFIG_FLASH_CFI_DRIVER
209
210	/* A non-standard buffered write algorithm */
211	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* faster */
212	#define CONFIG_SYS_FLASH_PROTECTION /* Use hardware sector protection */
213
214	/*
215	* NAND FLASH driver setup
216	*/
217	#define CONFIG_NAND_MXC
218	#define CONFIG_NAND_MXC_V1_1
219	#define CONFIG_MXC_NAND_REGS_BASE (NFC_BASE_ADDR)
220	#define CONFIG_SYS_MAX_NAND_DEVICE 1
221	#define CONFIG_SYS_NAND_BASE (NFC_BASE_ADDR)
222	#define CONFIG_MXC_NAND_HWECC
223	#define CONFIG_SYS_NAND_LARGEPAGE
224
225	#if 0
226	#define CONFIG_MTD_DEBUG
227	#define CONFIG_MTD_DEBUG_VERBOSE 7
228	#endif
229	#define CONFIG_SYS_NAND_ONFI_DETECTION
230
231	/*
232	* Default environment and default scripts
233	* to update uboot and load kernel
234	*/
d81b27a2 SB	235
	236	#define CONFIG_HOSTNAME woodburn
	237	#define CONFIG_EXTRA_ENV_SETTINGS \
	238	"netdev=eth0\0" \
	239	"nfsargs=setenv bootargs root=/dev/nfs rw " \
	240	"nfsroot=${serverip}:${rootpath}\0" \
	241	"ramargs=setenv bootargs root=/dev/ram rw\0" \
	242	"addip_sta=setenv bootargs ${bootargs} " \
	243	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
	244	":${hostname}:${netdev}:off panic=1\0" \
	245	"addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \
	246	"addip=if test -n ${ipdyn};then run addip_dyn;" \
	247	"else run addip_sta;fi\0" \
	248	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
	249	"addtty=setenv bootargs ${bootargs}" \
	250	" console=ttymxc0,${baudrate}\0" \
	251	"addmisc=setenv bootargs ${bootargs} ${misc}\0" \
	252	"loadaddr=80800000\0" \
	253	"kernel_addr_r=80800000\0" \
4a8c3f69 AG	254	"hostname=" __stringify(CONFIG_HOSTNAME) "\0" \
	255	"bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage\0" \
	256	"ramdisk_file=" __stringify(CONFIG_HOSTNAME) "/uRamdisk\0" \
d81b27a2 SB	257	"flash_self=run ramargs addip addtty addmtd addmisc;" \
	258	"bootm ${kernel_addr} ${ramdisk_addr}\0" \
	259	"flash_nfs=run nfsargs addip addtty addmtd addmisc;" \
	260	"bootm ${kernel_addr}\0" \
	261	"net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
	262	"run nfsargs addip addtty addmtd addmisc;" \
	263	"bootm ${kernel_addr_r}\0" \
	264	"net_self_load=tftp ${kernel_addr_r} ${bootfile};" \
	265	"tftp ${ramdisk_addr_r} ${ramdisk_file};\0" \
	266	"net_self=if run net_self_load;then " \
	267	"run ramargs addip addtty addmtd addmisc;" \
	268	"bootm ${kernel_addr_r} ${ramdisk_addr_r};" \
	269	"else echo Images not loades;fi\0" \
4a8c3f69	270	"u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.bin\0" \
d81b27a2	271	"load=tftp ${loadaddr} ${u-boot}\0" \
4a8c3f69	272	"uboot_addr=" __stringify(CONFIG_SYS_MONITOR_BASE) "\0" \
d81b27a2 SB	273	"update=protect off ${uboot_addr} +80000;" \
	274	"erase ${uboot_addr} +80000;" \
	275	"cp.b ${loadaddr} ${uboot_addr} ${filesize}\0" \
	276	"upd=if run load;then echo Updating u-boot;if run update;" \
	277	"then echo U-Boot updated;" \
	278	"else echo Error updating u-boot !;" \
	279	"echo Board without bootloader !!;" \
	280	"fi;" \
	281	"else echo U-Boot not downloaded..exiting;fi\0" \
	282	"bootcmd=run net_nfs\0"
	283
	284	#endif /* __CONFIG_H */