projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 412ae53a AA |
1 | /* |
| 2 | * WORK Microwave work_92105 board configuration file | |
| 3 | * | |
| 4 | * (C) Copyright 2014 DENX Software Engineering GmbH | |
| 5 | * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr> | |
| 6 | * | |
| 7 | * SPDX-License-Identifier: GPL-2.0+ | |
| 8 | */ | |
| 9 | ||
| 10 | #ifndef __CONFIG_WORK_92105_H__ | |
| 11 | #define __CONFIG_WORK_92105_H__ | |
| 12 | ||
| 13 | /* SoC and board defines */ | |
| 14 | #include <linux/sizes.h> | |
| 15 | #include <asm/arch/cpu.h> | |
| 16 | ||
| 17 | /* | |
| 18 | * Define work_92105 machine type by hand -- done only for compatibility | |
| 19 | * with original board code | |
| 20 | */ | |
| cd7b6344 | 21 | #define CONFIG_MACH_TYPE 736 |
| 412ae53a AA |
22 | |
| 23 | #define CONFIG_SYS_ICACHE_OFF | |
| 24 | #define CONFIG_SYS_DCACHE_OFF | |
| 25 | #if !defined(CONFIG_SPL_BUILD) | |
| 26 | #define CONFIG_SKIP_LOWLEVEL_INIT | |
| 27 | #endif | |
| 412ae53a AA |
28 | #define CONFIG_BOARD_EARLY_INIT_R |
| 29 | ||
| 30 | /* generate LPC32XX-specific SPL image */ | |
| 31 | #define CONFIG_LPC32XX_SPL | |
| 32 | ||
| 33 | /* | |
| 34 | * Memory configurations | |
| 35 | */ | |
| 36 | #define CONFIG_NR_DRAM_BANKS 1 | |
| 37 | #define CONFIG_SYS_MALLOC_LEN SZ_1M | |
| 38 | #define CONFIG_SYS_SDRAM_BASE EMC_DYCS0_BASE | |
| 39 | #define CONFIG_SYS_SDRAM_SIZE SZ_128M | |
| 412ae53a AA |
40 | #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + SZ_32K) |
| 41 | #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - SZ_1M) | |
| 42 | ||
| 43 | #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_32K) | |
| 44 | ||
| 45 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_512K \ | |
| 46 | - GENERATED_GBL_DATA_SIZE) | |
| 47 | ||
| 48 | /* | |
| 49 | * Serial Driver | |
| 50 | */ | |
| 51 | #define CONFIG_SYS_LPC32XX_UART 5 /* UART5 - NS16550 */ | |
| 412ae53a AA |
52 | |
| 53 | /* | |
| 54 | * Ethernet Driver | |
| 55 | */ | |
| 56 | ||
| 57 | #define CONFIG_PHY_SMSC | |
| 58 | #define CONFIG_LPC32XX_ETH | |
| 412ae53a AA |
59 | #define CONFIG_PHY_ADDR 0 |
| 60 | #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN | |
| 412ae53a AA |
61 | /* FIXME: remove "Waiting for PHY auto negotiation to complete..." message */ |
| 62 | ||
| 63 | /* | |
| 64 | * I2C driver | |
| 65 | */ | |
| 66 | ||
| 67 | #define CONFIG_SYS_I2C_LPC32XX | |
| 68 | #define CONFIG_SYS_I2C | |
| 412ae53a AA |
69 | #define CONFIG_SYS_I2C_SPEED 350000 |
| 70 | ||
| 71 | /* | |
| 72 | * I2C EEPROM | |
| 73 | */ | |
| 74 | ||
| 412ae53a AA |
75 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x56 |
| 76 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 | |
| 77 | ||
| 78 | /* | |
| 79 | * I2C RTC | |
| 80 | */ | |
| 81 | ||
| 412ae53a AA |
82 | #define CONFIG_RTC_DS1374 |
| 83 | ||
| 412ae53a AA |
84 | /* |
| 85 | * U-Boot General Configurations | |
| 86 | */ | |
| 412ae53a | 87 | #define CONFIG_SYS_CBSIZE 1024 |
| 412ae53a AA |
88 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE |
| 89 | ||
| 412ae53a AA |
90 | /* |
| 91 | * NAND chip timings for FIXME: which one? | |
| 92 | */ | |
| 93 | ||
| 94 | #define CONFIG_LPC32XX_NAND_MLC_TCEA_DELAY 333333333 | |
| 95 | #define CONFIG_LPC32XX_NAND_MLC_BUSY_DELAY 10000000 | |
| 96 | #define CONFIG_LPC32XX_NAND_MLC_NAND_TA 18181818 | |
| 97 | #define CONFIG_LPC32XX_NAND_MLC_RD_HIGH 31250000 | |
| 98 | #define CONFIG_LPC32XX_NAND_MLC_RD_LOW 45454545 | |
| 99 | #define CONFIG_LPC32XX_NAND_MLC_WR_HIGH 40000000 | |
| 100 | #define CONFIG_LPC32XX_NAND_MLC_WR_LOW 83333333 | |
| 101 | ||
| 102 | /* | |
| 103 | * NAND | |
| 104 | */ | |
| 105 | ||
| 106 | /* driver configuration */ | |
| 107 | #define CONFIG_SYS_NAND_SELF_INIT | |
| 108 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
| 109 | #define CONFIG_SYS_MAX_NAND_CHIPS 1 | |
| 110 | #define CONFIG_SYS_NAND_BASE MLC_NAND_BASE | |
| 111 | #define CONFIG_NAND_LPC32XX_MLC | |
| 112 | ||
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113 | /* |
| 114 | * GPIO | |
| 115 | */ | |
| 116 | ||
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117 | #define CONFIG_LPC32XX_GPIO |
| 118 | ||
| 119 | /* | |
| 120 | * SSP/SPI/DISPLAY | |
| 121 | */ | |
| 122 | ||
| 412ae53a | 123 | #define CONFIG_LPC32XX_SSP_TIMEOUT 100000 |
| 412ae53a AA |
124 | /* |
| 125 | * Environment | |
| 126 | */ | |
| 127 | ||
| 412ae53a AA |
128 | #define CONFIG_ENV_SIZE 0x00020000 |
| 129 | #define CONFIG_ENV_OFFSET 0x00100000 | |
| 130 | #define CONFIG_ENV_OFFSET_REDUND 0x00120000 | |
| 131 | #define CONFIG_ENV_ADDR 0x80000100 | |
| 132 | ||
| 412ae53a AA |
133 | /* |
| 134 | * Boot Linux | |
| 135 | */ | |
| 136 | #define CONFIG_CMDLINE_TAG | |
| 137 | #define CONFIG_SETUP_MEMORY_TAGS | |
| 138 | #define CONFIG_INITRD_TAG | |
| 139 | ||
| 412ae53a | 140 | #define CONFIG_BOOTFILE "uImage" |
| 412ae53a AA |
141 | #define CONFIG_LOADADDR 0x80008000 |
| 142 | ||
| 143 | /* | |
| 144 | * SPL | |
| 145 | */ | |
| 146 | ||
| 147 | /* SPL will be executed at offset 0 */ | |
| 148 | #define CONFIG_SPL_TEXT_BASE 0x00000000 | |
| 149 | /* SPL will use SRAM as stack */ | |
| 150 | #define CONFIG_SPL_STACK 0x0000FFF8 | |
| 412ae53a | 151 | /* Use the framework and generic lib */ |
| 412ae53a | 152 | /* SPL will use serial */ |
| 412ae53a | 153 | /* SPL will load U-Boot from NAND offset 0x40000 */ |
| 412ae53a AA |
154 | #define CONFIG_SPL_NAND_DRIVERS |
| 155 | #define CONFIG_SPL_NAND_BASE | |
| 156 | #define CONFIG_SPL_NAND_BOOT | |
| 157 | #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x00040000 | |
| 158 | #define CONFIG_SPL_PAD_TO 0x20000 | |
| 159 | /* U-Boot will be 0x40000 bytes, loaded and run at CONFIG_SYS_TEXT_BASE */ | |
| 160 | #define CONFIG_SYS_MONITOR_LEN 0x40000 /* actually, MAX size */ | |
| 161 | #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE | |
| 162 | #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE | |
| 163 | ||
| 164 | /* | |
| 165 | * Include SoC specific configuration | |
| 166 | */ | |
| 167 | #include <asm/arch/config.h> | |
| 168 | ||
| 169 | #endif /* __CONFIG_WORK_92105_H__*/ |