[people/ms/u-boot.git] / include / configs / x600.h

/*
 * (C) Copyright 2009
 * Vipin Kumar, STMicroelectronics, <vipin.kumar@st.com>
 *
 * Copyright (C) 2012, 2015 Stefan Roese <sr@denx.de>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */
#define CONFIG_SPEAR600				/* SPEAr600 SoC */
#define CONFIG_X600				/* on X600 board */
#define CONFIG_SYS_THUMB_BUILD

#include <asm/arch/hardware.h>

/* Timer, HZ specific defines */
#define CONFIG_SYS_HZ_CLOCK			8300000

#define	CONFIG_SYS_TEXT_BASE			0x00800040
#define CONFIG_SYS_FLASH_BASE			0xf8000000
/* Reserve 8KiB for SPL */
#define CONFIG_SPL_PAD_TO			8192	/* decimal for 'dd' */
#define CONFIG_SYS_SPL_LEN			CONFIG_SPL_PAD_TO
#define CONFIG_SYS_UBOOT_BASE			(CONFIG_SYS_FLASH_BASE + \
						 CONFIG_SYS_SPL_LEN)
#define CONFIG_SYS_UBOOT_START			CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MONITOR_BASE			CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_MONITOR_LEN			0x60000

#define CONFIG_ENV_IS_IN_FLASH

/* Serial Configuration (PL011) */
#define CONFIG_SYS_SERIAL0			0xD0000000
#define CONFIG_SYS_SERIAL1			0xD0080000
#define CONFIG_PL01x_PORTS			{ (void *)CONFIG_SYS_SERIAL0, \
						(void *)CONFIG_SYS_SERIAL1 }
#define CONFIG_PL011_SERIAL
#define CONFIG_PL011_CLOCK			(48 * 1000 * 1000)
#define CONFIG_CONS_INDEX			0
#define CONFIG_BAUDRATE				115200
#define CONFIG_SYS_BAUDRATE_TABLE		{ 9600, 19200, 38400, \
						  57600, 115200 }
#define CONFIG_SYS_LOADS_BAUD_CHANGE

/* NOR FLASH config options */
#define CONFIG_ST_SMI
#define CONFIG_SYS_MAX_FLASH_BANKS		1
#define CONFIG_SYS_FLASH_BANK_SIZE		0x01000000
#define CONFIG_SYS_FLASH_ADDR_BASE		{ CONFIG_SYS_FLASH_BASE }
#define CONFIG_SYS_MAX_FLASH_SECT		128
#define CONFIG_SYS_FLASH_EMPTY_INFO
#define CONFIG_SYS_FLASH_ERASE_TOUT		(3 * CONFIG_SYS_HZ)
#define CONFIG_SYS_FLASH_WRITE_TOUT		(3 * CONFIG_SYS_HZ)

/* NAND FLASH config options */
#define CONFIG_NAND_FSMC
#define CONFIG_SYS_NAND_SELF_INIT
#define CONFIG_SYS_MAX_NAND_DEVICE		1
#define CONFIG_SYS_NAND_BASE			CONFIG_FSMC_NAND_BASE
#define CONFIG_MTD_ECC_SOFT
#define CONFIG_SYS_FSMC_NAND_8BIT
#define CONFIG_SYS_NAND_ONFI_DETECTION
#define CONFIG_NAND_ECC_BCH
#define CONFIG_BCH

/* UBI/UBI config options */
#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_PARTITIONS
#define CONFIG_RBTREE

/* Ethernet config options */
#define CONFIG_MII
#define CONFIG_PHY_RESET_DELAY			10000		/* in usec */
#define CONFIG_PHY_ADDR		0	/* PHY address */
#define CONFIG_PHY_GIGE			/* Include GbE speed/duplex detection */
#define CONFIG_PHY_MICREL
#define CONFIG_PHY_MICREL_KSZ9031

#define CONFIG_SPEAR_GPIO

/* I2C config options */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_BASE			0xD0200000
#define CONFIG_SYS_I2C_SPEED			400000
#define CONFIG_SYS_I2C_SLAVE			0x02
#define CONFIG_I2C_CHIPADDRESS			0x50

#define CONFIG_RTC_M41T62	1
#define CONFIG_SYS_I2C_RTC_ADDR	0x68

/* FPGA config options */
#define CONFIG_FPGA
#define CONFIG_FPGA_XILINX
#define CONFIG_FPGA_SPARTAN3
#define CONFIG_FPGA_COUNT	1

/* USB EHCI options */
#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_SPEAR
#define CONFIG_USB_MAX_CONTROLLER_COUNT	2

/*
 * Command support defines
 */
#define CONFIG_CMD_DATE
#define CONFIG_CMD_ENV
#define CONFIG_CMD_FPGA_LOADMK
#define CONFIG_CMD_MTDPARTS
#define CONFIG_CMD_NAND
#define CONFIG_CMD_SAVES
#define CONFIG_CMD_UBI
#define CONFIG_CMD_UBIFS
#define CONFIG_LZO

/* Filesystem support (for USB key) */
#define CONFIG_SUPPORT_VFAT
#define CONFIG_DOS_PARTITION


/*
 * U-Boot Environment placing definitions.
 */
#define CONFIG_ENV_SECT_SIZE			0x00010000
#define CONFIG_ENV_ADDR				(CONFIG_SYS_MONITOR_BASE + \
						 CONFIG_SYS_MONITOR_LEN)
#define CONFIG_ENV_SIZE				0x02000
#define CONFIG_ENV_ADDR_REDUND			(CONFIG_ENV_ADDR + \
						 CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND			(CONFIG_ENV_SIZE)

/* Miscellaneous configurable options */
#define CONFIG_ARCH_CPU_INIT
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_BOOT_PARAMS_ADDR			0x00000100
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_MISC_INIT_R
#define CONFIG_BOARD_LATE_INIT
#define CONFIG_MX_CYCLIC		/* enable mdc/mwc commands      */

#define CONFIG_SYS_MEMTEST_START		0x00800000
#define CONFIG_SYS_MEMTEST_END			0x04000000
#define CONFIG_SYS_MALLOC_LEN			(8 << 20)
#define CONFIG_IDENT_STRING			"-SPEAr"
#define CONFIG_SYS_LONGHELP
#define CONFIG_CMDLINE_EDITING
#define CONFIG_AUTO_COMPLETE
#define CONFIG_SYS_CBSIZE			256
#define CONFIG_SYS_PBSIZE			(CONFIG_SYS_CBSIZE + \
						 sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS			16
#define CONFIG_SYS_BARGSIZE			CONFIG_SYS_CBSIZE
#define CONFIG_SYS_LOAD_ADDR			0x00800000
#define CONFIG_SYS_CONSOLE_INFO_QUIET

/* Use last 2 lwords in internal SRAM for bootcounter */
#define CONFIG_BOOTCOUNT_LIMIT
#define CONFIG_SYS_BOOTCOUNT_ADDR		(CONFIG_SRAM_BASE + \
						 CONFIG_SRAM_SIZE)

#define CONFIG_HOSTNAME				x600
#define CONFIG_UBI_PART				ubi0
#define CONFIG_UBIFS_VOLUME			rootfs

#define MTDIDS_DEFAULT		"nand0=nand"
#define MTDPARTS_DEFAULT	"mtdparts=nand:64M(ubi0),64M(ubi1)"

#define	CONFIG_EXTRA_ENV_SETTINGS					\
	"u-boot_addr=1000000\0"						\
	"u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.spr\0"		\
	"load=tftp ${u-boot_addr} ${u-boot}\0"				\
	"update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE)	\
		" +${filesize};"					\
		"erase " __stringify(CONFIG_SYS_MONITOR_BASE) " +${filesize};" \
		"cp.b ${u-boot_addr} " __stringify(CONFIG_SYS_MONITOR_BASE) \
		" ${filesize};"						\
		"protect on " __stringify(CONFIG_SYS_MONITOR_BASE)	\
		" +${filesize}\0"					\
	"upd=run load update\0"						\
	"ubifs=" __stringify(CONFIG_HOSTNAME) "/ubifs.img\0"		\
	"part=" __stringify(CONFIG_UBI_PART) "\0"			\
	"vol=" __stringify(CONFIG_UBIFS_VOLUME) "\0"			\
	"load_ubifs=tftp ${kernel_addr} ${ubifs}\0"			\
	"update_ubifs=ubi part ${part};ubi write ${kernel_addr} ${vol}"	\
		" ${filesize}\0"					\
	"upd_ubifs=run load_ubifs update_ubifs\0"			\
	"init_ubifs=nand erase.part ubi0;ubi part ${part};"		\
		"ubi create ${vol} 4000000\0"				\
	"netdev=eth0\0"							\
	"rootpath=/opt/eldk-4.2/arm\0"					\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=${serverip}:${rootpath}\0"			\
	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
	"boot_part=0\0"							\
	"altbootcmd=if test $boot_part -eq 0;then "			\
			"echo Switching to partition 1!;"		\
			"setenv boot_part 1;"				\
		"else; "						\
			"echo Switching to partition 0!;"		\
			"setenv boot_part 0;"				\
		"fi;"							\
		"saveenv;boot\0"					\
	"ubifsargs=set bootargs ubi.mtd=ubi${boot_part} "		\
		"root=ubi0:rootfs rootfstype=ubifs\0"			\
	"kernel=" __stringify(CONFIG_HOSTNAME) "/uImage\0"		\
	"kernel_fs=/boot/uImage \0"					\
	"kernel_addr=1000000\0"						\
	"dtb=" __stringify(CONFIG_HOSTNAME) "/"				\
		__stringify(CONFIG_HOSTNAME) ".dtb\0"			\
	"dtb_fs=/boot/" __stringify(CONFIG_HOSTNAME) ".dtb\0"		\
	"dtb_addr=1800000\0"						\
	"load_kernel=tftp ${kernel_addr} ${kernel}\0"			\
	"load_dtb=tftp ${dtb_addr} ${dtb}\0"				\
	"addip=setenv bootargs ${bootargs} "				\
		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
		":${hostname}:${netdev}:off panic=1\0"			\
	"addcon=setenv bootargs ${bootargs} console=ttyAMA0,"		\
		"${baudrate}\0"						\
	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"		\
	"net_nfs=run load_dtb load_kernel; "				\
		"run nfsargs addip addcon addmtd addmisc;"		\
		"bootm ${kernel_addr} - ${dtb_addr}\0"			\
	"mtdids=" MTDIDS_DEFAULT "\0"					\
	"mtdparts=" MTDPARTS_DEFAULT "\0"				\
	"nand_ubifs=run ubifs_mount ubifs_load ubifsargs addip"		\
		" addcon addmisc addmtd;"				\
		"bootm ${kernel_addr} - ${dtb_addr}\0"			\
	"ubifs_mount=ubi part ubi${boot_part};ubifsmount ubi:rootfs\0"	\
	"ubifs_load=ubifsload ${kernel_addr} ${kernel_fs};"		\
		"ubifsload ${dtb_addr} ${dtb_fs};\0"			\
	"nand_ubifs=run ubifs_mount ubifs_load ubifsargs addip addcon "	\
		"addmtd addmisc;bootm ${kernel_addr} - ${dtb_addr}\0"	\
	"bootcmd=run nand_ubifs\0"					\
	"\0"

/* Physical Memory Map */
#define CONFIG_NR_DRAM_BANKS			1
#define PHYS_SDRAM_1				0x00000000
#define PHYS_SDRAM_1_MAXSIZE			0x40000000

#define CONFIG_SYS_SDRAM_BASE			PHYS_SDRAM_1
#define CONFIG_SRAM_BASE			0xd2800000
/* Preserve the last 2 lwords for the boot-counter */
#define CONFIG_SRAM_SIZE			((8 << 10) - 0x8)
#define CONFIG_SYS_INIT_RAM_ADDR		CONFIG_SRAM_BASE
#define CONFIG_SYS_INIT_RAM_SIZE		CONFIG_SRAM_SIZE

#define CONFIG_SYS_INIT_SP_OFFSET		\
	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)

#define CONFIG_SYS_INIT_SP_ADDR			\
	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)

/*
 * SPL related defines
 */
#define CONFIG_SPL_TEXT_BASE		0xd2800b00
#define CONFIG_SPL_MAX_SIZE		(CONFIG_SRAM_SIZE - 0xb00)
#define	CONFIG_SPL_START_S_PATH	"arch/arm/cpu/arm926ejs/spear"
#define CONFIG_SPL_LDSCRIPT	"arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds"

#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_NOR_SUPPORT
#define CONFIG_SPL_SERIAL_SUPPORT

/*
 * Please select/define only one of the following
 * Each definition corresponds to a supported DDR chip.
 * DDR configuration is based on the following selection
 */
#define CONFIG_DDR_MT47H64M16		1
#define CONFIG_DDR_MT47H32M16		0
#define CONFIG_DDR_MT47H128M8		0

/*
 * Synchronous/Asynchronous operation of DDR
 *
 * Select CONFIG_DDR_2HCLK for DDR clk = 333MHz, synchronous operation
 * Select CONFIG_DDR_HCLK for DDR clk = 166MHz, synchronous operation
 * Select CONFIG_DDR_PLL2 for DDR clk = PLL2, asynchronous operation
 */
#define CONFIG_DDR_2HCLK		1
#define CONFIG_DDR_HCLK			0
#define CONFIG_DDR_PLL2			0

/*
 * xxx_BOOT_SUPPORTED macro defines whether a booting type is supported
 * or not. Modify/Add to only these macros to define new boot types
 */
#define USB_BOOT_SUPPORTED		0
#define PCIE_BOOT_SUPPORTED		0
#define SNOR_BOOT_SUPPORTED		1
#define NAND_BOOT_SUPPORTED		1
#define PNOR_BOOT_SUPPORTED		0
#define TFTP_BOOT_SUPPORTED		0
#define UART_BOOT_SUPPORTED		0
#define SPI_BOOT_SUPPORTED		0
#define I2C_BOOT_SUPPORTED		0
#define MMC_BOOT_SUPPORTED		0

#endif  /* __CONFIG_H */
Commit	Line	Data
995b72dd SR	1	/*
	2	* (C) Copyright 2009
	3	* Vipin Kumar, STMicroelectronics, <vipin.kumar@st.com>
	4	*
2fbdbda1	5	* Copyright (C) 2012, 2015 Stefan Roese <sr@denx.de>
995b72dd	6	*
1a459660	7	* SPDX-License-Identifier: GPL-2.0+
995b72dd SR	8	*/
	9
	10	#ifndef __CONFIG_H
	11	#define __CONFIG_H
	12
	13	/*
	14	* High Level Configuration Options
	15	* (easy to change)
	16	*/
	17	#define CONFIG_SPEAR600 /* SPEAr600 SoC */
	18	#define CONFIG_X600 /* on X600 board */
9b6aa00d	19	#define CONFIG_SYS_THUMB_BUILD
995b72dd SR	20
	21	#include <asm/arch/hardware.h>
	22
	23	/* Timer, HZ specific defines */
995b72dd SR	24	#define CONFIG_SYS_HZ_CLOCK 8300000
	25
	26	#define CONFIG_SYS_TEXT_BASE 0x00800040
	27	#define CONFIG_SYS_FLASH_BASE 0xf8000000
	28	/* Reserve 8KiB for SPL */
	29	#define CONFIG_SPL_PAD_TO 8192 /* decimal for 'dd' */
	30	#define CONFIG_SYS_SPL_LEN CONFIG_SPL_PAD_TO
	31	#define CONFIG_SYS_UBOOT_BASE (CONFIG_SYS_FLASH_BASE + \
	32	CONFIG_SYS_SPL_LEN)
285e266b	33	#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
995b72dd SR	34	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
	35	#define CONFIG_SYS_MONITOR_LEN 0x60000
	36
	37	#define CONFIG_ENV_IS_IN_FLASH
	38
	39	/* Serial Configuration (PL011) */
	40	#define CONFIG_SYS_SERIAL0 0xD0000000
	41	#define CONFIG_SYS_SERIAL1 0xD0080000
	42	#define CONFIG_PL01x_PORTS { (void *)CONFIG_SYS_SERIAL0, \
	43	(void *)CONFIG_SYS_SERIAL1 }
	44	#define CONFIG_PL011_SERIAL
	45	#define CONFIG_PL011_CLOCK (48 * 1000 * 1000)
	46	#define CONFIG_CONS_INDEX 0
	47	#define CONFIG_BAUDRATE 115200
	48	#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, \
	49	57600, 115200 }
	50	#define CONFIG_SYS_LOADS_BAUD_CHANGE
	51
	52	/* NOR FLASH config options */
	53	#define CONFIG_ST_SMI
	54	#define CONFIG_SYS_MAX_FLASH_BANKS 1
	55	#define CONFIG_SYS_FLASH_BANK_SIZE 0x01000000
	56	#define CONFIG_SYS_FLASH_ADDR_BASE { CONFIG_SYS_FLASH_BASE }
	57	#define CONFIG_SYS_MAX_FLASH_SECT 128
	58	#define CONFIG_SYS_FLASH_EMPTY_INFO
	59	#define CONFIG_SYS_FLASH_ERASE_TOUT (3 * CONFIG_SYS_HZ)
	60	#define CONFIG_SYS_FLASH_WRITE_TOUT (3 * CONFIG_SYS_HZ)
	61
	62	/* NAND FLASH config options */
	63	#define CONFIG_NAND_FSMC
	64	#define CONFIG_SYS_NAND_SELF_INIT
	65	#define CONFIG_SYS_MAX_NAND_DEVICE 1
	66	#define CONFIG_SYS_NAND_BASE CONFIG_FSMC_NAND_BASE
	67	#define CONFIG_MTD_ECC_SOFT
	68	#define CONFIG_SYS_FSMC_NAND_8BIT
	69	#define CONFIG_SYS_NAND_ONFI_DETECTION
0ddc5a2d SR	70	#define CONFIG_NAND_ECC_BCH
0ddc5a2d SR	71	#define CONFIG_BCH
995b72dd SR	72
	73	/* UBI/UBI config options */
	74	#define CONFIG_MTD_DEVICE
	75	#define CONFIG_MTD_PARTITIONS
	76	#define CONFIG_RBTREE
	77
	78	/* Ethernet config options */
	79	#define CONFIG_MII
995b72dd	80	#define CONFIG_PHY_RESET_DELAY 10000 /* in usec */
995b72dd SR	81	#define CONFIG_PHY_ADDR 0 /* PHY address */
995b72dd SR	82	#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
f7c32e8e SR	83	#define CONFIG_PHY_MICREL
f7c32e8e SR	84	#define CONFIG_PHY_MICREL_KSZ9031
995b72dd SR	85
	86	#define CONFIG_SPEAR_GPIO
	87
	88	/* I2C config options */
678398b1	89	#define CONFIG_SYS_I2C
f93f589c	90	#define CONFIG_SYS_I2C_BASE 0xD0200000
995b72dd SR	91	#define CONFIG_SYS_I2C_SPEED 400000
	92	#define CONFIG_SYS_I2C_SLAVE 0x02
	93	#define CONFIG_I2C_CHIPADDRESS 0x50
	94
	95	#define CONFIG_RTC_M41T62 1
	96	#define CONFIG_SYS_I2C_RTC_ADDR 0x68
	97
	98	/* FPGA config options */
	99	#define CONFIG_FPGA
	100	#define CONFIG_FPGA_XILINX
	101	#define CONFIG_FPGA_SPARTAN3
	102	#define CONFIG_FPGA_COUNT 1
	103
285e266b SR	104	/* USB EHCI options */
	105	#define CONFIG_USB_EHCI
	106	#define CONFIG_USB_EHCI_SPEAR
285e266b SR	107	#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
285e266b SR	108
995b72dd SR	109	/*
	110	* Command support defines
	111	*/
995b72dd	112	#define CONFIG_CMD_DATE
995b72dd	113	#define CONFIG_CMD_ENV
64e809af	114	#define CONFIG_CMD_FPGA_LOADMK
995b72dd SR	115	#define CONFIG_CMD_MTDPARTS
995b72dd SR	116	#define CONFIG_CMD_NAND
995b72dd SR	117	#define CONFIG_CMD_SAVES
	118	#define CONFIG_CMD_UBI
	119	#define CONFIG_CMD_UBIFS
	120	#define CONFIG_LZO
	121
285e266b SR	122	/* Filesystem support (for USB key) */
	123	#define CONFIG_SUPPORT_VFAT
	124	#define CONFIG_DOS_PARTITION
	125
995b72dd	126
995b72dd SR	127	/*
	128	* U-Boot Environment placing definitions.
	129	*/
	130	#define CONFIG_ENV_SECT_SIZE 0x00010000
	131	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
	132	CONFIG_SYS_MONITOR_LEN)
	133	#define CONFIG_ENV_SIZE 0x02000
	134	#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + \
	135	CONFIG_ENV_SECT_SIZE)
	136	#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
	137
	138	/* Miscellaneous configurable options */
	139	#define CONFIG_ARCH_CPU_INIT
	140	#define CONFIG_DISPLAY_CPUINFO
	141	#define CONFIG_BOOT_PARAMS_ADDR 0x00000100
	142	#define CONFIG_CMDLINE_TAG
995b72dd SR	143	#define CONFIG_SETUP_MEMORY_TAGS
	144	#define CONFIG_MISC_INIT_R
	145	#define CONFIG_BOARD_LATE_INIT
995b72dd	146	#define CONFIG_MX_CYCLIC /* enable mdc/mwc commands */
995b72dd SR	147
	148	#define CONFIG_SYS_MEMTEST_START 0x00800000
	149	#define CONFIG_SYS_MEMTEST_END 0x04000000
285e266b	150	#define CONFIG_SYS_MALLOC_LEN (8 << 20)
995b72dd SR	151	#define CONFIG_IDENT_STRING "-SPEAr"
995b72dd SR	152	#define CONFIG_SYS_LONGHELP
995b72dd	153	#define CONFIG_CMDLINE_EDITING
285e266b	154	#define CONFIG_AUTO_COMPLETE
995b72dd SR	155	#define CONFIG_SYS_CBSIZE 256
	156	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
	157	sizeof(CONFIG_SYS_PROMPT) + 16)
	158	#define CONFIG_SYS_MAXARGS 16
	159	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
	160	#define CONFIG_SYS_LOAD_ADDR 0x00800000
	161	#define CONFIG_SYS_CONSOLE_INFO_QUIET
995b72dd SR	162
	163	/* Use last 2 lwords in internal SRAM for bootcounter */
	164	#define CONFIG_BOOTCOUNT_LIMIT
2fbdbda1 SR	165	#define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SRAM_BASE + \
2fbdbda1 SR	166	CONFIG_SRAM_SIZE)
995b72dd SR	167
	168	#define CONFIG_HOSTNAME x600
	169	#define CONFIG_UBI_PART ubi0
	170	#define CONFIG_UBIFS_VOLUME rootfs
	171
995b72dd SR	172	#define MTDIDS_DEFAULT "nand0=nand"
	173	#define MTDPARTS_DEFAULT "mtdparts=nand:64M(ubi0),64M(ubi1)"
	174
	175	#define CONFIG_EXTRA_ENV_SETTINGS \
	176	"u-boot_addr=1000000\0" \
4a8c3f69	177	"u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.spr\0" \
995b72dd	178	"load=tftp ${u-boot_addr} ${u-boot}\0" \
4a8c3f69 AG	179	"update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \
	180	" +${filesize};" \
	181	"erase " __stringify(CONFIG_SYS_MONITOR_BASE) " +${filesize};" \
	182	"cp.b ${u-boot_addr} " __stringify(CONFIG_SYS_MONITOR_BASE) \
995b72dd	183	" ${filesize};" \
4a8c3f69	184	"protect on " __stringify(CONFIG_SYS_MONITOR_BASE) \
995b72dd SR	185	" +${filesize}\0" \
995b72dd SR	186	"upd=run load update\0" \
4a8c3f69 AG	187	"ubifs=" __stringify(CONFIG_HOSTNAME) "/ubifs.img\0" \
	188	"part=" __stringify(CONFIG_UBI_PART) "\0" \
	189	"vol=" __stringify(CONFIG_UBIFS_VOLUME) "\0" \
995b72dd SR	190	"load_ubifs=tftp ${kernel_addr} ${ubifs}\0" \
	191	"update_ubifs=ubi part ${part};ubi write ${kernel_addr} ${vol}" \
	192	" ${filesize}\0" \
	193	"upd_ubifs=run load_ubifs update_ubifs\0" \
	194	"init_ubifs=nand erase.part ubi0;ubi part ${part};" \
	195	"ubi create ${vol} 4000000\0" \
	196	"netdev=eth0\0" \
	197	"rootpath=/opt/eldk-4.2/arm\0" \
	198	"nfsargs=setenv bootargs root=/dev/nfs rw " \
	199	"nfsroot=${serverip}:${rootpath}\0" \
	200	"ramargs=setenv bootargs root=/dev/ram rw\0" \
	201	"boot_part=0\0" \
	202	"altbootcmd=if test $boot_part -eq 0;then " \
	203	"echo Switching to partition 1!;" \
	204	"setenv boot_part 1;" \
	205	"else; " \
	206	"echo Switching to partition 0!;" \
	207	"setenv boot_part 0;" \
	208	"fi;" \
	209	"saveenv;boot\0" \
	210	"ubifsargs=set bootargs ubi.mtd=ubi${boot_part} " \
	211	"root=ubi0:rootfs rootfstype=ubifs\0" \
4a8c3f69	212	"kernel=" __stringify(CONFIG_HOSTNAME) "/uImage\0" \
995b72dd SR	213	"kernel_fs=/boot/uImage \0" \
995b72dd SR	214	"kernel_addr=1000000\0" \
4a8c3f69 AG	215	"dtb=" __stringify(CONFIG_HOSTNAME) "/" \
	216	__stringify(CONFIG_HOSTNAME) ".dtb\0" \
	217	"dtb_fs=/boot/" __stringify(CONFIG_HOSTNAME) ".dtb\0" \
995b72dd SR	218	"dtb_addr=1800000\0" \
	219	"load_kernel=tftp ${kernel_addr} ${kernel}\0" \
	220	"load_dtb=tftp ${dtb_addr} ${dtb}\0" \
	221	"addip=setenv bootargs ${bootargs} " \
	222	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
	223	":${hostname}:${netdev}:off panic=1\0" \
	224	"addcon=setenv bootargs ${bootargs} console=ttyAMA0," \
	225	"${baudrate}\0" \
	226	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
	227	"net_nfs=run load_dtb load_kernel; " \
	228	"run nfsargs addip addcon addmtd addmisc;" \
	229	"bootm ${kernel_addr} - ${dtb_addr}\0" \
	230	"mtdids=" MTDIDS_DEFAULT "\0" \
	231	"mtdparts=" MTDPARTS_DEFAULT "\0" \
	232	"nand_ubifs=run ubifs_mount ubifs_load ubifsargs addip" \
	233	" addcon addmisc addmtd;" \
	234	"bootm ${kernel_addr} - ${dtb_addr}\0" \
949a7710	235	"ubifs_mount=ubi part ubi${boot_part};ubifsmount ubi:rootfs\0" \
995b72dd SR	236	"ubifs_load=ubifsload ${kernel_addr} ${kernel_fs};" \
	237	"ubifsload ${dtb_addr} ${dtb_fs};\0" \
	238	"nand_ubifs=run ubifs_mount ubifs_load ubifsargs addip addcon " \
	239	"addmtd addmisc;bootm ${kernel_addr} - ${dtb_addr}\0" \
	240	"bootcmd=run nand_ubifs\0" \
	241	"\0"
	242
995b72dd SR	243	/* Physical Memory Map */
	244	#define CONFIG_NR_DRAM_BANKS 1
	245	#define PHYS_SDRAM_1 0x00000000
	246	#define PHYS_SDRAM_1_MAXSIZE 0x40000000
	247
	248	#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
2fbdbda1 SR	249	#define CONFIG_SRAM_BASE 0xd2800000
	250	/* Preserve the last 2 lwords for the boot-counter */
	251	#define CONFIG_SRAM_SIZE ((8 << 10) - 0x8)
	252	#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SRAM_BASE
	253	#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SRAM_SIZE
995b72dd SR	254
	255	#define CONFIG_SYS_INIT_SP_OFFSET \
	256	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
	257
	258	#define CONFIG_SYS_INIT_SP_ADDR \
	259	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
	260
	261	/*
	262	* SPL related defines
	263	*/
2fbdbda1 SR	264	#define CONFIG_SPL_TEXT_BASE 0xd2800b00
2fbdbda1 SR	265	#define CONFIG_SPL_MAX_SIZE (CONFIG_SRAM_SIZE - 0xb00)
995b72dd SR	266	#define CONFIG_SPL_START_S_PATH "arch/arm/cpu/arm926ejs/spear"
	267	#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds"
	268
2fbdbda1 SR	269	#define CONFIG_SPL_FRAMEWORK
2fbdbda1 SR	270	#define CONFIG_SPL_NOR_SUPPORT
995b72dd	271	#define CONFIG_SPL_SERIAL_SUPPORT
995b72dd SR	272
	273	/*
	274	* Please select/define only one of the following
	275	* Each definition corresponds to a supported DDR chip.
	276	* DDR configuration is based on the following selection
	277	*/
	278	#define CONFIG_DDR_MT47H64M16 1
	279	#define CONFIG_DDR_MT47H32M16 0
	280	#define CONFIG_DDR_MT47H128M8 0
	281
	282	/*
	283	* Synchronous/Asynchronous operation of DDR
	284	*
	285	* Select CONFIG_DDR_2HCLK for DDR clk = 333MHz, synchronous operation
	286	* Select CONFIG_DDR_HCLK for DDR clk = 166MHz, synchronous operation
	287	* Select CONFIG_DDR_PLL2 for DDR clk = PLL2, asynchronous operation
	288	*/
	289	#define CONFIG_DDR_2HCLK 1
	290	#define CONFIG_DDR_HCLK 0
	291	#define CONFIG_DDR_PLL2 0
	292
	293	/*
	294	* xxx_BOOT_SUPPORTED macro defines whether a booting type is supported
	295	* or not. Modify/Add to only these macros to define new boot types
	296	*/
	297	#define USB_BOOT_SUPPORTED 0
	298	#define PCIE_BOOT_SUPPORTED 0
	299	#define SNOR_BOOT_SUPPORTED 1
	300	#define NAND_BOOT_SUPPORTED 1
	301	#define PNOR_BOOT_SUPPORTED 0
	302	#define TFTP_BOOT_SUPPORTED 0
	303	#define UART_BOOT_SUPPORTED 0
	304	#define SPI_BOOT_SUPPORTED 0
	305	#define I2C_BOOT_SUPPORTED 0
	306	#define MMC_BOOT_SUPPORTED 0
	307
	308	#endif /* __CONFIG_H */