[people/ms/u-boot.git] / include / configs / xaeniax.h

/*
 * (C) Copyright 2004-2005
 * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
 *
 * (C) Copyright 2004
 * Vincent Dubey, Xa SA, vincent.dubey@xa-ch.com
 *
 * (C) Copyright 2002
 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.ne
 *
 * (C) Copyright 2002
 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
 * Marius Groeger <mgroeger@sysgo.de>
 *
 * Configuation settings for the xaeniax board.
 *
 * SPDX-License-Identifier:	GPL-2.0+ 
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */
#define CONFIG_CPU_PXA25X		1	/* This is an PXA255 CPU    */
#define CONFIG_XAENIAX		1	/* on a xaeniax board	    */
#define	CONFIG_SYS_TEXT_BASE	0x0

#define CONFIG_BOARD_LATE_INIT

/* we will never enable dcache, because we have to setup MMU first */
#define CONFIG_SYS_DCACHE_OFF

/*
 * select serial console configuration
 */
#define CONFIG_PXA_SERIAL
#define CONFIG_BTUART	       1       /* we use BTUART on XAENIAX */
#define CONFIG_CONS_INDEX	4

/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE

#define	CONFIG_TIMESTAMP		/* Print image info with timestamp */

#define CONFIG_BAUDRATE		115200

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_DHCP
#define CONFIG_CMD_DIAG
#define CONFIG_CMD_NFS
#define CONFIG_CMD_SDRAM
#define CONFIG_CMD_SNTP

#undef CONFIG_CMD_DTT


#define CONFIG_ETHADDR		08:00:3e:26:0a:5b
#define CONFIG_NETMASK		255.255.255.0
#define CONFIG_IPADDR		192.168.68.201
#define CONFIG_SERVERIP		192.168.68.62

#define CONFIG_BOOTDELAY	3
#define CONFIG_BOOTCOMMAND	"bootm 0x00100000"
#define CONFIG_BOOTARGS		"console=ttyS1,115200"
#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS	1
#define CONFIG_INITRD_TAG		1

#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE	115200			/* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX	1			/* which serial port to use */
#endif

/*
 * Size of malloc() pool; this lives below the uppermost 128 KiB which are
 * used for the RAM copy of the uboot code
 */
#define CONFIG_SYS_MALLOC_LEN	    (CONFIG_ENV_SIZE + 128*1024)

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP				/* undef to save memory	*/
#define CONFIG_SYS_HUSH_PARSER		1


#ifdef CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT		"u-boot$ "	/* Monitor Command Prompt */
#else
#define CONFIG_SYS_PROMPT		"u-boot=> "	/* Monitor Command Prompt */
#endif
#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
#define CONFIG_SYS_DEVICE_NULLDEV	1

#define CONFIG_SYS_MEMTEST_START	0xa0400000	/* memtest works on	*/
#define CONFIG_SYS_MEMTEST_END		0xa0800000	/* 4 ... 8 MB in DRAM	*/

#define CONFIG_SYS_LOAD_ADDR		0xa1000000	/* default load address */

#define CONFIG_SYS_HZ			1000
#define CONFIG_SYS_CPUSPEED		0x141		/* set core clock to 400/200/100 MHz */

/*
 * Physical Memory Map
 */
#define CONFIG_NR_DRAM_BANKS	1	   /* we have 1 banks (partition) of DRAM */
#define PHYS_SDRAM_1		0xa0000000 /* SDRAM Bank #1 */
#define PHYS_SDRAM_1_SIZE	0x04000000 /* 64 MB */
#define PHYS_SDRAM_2		0xa4000000 /* SDRAM Bank #2 */
#define PHYS_SDRAM_2_SIZE	0x00000000 /* 0 MB */
#define PHYS_SDRAM_3		0xa8000000 /* SDRAM Bank #3 */
#define PHYS_SDRAM_3_SIZE	0x00000000 /* 0 MB */
#define PHYS_SDRAM_4		0xac000000 /* SDRAM Bank #4 */
#define PHYS_SDRAM_4_SIZE	0x00000000 /* 0 MB */

#define PHYS_FLASH_1		0x00000000 /* Flash Bank #1 */
#define PHYS_FLASH_2		0x04000000 /* Flash Bank #2 */
#define PHYS_FLASH_SIZE		0x02000000 /* 32 MB */
#define PHYS_FLASH_BANK_SIZE	0x02000000 /* 32 MB Banks */
#define PHYS_FLASH_SECT_SIZE	0x00040000 /* 256 KB sectors (x2) */

#define CONFIG_SYS_DRAM_BASE		0xa0000000
#define CONFIG_SYS_DRAM_SIZE		0x04000000

#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1

#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
#define	CONFIG_SYS_INIT_SP_ADDR		0xfffff800

/*
 * FLASH and environment organization
 */
#define CONFIG_SYS_MAX_FLASH_BANKS	1    /* max number of memory banks		*/
#define CONFIG_SYS_MAX_FLASH_SECT	128  /* max number of sectors on one chip    */

/* timeout values are in ticks */
#define CONFIG_SYS_FLASH_ERASE_TOUT	(25*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
#define CONFIG_SYS_FLASH_WRITE_TOUT	(25*CONFIG_SYS_HZ) /* Timeout for Flash Write */

/* FIXME */
#define CONFIG_ENV_IS_IN_FLASH	1
#define CONFIG_ENV_ADDR		(PHYS_FLASH_1 + 0x40000)/* Addr of Environment Sector	*/
#define CONFIG_ENV_SIZE		0x40000			/* Total Size of Environment Sector	*/

/*
 * SMSC91C111 Network Card
 */
#define CONFIG_SMC91111		1
#define CONFIG_SMC91111_BASE		0x10000300  /* chip select 3         */
#define CONFIG_SMC_USE_32_BIT		1          /* 32 bit bus  */
#undef  CONFIG_SMC_91111_EXT_PHY		   /* we use internal phy   */
#undef  CONFIG_SHOW_ACTIVITY
#define CONFIG_NET_RETRY_COUNT		10	   /* # of retries          */

/*
 * GPIO settings
 */

/*
 * GP05 == nUSBReset  is 1
 * GP10 == CFReset   is 1
 * GP13 == nCFDataEnable is 1
 * GP14 == nCFAddrEnable is 1
 * GP15 == nCS1      is 1
 * GP21 == ComBrdReset is 1
 * GP24 == SFRM      is 1
 * GP25 == TXD       is 1
 * GP31 == SYNC      is 1
 * GP33 == nCS5      is 1
 * GP39 == FFTXD     is 1
 * GP41 == RTS       is 1
 * GP43 == BTTXD     is 1
 * GP45 == BTRTS     is 1
 * GP47 == TXD       is 1
 * GP48 == nPOE      is 1
 * GP49 == nPWE      is 1
 * GP50 == nPIOR     is 1
 * GP51 == nPIOW     is 1
 * GP52 == nPCE[1]   is 1
 * GP53 == nPCE[2]   is 1
 * GP54 == nPSKTSEL  is 1
 * GP55 == nPREG     is 1
 * GP78 == nCS2      is 1
 * GP79 == nCS3      is 1
 * GP80 == nCS4      is 1
 * GP82 == NSSPSFRM  is 1
 * GP83 == NSSPTXD   is 1
 */
#define CONFIG_SYS_GPSR0_VAL		0x8320E420
#define CONFIG_SYS_GPSR1_VAL		0x00FFAA82
#define CONFIG_SYS_GPSR2_VAL		0x000DC000

/*
 * GP03 == LANReset  is 0
 * GP06 == USBWakeUp  is 0
 * GP11 == USBControl is 0
 * GP12 == Buzzer     is 0
 * GP16 == PWM0       is 0
 * GP17 == PWM1       is 0
 * GP23 == SCLK      is 0
 * GP30 == SDATA_OUT is 0
 * GP81 == NSSPCLK   is 0
 */
#define CONFIG_SYS_GPCR0_VAL		0x40C31848
#define CONFIG_SYS_GPCR1_VAL		0x00000000
#define CONFIG_SYS_GPCR2_VAL		0x00020000

/*
 * GP00 == CPUWakeUpUSB is input
 * GP01 == GP reset is input
 * GP02 == LANInterrupt is input
 * GP03 == LANReset     is output
 * GP04 == USBInterrupt is input
 * GP05 == nUSBReset    is output
 * GP06 == USBWakeUp    is output
 * GP07 == CFReady/nBusy is input
 * GP08 == nCFCardDetect1 is input
 * GP09 == nCFCardDetect2 is input
 * GP10 == nCFReset   is output
 * GP11 == USBControl is output
 * GP12 == Buzzer     is output
 * GP13 == CFDataEnable is output
 * GP14 == CFAddressEnable is output
 * GP15 == nCS1      is output
 * GP16 == PWM0      is output
 * GP17 == PWM1      is output
 * GP18 == RDY       is input
 * GP19 == ReaderReady is input
 * GP20 == ReaderReset is input
 * GP21 == ComBrdReset is output
 * GP23 == SCLK      is output
 * GP24 == SFRM      is output
 * GP25 == TXD       is output
 * GP26 == RXD       is input
 * GP27 == EXTCLK    is input
 * GP28 == BITCLK    is output
 * GP29 == SDATA_IN0 is input
 * GP30 == SDATA_OUT is output
 * GP31 == SYNC      is output
 * GP32 == SYSSCLK   is output
 * GP33 == nCS5      is output
 * GP34 == FFRXD     is input
 * GP35 == CTS       is input
 * GP36 == DCD       is input
 * GP37 == DSR       is input
 * GP38 == RI        is input
 * GP39 == FFTXD     is output
 * GP40 == DTR       is output
 * GP41 == RTS       is output
 * GP42 == BTRXD     is input
 * GP43 == BTTXD     is output
 * GP44 == BTCTS     is input
 * GP45 == BTRTS     is output
 * GP46 == RXD       is input
 * GP47 == TXD       is output
 * GP48 == nPOE      is output
 * GP49 == nPWE      is output
 * GP50 == nPIOR     is output
 * GP51 == nPIOW     is output
 * GP52 == nPCE[1]   is output
 * GP53 == nPCE[2]   is output
 * GP54 == nPSKTSEL  is output
 * GP55 == nPREG     is output
 * GP56 == nPWAIT    is input
 * GP57 == nPIOS16   is input
 * GP58 == LDD[0]    is output
 * GP59 == LDD[1]    is output
 * GP60 == LDD[2]    is output
 * GP61 == LDD[3]    is output
 * GP62 == LDD[4]    is output
 * GP63 == LDD[5]    is output
 * GP64 == LDD[6]    is output
 * GP65 == LDD[7]    is output
 * GP66 == LDD[8]    is output
 * GP67 == LDD[9]    is output
 * GP68 == LDD[10]   is output
 * GP69 == LDD[11]   is output
 * GP70 == LDD[12]   is output
 * GP71 == LDD[13]   is output
 * GP72 == LDD[14]   is output
 * GP73 == LDD[15]   is output
 * GP74 == LCD_FCLK  is output
 * GP75 == LCD_LCLK  is output
 * GP76 == LCD_PCLK  is output
 * GP77 == LCD_ACBIAS is output
 * GP78 == nCS2      is output
 * GP79 == nCS3      is output
 * GP80 == nCS4      is output
 * GP81 == NSSPCLK   is output
 * GP82 == NSSPSFRM  is output
 * GP83 == NSSPTXD   is output
 * GP84 == NSSPRXD   is input
 */
#define CONFIG_SYS_GPDR0_VAL		0xD3E3FC68
#define CONFIG_SYS_GPDR1_VAL		0xFCFFAB83
#define CONFIG_SYS_GPDR2_VAL		0x000FFFFF

/*
 * GP01 == GP reset is AF01
 * GP15 == nCS1     is AF10
 * GP16 == PWM0     is AF10
 * GP17 == PWM1     is AF10
 * GP18 == RDY      is AF01
 * GP23 == SCLK     is AF10
 * GP24 == SFRM     is AF10
 * GP25 == TXD      is AF10
 * GP26 == RXD      is AF01
 * GP27 == EXTCLK   is AF01
 * GP28 == BITCLK   is AF01
 * GP29 == SDATA_IN0 is AF10
 * GP30 == SDATA_OUT is AF01
 * GP31 == SYNC     is AF01
 * GP32 == SYSCLK   is AF01
 * GP33 == nCS5  is AF10
 * GP34 == FFRXD is AF01
 * GP35 == CTS   is AF01
 * GP36 == DCD   is AF01
 * GP37 == DSR   is AF01
 * GP38 == RI    is AF01
 * GP39 == FFTXD is AF10
 * GP40 == DTR   is AF10
 * GP41 == RTS   is AF10
 * GP42 == BTRXD is AF01
 * GP43 == BTTXD is AF10
 * GP44 == BTCTS is AF01
 * GP45 == BTRTS is AF10
 * GP46 == RXD   is AF10
 * GP47 == TXD   is AF01
 * GP48 == nPOE  is AF10
 * GP49 == nPWE  is AF10
 * GP50 == nPIOR is AF10
 * GP51 == nPIOW is AF10
 * GP52 == nPCE[1] is AF10
 * GP53 == nPCE[2] is AF10
 * GP54 == nPSKTSEL is AF10
 * GP55 == nPREG   is AF10
 * GP56 == nPWAIT  is AF01
 * GP57 == nPIOS16 is AF01
 * GP58 == LDD[0]  is AF10
 * GP59 == LDD[1]  is AF10
 * GP60 == LDD[2]  is AF10
 * GP61 == LDD[3]  is AF10
 * GP62 == LDD[4]  is AF10
 * GP63 == LDD[5]  is AF10
 * GP64 == LDD[6]  is AF10
 * GP65 == LDD[7]  is AF10
 * GP66 == LDD[8]  is AF10
 * GP67 == LDD[9]  is AF10
 * GP68 == LDD[10] is AF10
 * GP69 == LDD[11] is AF10
 * GP70 == LDD[12] is AF10
 * GP71 == LDD[13] is AF10
 * GP72 == LDD[14] is AF10
 * GP73 == LDD[15] is AF10
 * GP74 == LCD_FCLK is AF10
 * GP75 == LCD_LCLK is AF10
 * GP76 == LCD_PCLK is AF10
 * GP77 == LCD_ACBIAS is AF10
 * GP78 == nCS2     is AF10
 * GP79 == nCS3     is AF10
 * GP80 == nCS4     is AF10
 * GP81 == NSSPCLK  is AF01
 * GP82 == NSSPSFRM is AF01
 * GP83 == NSSPTXD  is AF01
 * GP84 == NSSPRXD  is AF10
 */
#define CONFIG_SYS_GAFR0_L_VAL		0x80000004
#define CONFIG_SYS_GAFR0_U_VAL		0x595A801A
#define CONFIG_SYS_GAFR1_L_VAL		0x699A9559
#define CONFIG_SYS_GAFR1_U_VAL		0xAAA5AAAA
#define CONFIG_SYS_GAFR2_L_VAL		0xAAAAAAAA
#define CONFIG_SYS_GAFR2_U_VAL		0x00000256

/*
 * clock settings
 */
/* RDH = 1
 * PH  = 0
 * VFS = 0
 * BFS = 0
 * SSS = 0
 */
#define CONFIG_SYS_PSSR_VAL		0x00000030

#define CONFIG_SYS_CKEN			0x00000080  /*  */
#define CONFIG_SYS_ICMR			0x00000000  /* No interrupts enabled        */
#define	CONFIG_SYS_CCCR			CCCR_L27|CCCR_M2|CCCR_N10


/*
 * Memory settings
 *
 * This is the configuration for nCS0/1 -> flash banks
 * configuration for nCS1 :
 * [31]    0    -
 * [30:28] 000  -
 * [27:24] 0000 -
 * [23:20] 0000 -
 * [19]    0    -
 * [18:16] 000  -
 * configuration for nCS0:
 * [15]    0    - Slower Device
 * [14:12] 010  - CS deselect to CS time: 2*(2*MemClk) = 40 ns
 * [11:08] 0011 - Address to data valid in bursts: (3+1)*MemClk = 40 ns
 * [07:04] 1111 - " for first access: (23+2)*MemClk = 250 ns (fixme 12+2?)
 * [03]    0    - 32 Bit bus width
 * [02:00] 010  - burst OF 4 ROM or FLASH
*/
#define CONFIG_SYS_MSC0_VAL		0x000023D2

/* This is the configuration for nCS2/3 -> USB controller, LAN
 * configuration for nCS3: LAN
 * [31]    0    - Slower Device
 * [30:28] 001  - RRR3: CS deselect to CS time: 1*(2*MemClk) = 20 ns
 * [27:24] 0010 - RDN3: Address to data valid in bursts: (2+1)*MemClk = 30 ns
 * [23:20] 0010 - RDF3: Address for first access: (2+1)*MemClk = 30 ns
 * [19]    0    - 32 Bit bus width
 * [18:16] 100  - variable latency I/O
 * configuration for nCS2: USB
 * [15]    1    - Faster Device
 * [14:12] 010  - RRR2: CS deselect to CS time: 2*(2*MemClk) = 40 ns
 * [11:08] 0010 - RDN2: Address to data valid in bursts: (2+1)*MemClk = 30 ns
 * [07:04] 0110 - RDF2: Address for first access: (6+1)*MemClk = 70 ns
 * [03]    1    - 16 Bit bus width
 * [02:00] 100  - variable latency I/O
 */
#define CONFIG_SYS_MSC1_VAL		0x1224A26C

/* This is the configuration for nCS4/5 -> LAN
 * configuration for nCS5:
 * [31]    0    -
 * [30:28] 000  -
 * [27:24] 0000 -
 * [23:20] 0000 -
 * [19]    0    -
 * [18:16] 000  -
 * configuration for nCS4: LAN
 * [15]    1    - Faster Device
 * [14:12] 010  - RRR2: CS deselect to CS time: 2*(2*MemClk) = 40 ns
 * [11:08] 0010 - RDN2: Address to data valid in bursts: (2+1)*MemClk = 30 ns
 * [07:04] 0110 - RDF2: Address for first access: (6+1)*MemClk = 70 ns
 * [03]    0    - 32 Bit bus width
 * [02:00] 100  - variable latency I/O
 */
#define CONFIG_SYS_MSC2_VAL		0x00001224

/* MDCNFG: SDRAM Configuration Register
 *
 * [31:29]   000 - reserved
 * [28]      0	 - no SA1111 compatiblity mode
 * [27]      0   - latch return data with return clock
 * [26]      0   - alternate addressing for pair 2/3
 * [25:24]   00  - timings
 * [23]      0   - internal banks in lower partition 2/3 (not used)
 * [22:21]   00  - row address bits for partition 2/3 (not used)
 * [20:19]   00  - column address bits for partition 2/3 (not used)
 * [18]      0   - SDRAM partition 2/3 width is 32 bit
 * [17]      0   - SDRAM partition 3 disabled
 * [16]      0   - SDRAM partition 2 disabled
 * [15:13]   000 - reserved
 * [12]      0	 - no SA1111 compatiblity mode
 * [11]      1   - latch return data with return clock
 * [10]      0   - no alternate addressing for pair 0/1
 * [09:08]   10  - tRP=2*MemClk CL=2 tRCD=2*MemClk tRAS=5*MemClk tRC=8*MemClk
 * [7]       1   - 4 internal banks in lower partition pair
 * [06:05]   10  - 13 row address bits for partition 0/1
 * [04:03]   01  - 9 column address bits for partition 0/1
 * [02]      0   - SDRAM partition 0/1 width is 32 bit
 * [01]      0   - disable SDRAM partition 1
 * [00]      1   - enable  SDRAM partition 0
 */
/* use the configuration above but disable partition 0 */
#define CONFIG_SYS_MDCNFG_VAL		0x00000AC9

/* MDREFR: SDRAM Refresh Control Register
 *
 * [32:26] 0     - reserved
 * [25]    0     - K2FREE: not free running
 * [24]    0     - K1FREE: not free running
 * [23]    0     - K0FREE: not free running
 * [22]    0     - SLFRSH: self refresh disabled
 * [21]    0     - reserved
 * [20]    1     - APD: auto power down
 * [19]    0     - K2DB2: SDCLK2 is MemClk
 * [18]    0     - K2RUN: disable SDCLK2
 * [17]    0     - K1DB2: SDCLK1 is MemClk
 * [16]    1     - K1RUN: enable SDCLK1
 * [15]    1     - E1PIN: SDRAM clock enable
 * [14]    0     - K0DB2: SDCLK0 is MemClk
 * [13]    0     - K0RUN: disable SDCLK0
 * [12]    0     - E0PIN: disable SDCKE0
 * [11:00] 000000011000 - (64ms/8192)*MemClkFreq/32 = 24
 */
#define CONFIG_SYS_MDREFR_VAL		0x00138018 /* mh: was 0x00118018 */

/* MDMRS: Mode Register Set Configuration Register
 *
 * [31]      0       - reserved
 * [30:23]   00000000- MDMRS2: SDRAM2/3 MRS Value. (not used)
 * [22:20]   011     - MDCL2:  SDRAM2/3 Cas Latency.  (not used)
 * [19]      0       - MDADD2: SDRAM2/3 burst Type. Fixed to sequential.  (not used)
 * [18:16]   010     - MDBL2:  SDRAM2/3 burst Length. Fixed to 4.  (not used)
 * [15]      0       - reserved
 * [14:07]   00000000- MDMRS0: SDRAM0/1 MRS Value.
 * [06:04]   011     - MDCL0:  SDRAM0/1 Cas Latency.
 * [03]      0       - MDADD0: SDRAM0/1 burst Type. Fixed to sequential.
 * [02:00]   010     - MDBL0:  SDRAM0/1 burst Length. Fixed to 4.
 */
#define CONFIG_SYS_MDMRS_VAL		0x00320032

#define	CONFIG_SYS_FLYCNFG_VAL		0x00000000
#define	CONFIG_SYS_SXCNFG_VAL		0x00000000

/*
 * PCMCIA and CF Interfaces
 */
#define CONFIG_SYS_MECR_VAL		0x00000000
#define CONFIG_SYS_MCMEM0_VAL		0x00010504
#define CONFIG_SYS_MCMEM1_VAL		0x00010504
#define CONFIG_SYS_MCATT0_VAL		0x00010504
#define CONFIG_SYS_MCATT1_VAL		0x00010504
#define CONFIG_SYS_MCIO0_VAL		0x00004715
#define CONFIG_SYS_MCIO1_VAL		0x00004715


#endif	/* __CONFIG_H */
Commit	Line	Data
4ec3a7f0	1	/*
414eec35 WD	2	* (C) Copyright 2004-2005
	3	* Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
	4	*
4ec3a7f0 WD	5	* (C) Copyright 2004
	6	* Vincent Dubey, Xa SA, vincent.dubey@xa-ch.com
	7	*
	8	* (C) Copyright 2002
	9	* Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.ne
	10	*
	11	* (C) Copyright 2002
	12	* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
	13	* Marius Groeger <mgroeger@sysgo.de>
	14	*
	15	* Configuation settings for the xaeniax board.
	16	*
1a459660	17	* SPDX-License-Identifier: GPL-2.0+
4ec3a7f0 WD	18	*/
	19
	20	#ifndef __CONFIG_H
	21	#define __CONFIG_H
	22
4ec3a7f0 WD	23	/*
	24	* High Level Configuration Options
	25	* (easy to change)
	26	*/
abc20aba	27	#define CONFIG_CPU_PXA25X 1 /* This is an PXA255 CPU */
4ec3a7f0	28	#define CONFIG_XAENIAX 1 /* on a xaeniax board */
1123d412	29	#define CONFIG_SYS_TEXT_BASE 0x0
4ec3a7f0	30
9660e442	31	#define CONFIG_BOARD_LATE_INIT
4ec3a7f0	32
b3acb6cd	33	/* we will never enable dcache, because we have to setup MMU first */
e47f2db5	34	#define CONFIG_SYS_DCACHE_OFF
b3acb6cd	35
4ec3a7f0 WD	36	/*
	37	* select serial console configuration
	38	*/
379be585	39	#define CONFIG_PXA_SERIAL
4ec3a7f0	40	#define CONFIG_BTUART 1 /* we use BTUART on XAENIAX */
ce6971cd	41	#define CONFIG_CONS_INDEX 4
4ec3a7f0 WD	42
	43	/* allow to overwrite serial and ethaddr */
	44	#define CONFIG_ENV_OVERWRITE
	45
414eec35 WD	46	#define CONFIG_TIMESTAMP /* Print image info with timestamp */
414eec35 WD	47
4ec3a7f0 WD	48	#define CONFIG_BAUDRATE 115200
4ec3a7f0 WD	49
079a136c JL	50	/*
	51	* BOOTP options
	52	*/
	53	#define CONFIG_BOOTP_BOOTFILESIZE
	54	#define CONFIG_BOOTP_BOOTPATH
	55	#define CONFIG_BOOTP_GATEWAY
	56	#define CONFIG_BOOTP_HOSTNAME
	57
	58
dca3b3d6 JL	59	/*
	60	* Command line configuration.
	61	*/
	62	#include <config_cmd_default.h>
	63
	64	#define CONFIG_CMD_DHCP
	65	#define CONFIG_CMD_DIAG
	66	#define CONFIG_CMD_NFS
	67	#define CONFIG_CMD_SDRAM
	68	#define CONFIG_CMD_SNTP
	69
	70	#undef CONFIG_CMD_DTT
	71
4ec3a7f0 WD	72
	73	#define CONFIG_ETHADDR 08:00:3e:26:0a:5b
	74	#define CONFIG_NETMASK 255.255.255.0
	75	#define CONFIG_IPADDR 192.168.68.201
	76	#define CONFIG_SERVERIP 192.168.68.62
	77
	78	#define CONFIG_BOOTDELAY 3
	79	#define CONFIG_BOOTCOMMAND "bootm 0x00100000"
	80	#define CONFIG_BOOTARGS "console=ttyS1,115200"
14699a22	81	#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
53677ef1	82	#define CONFIG_SETUP_MEMORY_TAGS 1
14699a22	83	#define CONFIG_INITRD_TAG 1
4ec3a7f0	84
dca3b3d6	85	#if defined(CONFIG_CMD_KGDB)
4ec3a7f0 WD	86	#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
	87	#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */
	88	#endif
	89
	90	/*
	91	* Size of malloc() pool; this lives below the uppermost 128 KiB which are
	92	* used for the RAM copy of the uboot code
	93	*/
6d0f6bcf	94	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
4ec3a7f0 WD	95
	96	/*
	97	* Miscellaneous configurable options
	98	*/
6d0f6bcf JCPV	99	#define CONFIG_SYS_LONGHELP /* undef to save memory */
6d0f6bcf JCPV	100	#define CONFIG_SYS_HUSH_PARSER 1
4ec3a7f0	101
4ec3a7f0	102
6d0f6bcf JCPV	103	#ifdef CONFIG_SYS_HUSH_PARSER
6d0f6bcf JCPV	104	#define CONFIG_SYS_PROMPT "u-boot$ " /* Monitor Command Prompt */
4ec3a7f0	105	#else
6d0f6bcf	106	#define CONFIG_SYS_PROMPT "u-boot=> " /* Monitor Command Prompt */
4ec3a7f0	107	#endif
6d0f6bcf JCPV	108	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
	109	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	110	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	111	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
	112	#define CONFIG_SYS_DEVICE_NULLDEV 1
4ec3a7f0	113
6d0f6bcf JCPV	114	#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */
6d0f6bcf JCPV	115	#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
4ec3a7f0	116
6d0f6bcf	117	#define CONFIG_SYS_LOAD_ADDR 0xa1000000 /* default load address */
4ec3a7f0	118
94a33129	119	#define CONFIG_SYS_HZ 1000
6d0f6bcf	120	#define CONFIG_SYS_CPUSPEED 0x141 /* set core clock to 400/200/100 MHz */
4ec3a7f0 WD	121
	122	/*
	123	* Physical Memory Map
	124	*/
	125	#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 banks (partition) of DRAM */
	126	#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
	127	#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
	128	#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */
	129	#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */
	130	#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */
	131	#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */
	132	#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */
	133	#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */
	134
	135	#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
	136	#define PHYS_FLASH_2 0x04000000 /* Flash Bank #2 */
	137	#define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */
	138	#define PHYS_FLASH_BANK_SIZE 0x02000000 /* 32 MB Banks */
	139	#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */
	140
6d0f6bcf JCPV	141	#define CONFIG_SYS_DRAM_BASE 0xa0000000
6d0f6bcf JCPV	142	#define CONFIG_SYS_DRAM_SIZE 0x04000000
4ec3a7f0	143
6d0f6bcf	144	#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
4ec3a7f0	145
6ef6eb91	146	#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
00d5ec93	147	#define CONFIG_SYS_INIT_SP_ADDR 0xfffff800
6ef6eb91	148
4ec3a7f0 WD	149	/*
	150	* FLASH and environment organization
	151	*/
6d0f6bcf JCPV	152	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
6d0f6bcf JCPV	153	#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
4ec3a7f0 WD	154
4ec3a7f0 WD	155	/* timeout values are in ticks */
6d0f6bcf JCPV	156	#define CONFIG_SYS_FLASH_ERASE_TOUT (25CONFIG_SYS_HZ) / Timeout for Flash Erase */
6d0f6bcf JCPV	157	#define CONFIG_SYS_FLASH_WRITE_TOUT (25CONFIG_SYS_HZ) / Timeout for Flash Write */
4ec3a7f0 WD	158
4ec3a7f0 WD	159	/* FIXME */
5a1aceb0	160	#define CONFIG_ENV_IS_IN_FLASH 1
0e8d1586 JCPV	161	#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x40000)/* Addr of Environment Sector */
0e8d1586 JCPV	162	#define CONFIG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */
4ec3a7f0	163
4ec3a7f0 WD	164	/*
	165	* SMSC91C111 Network Card
	166	*/
7194ab80	167	#define CONFIG_SMC91111 1
1f6d4258	168	#define CONFIG_SMC91111_BASE 0x10000300 /* chip select 3 */
4ec3a7f0 WD	169	#define CONFIG_SMC_USE_32_BIT 1 /* 32 bit bus */
	170	#undef CONFIG_SMC_91111_EXT_PHY /* we use internal phy */
	171	#undef CONFIG_SHOW_ACTIVITY
	172	#define CONFIG_NET_RETRY_COUNT 10 /* # of retries */
	173
	174	/*
	175	* GPIO settings
	176	*/
	177
	178	/*
	179	* GP05 == nUSBReset is 1
	180	* GP10 == CFReset is 1
	181	* GP13 == nCFDataEnable is 1
	182	* GP14 == nCFAddrEnable is 1
	183	* GP15 == nCS1 is 1
	184	* GP21 == ComBrdReset is 1
	185	* GP24 == SFRM is 1
	186	* GP25 == TXD is 1
	187	* GP31 == SYNC is 1
	188	* GP33 == nCS5 is 1
	189	* GP39 == FFTXD is 1
	190	* GP41 == RTS is 1
	191	* GP43 == BTTXD is 1
	192	* GP45 == BTRTS is 1
	193	* GP47 == TXD is 1
	194	* GP48 == nPOE is 1
	195	* GP49 == nPWE is 1
	196	* GP50 == nPIOR is 1
	197	* GP51 == nPIOW is 1
	198	* GP52 == nPCE[1] is 1
	199	* GP53 == nPCE[2] is 1
	200	* GP54 == nPSKTSEL is 1
	201	* GP55 == nPREG is 1
	202	* GP78 == nCS2 is 1
	203	* GP79 == nCS3 is 1
	204	* GP80 == nCS4 is 1
	205	* GP82 == NSSPSFRM is 1
	206	* GP83 == NSSPTXD is 1
	207	*/
6d0f6bcf JCPV	208	#define CONFIG_SYS_GPSR0_VAL 0x8320E420
	209	#define CONFIG_SYS_GPSR1_VAL 0x00FFAA82
	210	#define CONFIG_SYS_GPSR2_VAL 0x000DC000
4ec3a7f0 WD	211
	212	/*
	213	* GP03 == LANReset is 0
	214	* GP06 == USBWakeUp is 0
	215	* GP11 == USBControl is 0
	216	* GP12 == Buzzer is 0
	217	* GP16 == PWM0 is 0
	218	* GP17 == PWM1 is 0
	219	* GP23 == SCLK is 0
	220	* GP30 == SDATA_OUT is 0
	221	* GP81 == NSSPCLK is 0
	222	*/
6d0f6bcf JCPV	223	#define CONFIG_SYS_GPCR0_VAL 0x40C31848
	224	#define CONFIG_SYS_GPCR1_VAL 0x00000000
	225	#define CONFIG_SYS_GPCR2_VAL 0x00020000
4ec3a7f0 WD	226
	227	/*
	228	* GP00 == CPUWakeUpUSB is input
	229	* GP01 == GP reset is input
	230	* GP02 == LANInterrupt is input
	231	* GP03 == LANReset is output
	232	* GP04 == USBInterrupt is input
	233	* GP05 == nUSBReset is output
	234	* GP06 == USBWakeUp is output
	235	* GP07 == CFReady/nBusy is input
	236	* GP08 == nCFCardDetect1 is input
	237	* GP09 == nCFCardDetect2 is input
	238	* GP10 == nCFReset is output
	239	* GP11 == USBControl is output
	240	* GP12 == Buzzer is output
	241	* GP13 == CFDataEnable is output
	242	* GP14 == CFAddressEnable is output
	243	* GP15 == nCS1 is output
	244	* GP16 == PWM0 is output
	245	* GP17 == PWM1 is output
	246	* GP18 == RDY is input
	247	* GP19 == ReaderReady is input
	248	* GP20 == ReaderReset is input
	249	* GP21 == ComBrdReset is output
	250	* GP23 == SCLK is output
	251	* GP24 == SFRM is output
	252	* GP25 == TXD is output
	253	* GP26 == RXD is input
	254	* GP27 == EXTCLK is input
	255	* GP28 == BITCLK is output
	256	* GP29 == SDATA_IN0 is input
	257	* GP30 == SDATA_OUT is output
	258	* GP31 == SYNC is output
	259	* GP32 == SYSSCLK is output
	260	* GP33 == nCS5 is output
	261	* GP34 == FFRXD is input
	262	* GP35 == CTS is input
	263	* GP36 == DCD is input
	264	* GP37 == DSR is input
	265	* GP38 == RI is input
	266	* GP39 == FFTXD is output
	267	* GP40 == DTR is output
	268	* GP41 == RTS is output
	269	* GP42 == BTRXD is input
	270	* GP43 == BTTXD is output
	271	* GP44 == BTCTS is input
	272	* GP45 == BTRTS is output
	273	* GP46 == RXD is input
	274	* GP47 == TXD is output
	275	* GP48 == nPOE is output
	276	* GP49 == nPWE is output
	277	* GP50 == nPIOR is output
	278	* GP51 == nPIOW is output
	279	* GP52 == nPCE[1] is output
	280	* GP53 == nPCE[2] is output
	281	* GP54 == nPSKTSEL is output
	282	* GP55 == nPREG is output
	283	* GP56 == nPWAIT is input
	284	* GP57 == nPIOS16 is input
	285	* GP58 == LDD[0] is output
	286	* GP59 == LDD[1] is output
	287	* GP60 == LDD[2] is output
	288	* GP61 == LDD[3] is output
	289	* GP62 == LDD[4] is output
290	* GP63 == LDD[5] is output
291	* GP64 == LDD[6] is output
292	* GP65 == LDD[7] is output
293	* GP66 == LDD[8] is output
294	* GP67 == LDD[9] is output
295	* GP68 == LDD[10] is output
296	* GP69 == LDD[11] is output
297	* GP70 == LDD[12] is output
298	* GP71 == LDD[13] is output
299	* GP72 == LDD[14] is output
300	* GP73 == LDD[15] is output
301	* GP74 == LCD_FCLK is output
302	* GP75 == LCD_LCLK is output
303	* GP76 == LCD_PCLK is output
304	* GP77 == LCD_ACBIAS is output
305	* GP78 == nCS2 is output
306	* GP79 == nCS3 is output
307	* GP80 == nCS4 is output
308	* GP81 == NSSPCLK is output
309	* GP82 == NSSPSFRM is output
310	* GP83 == NSSPTXD is output
311	* GP84 == NSSPRXD is input
312	*/
6d0f6bcf JCPV	313	#define CONFIG_SYS_GPDR0_VAL 0xD3E3FC68
	314	#define CONFIG_SYS_GPDR1_VAL 0xFCFFAB83
	315	#define CONFIG_SYS_GPDR2_VAL 0x000FFFFF
4ec3a7f0 WD	316
	317	/*
	318	* GP01 == GP reset is AF01
	319	* GP15 == nCS1 is AF10
	320	* GP16 == PWM0 is AF10
	321	* GP17 == PWM1 is AF10
	322	* GP18 == RDY is AF01
	323	* GP23 == SCLK is AF10
	324	* GP24 == SFRM is AF10
	325	* GP25 == TXD is AF10
	326	* GP26 == RXD is AF01
	327	* GP27 == EXTCLK is AF01
	328	* GP28 == BITCLK is AF01
	329	* GP29 == SDATA_IN0 is AF10
	330	* GP30 == SDATA_OUT is AF01
	331	* GP31 == SYNC is AF01
	332	* GP32 == SYSCLK is AF01
	333	* GP33 == nCS5 is AF10
	334	* GP34 == FFRXD is AF01
	335	* GP35 == CTS is AF01
	336	* GP36 == DCD is AF01
	337	* GP37 == DSR is AF01
	338	* GP38 == RI is AF01
	339	* GP39 == FFTXD is AF10
	340	* GP40 == DTR is AF10
	341	* GP41 == RTS is AF10
	342	* GP42 == BTRXD is AF01
	343	* GP43 == BTTXD is AF10
	344	* GP44 == BTCTS is AF01
	345	* GP45 == BTRTS is AF10
	346	* GP46 == RXD is AF10
	347	* GP47 == TXD is AF01
	348	* GP48 == nPOE is AF10
	349	* GP49 == nPWE is AF10
	350	* GP50 == nPIOR is AF10
	351	* GP51 == nPIOW is AF10
	352	* GP52 == nPCE[1] is AF10
	353	* GP53 == nPCE[2] is AF10
	354	* GP54 == nPSKTSEL is AF10
	355	* GP55 == nPREG is AF10
	356	* GP56 == nPWAIT is AF01
	357	* GP57 == nPIOS16 is AF01
	358	* GP58 == LDD[0] is AF10
	359	* GP59 == LDD[1] is AF10
	360	* GP60 == LDD[2] is AF10
	361	* GP61 == LDD[3] is AF10
	362	* GP62 == LDD[4] is AF10
	363	* GP63 == LDD[5] is AF10
	364	* GP64 == LDD[6] is AF10
	365	* GP65 == LDD[7] is AF10
	366	* GP66 == LDD[8] is AF10
	367	* GP67 == LDD[9] is AF10
	368	* GP68 == LDD[10] is AF10
	369	* GP69 == LDD[11] is AF10
	370	* GP70 == LDD[12] is AF10
	371	* GP71 == LDD[13] is AF10
	372	* GP72 == LDD[14] is AF10
	373	* GP73 == LDD[15] is AF10
	374	* GP74 == LCD_FCLK is AF10
	375	* GP75 == LCD_LCLK is AF10
	376	* GP76 == LCD_PCLK is AF10
	377	* GP77 == LCD_ACBIAS is AF10
	378	* GP78 == nCS2 is AF10
	379	* GP79 == nCS3 is AF10
380	* GP80 == nCS4 is AF10
381	* GP81 == NSSPCLK is AF01
382	* GP82 == NSSPSFRM is AF01
383	* GP83 == NSSPTXD is AF01
384	* GP84 == NSSPRXD is AF10
385	*/
6d0f6bcf JCPV	386	#define CONFIG_SYS_GAFR0_L_VAL 0x80000004
	387	#define CONFIG_SYS_GAFR0_U_VAL 0x595A801A
	388	#define CONFIG_SYS_GAFR1_L_VAL 0x699A9559
	389	#define CONFIG_SYS_GAFR1_U_VAL 0xAAA5AAAA
	390	#define CONFIG_SYS_GAFR2_L_VAL 0xAAAAAAAA
	391	#define CONFIG_SYS_GAFR2_U_VAL 0x00000256
4ec3a7f0 WD	392
	393	/*
	394	* clock settings
	395	*/
	396	/* RDH = 1
	397	* PH = 0
	398	* VFS = 0
	399	* BFS = 0
	400	* SSS = 0
	401	*/
6d0f6bcf	402	#define CONFIG_SYS_PSSR_VAL 0x00000030
4ec3a7f0	403
1123d412 MV	404	#define CONFIG_SYS_CKEN 0x00000080 /* */
	405	#define CONFIG_SYS_ICMR 0x00000000 /* No interrupts enabled */
	406	#define CONFIG_SYS_CCCR CCCR_L27\|CCCR_M2\|CCCR_N10
4ec3a7f0 WD	407
	408
	409	/*
	410	* Memory settings
	411	*
	412	* This is the configuration for nCS0/1 -> flash banks
	413	* configuration for nCS1 :
	414	* [31] 0 -
	415	* [30:28] 000 -
	416	* [27:24] 0000 -
	417	* [23:20] 0000 -
	418	* [19] 0 -
	419	* [18:16] 000 -
	420	* configuration for nCS0:
	421	* [15] 0 - Slower Device
	422	* [14:12] 010 - CS deselect to CS time: 2(2MemClk) = 40 ns
	423	* [11:08] 0011 - Address to data valid in bursts: (3+1)*MemClk = 40 ns
	424	* [07:04] 1111 - " for first access: (23+2)*MemClk = 250 ns (fixme 12+2?)
	425	* [03] 0 - 32 Bit bus width
	426	* [02:00] 010 - burst OF 4 ROM or FLASH
	427	*/
6d0f6bcf	428	#define CONFIG_SYS_MSC0_VAL 0x000023D2
4ec3a7f0 WD	429
	430	/* This is the configuration for nCS2/3 -> USB controller, LAN
	431	* configuration for nCS3: LAN
	432	* [31] 0 - Slower Device
	433	* [30:28] 001 - RRR3: CS deselect to CS time: 1(2MemClk) = 20 ns
	434	* [27:24] 0010 - RDN3: Address to data valid in bursts: (2+1)*MemClk = 30 ns
	435	* [23:20] 0010 - RDF3: Address for first access: (2+1)*MemClk = 30 ns
	436	* [19] 0 - 32 Bit bus width
	437	* [18:16] 100 - variable latency I/O
	438	* configuration for nCS2: USB
	439	* [15] 1 - Faster Device
	440	* [14:12] 010 - RRR2: CS deselect to CS time: 2(2MemClk) = 40 ns
	441	* [11:08] 0010 - RDN2: Address to data valid in bursts: (2+1)*MemClk = 30 ns
	442	* [07:04] 0110 - RDF2: Address for first access: (6+1)*MemClk = 70 ns
452f6740	443	* [03] 1 - 16 Bit bus width
4ec3a7f0 WD	444	* [02:00] 100 - variable latency I/O
4ec3a7f0 WD	445	*/
6d0f6bcf	446	#define CONFIG_SYS_MSC1_VAL 0x1224A26C
4ec3a7f0 WD	447
	448	/* This is the configuration for nCS4/5 -> LAN
	449	* configuration for nCS5:
	450	* [31] 0 -
	451	* [30:28] 000 -
	452	* [27:24] 0000 -
	453	* [23:20] 0000 -
	454	* [19] 0 -
	455	* [18:16] 000 -
	456	* configuration for nCS4: LAN
	457	* [15] 1 - Faster Device
	458	* [14:12] 010 - RRR2: CS deselect to CS time: 2(2MemClk) = 40 ns
	459	* [11:08] 0010 - RDN2: Address to data valid in bursts: (2+1)*MemClk = 30 ns
	460	* [07:04] 0110 - RDF2: Address for first access: (6+1)*MemClk = 70 ns
	461	* [03] 0 - 32 Bit bus width
	462	* [02:00] 100 - variable latency I/O
	463	*/
6d0f6bcf	464	#define CONFIG_SYS_MSC2_VAL 0x00001224
4ec3a7f0 WD	465
	466	/* MDCNFG: SDRAM Configuration Register
	467	*
	468	* [31:29] 000 - reserved
	469	* [28] 0 - no SA1111 compatiblity mode
	470	* [27] 0 - latch return data with return clock
	471	* [26] 0 - alternate addressing for pair 2/3
	472	* [25:24] 00 - timings
	473	* [23] 0 - internal banks in lower partition 2/3 (not used)
	474	* [22:21] 00 - row address bits for partition 2/3 (not used)
	475	* [20:19] 00 - column address bits for partition 2/3 (not used)
	476	* [18] 0 - SDRAM partition 2/3 width is 32 bit
	477	* [17] 0 - SDRAM partition 3 disabled
	478	* [16] 0 - SDRAM partition 2 disabled
	479	* [15:13] 000 - reserved
	480	* [12] 0 - no SA1111 compatiblity mode
	481	* [11] 1 - latch return data with return clock
	482	* [10] 0 - no alternate addressing for pair 0/1
	483	* [09:08] 10 - tRP=2MemClk CL=2 tRCD=2MemClk tRAS=5MemClk tRC=8MemClk
	484	* [7] 1 - 4 internal banks in lower partition pair
	485	* [06:05] 10 - 13 row address bits for partition 0/1
	486	* [04:03] 01 - 9 column address bits for partition 0/1
	487	* [02] 0 - SDRAM partition 0/1 width is 32 bit
	488	* [01] 0 - disable SDRAM partition 1
	489	* [00] 1 - enable SDRAM partition 0
	490	*/
	491	/* use the configuration above but disable partition 0 */
6d0f6bcf	492	#define CONFIG_SYS_MDCNFG_VAL 0x00000AC9
4ec3a7f0 WD	493
	494	/* MDREFR: SDRAM Refresh Control Register
	495	*
	496	* [32:26] 0 - reserved
	497	* [25] 0 - K2FREE: not free running
	498	* [24] 0 - K1FREE: not free running
	499	* [23] 0 - K0FREE: not free running
	500	* [22] 0 - SLFRSH: self refresh disabled
	501	* [21] 0 - reserved
	502	* [20] 1 - APD: auto power down
	503	* [19] 0 - K2DB2: SDCLK2 is MemClk
	504	* [18] 0 - K2RUN: disable SDCLK2
	505	* [17] 0 - K1DB2: SDCLK1 is MemClk
	506	* [16] 1 - K1RUN: enable SDCLK1
	507	* [15] 1 - E1PIN: SDRAM clock enable
	508	* [14] 0 - K0DB2: SDCLK0 is MemClk
	509	* [13] 0 - K0RUN: disable SDCLK0
	510	* [12] 0 - E0PIN: disable SDCKE0
	511	* [11:00] 000000011000 - (64ms/8192)*MemClkFreq/32 = 24
	512	*/
6d0f6bcf	513	#define CONFIG_SYS_MDREFR_VAL 0x00138018 /* mh: was 0x00118018 */
4ec3a7f0 WD	514
	515	/* MDMRS: Mode Register Set Configuration Register
	516	*
	517	* [31] 0 - reserved
	518	* [30:23] 00000000- MDMRS2: SDRAM2/3 MRS Value. (not used)
	519	* [22:20] 011 - MDCL2: SDRAM2/3 Cas Latency. (not used)
	520	* [19] 0 - MDADD2: SDRAM2/3 burst Type. Fixed to sequential. (not used)
	521	* [18:16] 010 - MDBL2: SDRAM2/3 burst Length. Fixed to 4. (not used)
	522	* [15] 0 - reserved
	523	* [14:07] 00000000- MDMRS0: SDRAM0/1 MRS Value.
	524	* [06:04] 011 - MDCL0: SDRAM0/1 Cas Latency.
	525	* [03] 0 - MDADD0: SDRAM0/1 burst Type. Fixed to sequential.
	526	* [02:00] 010 - MDBL0: SDRAM0/1 burst Length. Fixed to 4.
	527	*/
6d0f6bcf	528	#define CONFIG_SYS_MDMRS_VAL 0x00320032
4ec3a7f0	529
1123d412 MV	530	#define CONFIG_SYS_FLYCNFG_VAL 0x00000000
	531	#define CONFIG_SYS_SXCNFG_VAL 0x00000000
	532
4ec3a7f0 WD	533	/*
	534	* PCMCIA and CF Interfaces
	535	*/
6d0f6bcf JCPV	536	#define CONFIG_SYS_MECR_VAL 0x00000000
	537	#define CONFIG_SYS_MCMEM0_VAL 0x00010504
	538	#define CONFIG_SYS_MCMEM1_VAL 0x00010504
	539	#define CONFIG_SYS_MCATT0_VAL 0x00010504
	540	#define CONFIG_SYS_MCATT1_VAL 0x00010504
	541	#define CONFIG_SYS_MCIO0_VAL 0x00004715
	542	#define CONFIG_SYS_MCIO1_VAL 0x00004715
4ec3a7f0 WD	543
	544
	545	#endif /* __CONFIG_H */