[people/ms/u-boot.git] / include / configs / xpedite1000.h

/*
 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*
 * config for XPedite1000 from XES Inc.
 * Ported from EBONY config by Travis B. Sawyer <tsawyer@sandburst.com>
 * (C) Copyright 2003 Sandburst Corporation
 * board/config_EBONY.h - configuration for AMCC 440GP Ref (Ebony)
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/* High Level Configuration Options */
#define CONFIG_XPEDITE1000	1
#define CONFIG_SYS_BOARD_NAME	"XPedite1000"
#define CONFIG_SYS_FORM_PMC	1
#define CONFIG_440		1
#define CONFIG_440GX		1		/* 440 GX */
#define CONFIG_BOARD_EARLY_INIT_F 1		/* Call board_pre_init	*/
#define CONFIG_SYS_CLK_FREQ	33333333	/* external freq to pll */

#define	CONFIG_SYS_TEXT_BASE	0xFFF80000

/*
 * DDR config
 */
#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for setup */
#define SPD_EEPROM_ADDRESS	{0x54}	/* SPD i2c spd addresses */
#define CONFIG_VERY_BIG_RAM	1

/*
 * Base addresses -- Note these are effective addresses where the
 * actual resources get mapped (not physical addresses)
 */
#define CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_FLASH_BASE		0xff000000	/* start of FLASH */
#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE	/* start of monitor */
#define CONFIG_SYS_PCI_MEMBASE		0x80000000	/* mapped pci memory */
#define CONFIG_SYS_ISRAM_BASE		0xc0000000	/* internal SRAM */
#define CONFIG_SYS_PCI_BASE		0xd0000000	/* internal PCI regs */
#define CONFIG_SYS_NVRAM_BASE_ADDR	(CONFIG_SYS_PERIPHERAL_BASE + 0x08000000)
#define CONFIG_SYS_GPIO_BASE		(CONFIG_SYS_PERIPHERAL_BASE + 0x00000700)

/*
 * Diagnostics
 */
#define CONFIG_SYS_ALT_MEMTEST
#define CONFIG_SYS_MEMTEST_START	0x0400000
#define CONFIG_SYS_MEMTEST_END		0x0C00000

/* POST support */
#define CONFIG_POST		(CONFIG_SYS_POST_RTC	| \
				 CONFIG_SYS_POST_I2C)

/*
 * LED support
 */
#define USR_LED0	0x00000080
#define USR_LED1	0x00000100
#define USR_LED2	0x00000200
#define USR_LED3	0x00000400

#ifndef __ASSEMBLY__
extern unsigned long in32(unsigned int);
extern void out32(unsigned int, unsigned long);

#define LED0_ON() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) & ~USR_LED0))
#define LED1_ON() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) & ~USR_LED1))
#define LED2_ON() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) & ~USR_LED2))
#define LED3_ON() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) & ~USR_LED3))

#define LED0_OFF() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) | USR_LED0))
#define LED1_OFF() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) | USR_LED1))
#define LED2_OFF() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) | USR_LED2))
#define LED3_OFF() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) | USR_LED3))
#endif

/*
 * Use internal SRAM for initial stack
 */
#define CONFIG_SYS_TEMP_STACK_OCM	1
#define CONFIG_SYS_OCM_DATA_ADDR	CONFIG_SYS_ISRAM_BASE
#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_ISRAM_BASE	/* Initial RAM address */
#define CONFIG_SYS_INIT_RAM_SIZE		0x2000	/* Size of used area in RAM */
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_GBL_DATA_OFFSET - 0x4)

#define CONFIG_SYS_MONITOR_LEN	(512 * 1024)	/* Reserve 512 KB for Mon */
#define CONFIG_SYS_MALLOC_LEN	(1024 * 1024)	/* Reserved for malloc */

/*
 * Serial Port
 */
#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#define CONFIG_SYS_NS16550_CLK		get_serial_clock()

#define CONFIG_SYS_BAUDRATE_TABLE \
	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400}
#define CONFIG_BAUDRATE			115200
#define CONFIG_LOADS_ECHO		1	/* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */

/*
 * NOR flash configuration
 */
#define CONFIG_SYS_MAX_FLASH_BANKS	3
#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE, 0xf0000000, 0xf4000000 }
#define CONFIG_SYS_MAX_FLASH_SECT	512	/* sectors per device */
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
#define CONFIG_SYS_FLASH_QUIET_TEST		/* MirrorBit flashes are optional */
#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms) */

/*
 * I2C
 */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_PPC4XX
#define CONFIG_SYS_I2C_PPC4XX_CH0
#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		400000
#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0		0x7f

/* I2C EEPROM */
#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10

/* I2C RTC: STMicro M41T00 */
#define CONFIG_RTC_M41T11		1
#define CONFIG_SYS_I2C_RTC_ADDR		0x68
#define CONFIG_SYS_M41T11_BASE_YEAR	2000

/*
 * PCI
 */
/* General PCI */
#define CONFIG_PCI				/* include pci support */
#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
#define CONFIG_PCI_PNP				/* do pci plug-and-play */
#define CONFIG_PCI_SCAN_SHOW			/* show pci devices on startup */
#define CONFIG_SYS_PCI_TARGBASE	0x80000000	/* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE */

/* Board-specific PCI */
#define CONFIG_SYS_PCI_TARGET_INIT		/* let board init pci target */
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014	/* IBM */
#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe	/* Whatever */
#define CONFIG_SYS_PCI_FORCE_PCI_CONV		/* Force PCI Conventional Mode */

/*
 * Networking options
 */
#define CONFIG_PPC4xx_EMAC
#define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
#define CONFIG_MII		1	/* MII PHY management */
#define CONFIG_PHY_RESET	1	/* reset phy upon startup */
#define CONFIG_SYS_RX_ETH_BUFFER 32	/* Number of ethernet rx buffers & descriptors */
#define CONFIG_ETHPRIME		"ppc_4xx_eth2"
#define CONFIG_PHY_ADDR		4	/* PHY address phy0 not populated */
#define CONFIG_PHY2_ADDR	4	/* PHY address phy2 */
#define CONFIG_HAS_ETH2		1	/* add support for "eth2addr" */
#define CONFIG_PHY3_ADDR	8	/* PHY address phy3 */
#define CONFIG_HAS_ETH3		1	/* add support for "eth3addr" */

/* BOOTP options */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME

/*
 * Command configuration
 */
#define CONFIG_CMD_DATE
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_PCI

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP			/* undef to save memory */
#define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
#define CONFIG_CMDLINE_EDITING	1		/* Command-line editing */
#define CONFIG_PANIC_HANG			/* do not reset board on panic */
#define CONFIG_PREBOOT				/* enable preboot variable */
#define CONFIG_INTEGRITY			/* support booting INTEGRITY OS */
#define CONFIG_SYS_EXTBDINFO	1		/* To use extended board_into (bd_t) */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */

/*
 * Environment Configuration
 */
#define CONFIG_ENV_IS_IN_FLASH	1
#define CONFIG_ENV_SECT_SIZE	0x20000 /* 128k (one sector) for env */
#define CONFIG_ENV_SIZE		0x8000
#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - (256 * 1024))

/*
 * Flash memory map:
 * fff80000 - ffffffff	U-Boot (512 KB)
 * fff40000 - fff7ffff	U-Boot Environment (256 KB)
 * fff00000 - fff3ffff	FDT (256KB)
 * ffc00000 - ffefffff	OS image (3MB)
 * ff000000 - ffbfffff	OS Use/Filesystem (12MB)
 */

#define CONFIG_UBOOT_ENV_ADDR	__stringify(CONFIG_SYS_TEXT_BASE)
#define CONFIG_FDT_ENV_ADDR	__stringify(0xfff00000)
#define CONFIG_OS_ENV_ADDR	__stringify(0xffc00000)

#define CONFIG_PROG_UBOOT						\
	"$download_cmd $loadaddr $ubootfile; "				\
	"if test $? -eq 0; then "					\
		"protect off "CONFIG_UBOOT_ENV_ADDR" +80000; "		\
		"erase "CONFIG_UBOOT_ENV_ADDR" +80000; "		\
		"cp.w $loadaddr "CONFIG_UBOOT_ENV_ADDR" 40000; "	\
		"protect on "CONFIG_UBOOT_ENV_ADDR" +80000; "		\
		"cmp.b $loadaddr "CONFIG_UBOOT_ENV_ADDR" 80000; "	\
		"if test $? -ne 0; then "				\
			"echo PROGRAM FAILED; "				\
		"else; "						\
			"echo PROGRAM SUCCEEDED; "			\
		"fi; "							\
	"else; "							\
		"echo DOWNLOAD FAILED; "				\
	"fi;"

#define CONFIG_BOOT_OS_NET						\
	"$download_cmd $osaddr $osfile; "				\
	"if test $? -eq 0; then "					\
		"if test -n $fdtaddr; then "				\
			"$download_cmd $fdtaddr $fdtfile; "		\
			"if test $? -eq 0; then "			\
				"bootm $osaddr - $fdtaddr; "		\
			"else; "					\
				"echo FDT DOWNLOAD FAILED; "		\
			"fi; "						\
		"else; "						\
			"bootm $osaddr; "				\
		"fi; "							\
	"else; "							\
		"echo OS DOWNLOAD FAILED; "				\
	"fi;"

#define CONFIG_PROG_OS							\
	"$download_cmd $osaddr $osfile; "				\
	"if test $? -eq 0; then "					\
		"erase "CONFIG_OS_ENV_ADDR" +$filesize; "		\
		"cp.b $osaddr "CONFIG_OS_ENV_ADDR" $filesize; "		\
		"cmp.b $osaddr "CONFIG_OS_ENV_ADDR" $filesize; "	\
		"if test $? -ne 0; then "				\
			"echo OS PROGRAM FAILED; "			\
		"else; "						\
			"echo OS PROGRAM SUCCEEDED; "			\
		"fi; "							\
	"else; "							\
		"echo OS DOWNLOAD FAILED; "				\
	"fi;"

#define CONFIG_PROG_FDT							\
	"$download_cmd $fdtaddr $fdtfile; "				\
	"if test $? -eq 0; then "					\
		"erase "CONFIG_FDT_ENV_ADDR" +$filesize;"		\
		"cp.b $fdtaddr "CONFIG_FDT_ENV_ADDR" $filesize; "	\
		"cmp.b $fdtaddr "CONFIG_FDT_ENV_ADDR" $filesize; "	\
		"if test $? -ne 0; then "				\
			"echo FDT PROGRAM FAILED; "			\
		"else; "						\
			"echo FDT PROGRAM SUCCEEDED; "			\
		"fi; "							\
	"else; "							\
		"echo FDT DOWNLOAD FAILED; "				\
	"fi;"

#define	CONFIG_EXTRA_ENV_SETTINGS					\
	"autoload=yes\0"						\
	"download_cmd=tftp\0"						\
	"console_args=console=ttyS0,115200\0"				\
	"root_args=root=/dev/nfs rw\0"					\
	"misc_args=ip=on\0"						\
	"set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
	"bootfile=/home/user/file\0"					\
	"osfile=/home/user/board.uImage\0"				\
	"fdtfile=/home/user/board.dtb\0"				\
	"ubootfile=/home/user/u-boot.bin\0"				\
	"fdtaddr=0x1e00000\0"						\
	"osaddr=0x1000000\0"						\
	"loadaddr=0x1000000\0"						\
	"prog_uboot="CONFIG_PROG_UBOOT"\0"				\
	"prog_os="CONFIG_PROG_OS"\0"					\
	"prog_fdt="CONFIG_PROG_FDT"\0"					\
	"bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0"		\
	"bootcmd_flash=run set_bootargs; "				\
		"bootm "CONFIG_OS_ENV_ADDR" - "CONFIG_FDT_ENV_ADDR"\0"	\
	"bootcmd=run bootcmd_flash\0"
#endif	/* __CONFIG_H */
Commit	Line	Data
ba56f625 WD	1	/*
	2	* (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
	3	*
3765b3e7	4	* SPDX-License-Identifier: GPL-2.0+
ba56f625 WD	5	*/
ba56f625 WD	6
e0299076	7	/*
ba56f625 WD	8	* config for XPedite1000 from XES Inc.
	9	* Ported from EBONY config by Travis B. Sawyer <tsawyer@sandburst.com>
	10	* (C) Copyright 2003 Sandburst Corporation
0c8721a4	11	* board/config_EBONY.h - configuration for AMCC 440GP Ref (Ebony)
e0299076	12	*/
ba56f625 WD	13
	14	#ifndef __CONFIG_H
	15	#define __CONFIG_H
	16
e0299076	17	/* High Level Configuration Options */
10c1b218	18	#define CONFIG_XPEDITE1000 1
54381b79	19	#define CONFIG_SYS_BOARD_NAME "XPedite1000"
92af6549	20	#define CONFIG_SYS_FORM_PMC 1
ba56f625	21	#define CONFIG_440 1
846b0dd2	22	#define CONFIG_440GX 1 /* 440 GX */
3c74e32a	23	#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
ba56f625 WD	24	#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
ba56f625 WD	25
2ae18241 WD	26	#define CONFIG_SYS_TEXT_BASE 0xFFF80000
2ae18241 WD	27
4cdad5f4 PT	28	/*
	29	* DDR config
	30	*/
	31	#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */
	32	#define SPD_EEPROM_ADDRESS {0x54} /* SPD i2c spd addresses */
	33	#define CONFIG_VERY_BIG_RAM 1
ba56f625	34
e0299076	35	/*
ba56f625 WD	36	* Base addresses -- Note these are effective addresses where the
ba56f625 WD	37	* actual resources get mapped (not physical addresses)
e0299076	38	*/
4cdad5f4 PT	39	#define CONFIG_SYS_SDRAM_BASE 0x00000000
4cdad5f4 PT	40	#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH */
14d0a02a	41	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
4cdad5f4	42	#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */
4cdad5f4 PT	43	#define CONFIG_SYS_ISRAM_BASE 0xc0000000 /* internal SRAM */
4cdad5f4 PT	44	#define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */
e0299076 PT	45	#define CONFIG_SYS_NVRAM_BASE_ADDR (CONFIG_SYS_PERIPHERAL_BASE + 0x08000000)
e0299076 PT	46	#define CONFIG_SYS_GPIO_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000700)
ba56f625	47
4cdad5f4 PT	48	/*
	49	* Diagnostics
	50	*/
9b4ef1f5	51	#define CONFIG_SYS_ALT_MEMTEST
4cdad5f4 PT	52	#define CONFIG_SYS_MEMTEST_START 0x0400000
	53	#define CONFIG_SYS_MEMTEST_END 0x0C00000
	54
	55	/* POST support */
	56	#define CONFIG_POST (CONFIG_SYS_POST_RTC \| \
	57	CONFIG_SYS_POST_I2C)
	58
	59	/*
	60	* LED support
	61	*/
e0299076 PT	62	#define USR_LED0 0x00000080
	63	#define USR_LED1 0x00000100
	64	#define USR_LED2 0x00000200
	65	#define USR_LED3 0x00000400
ba56f625 WD	66
	67	#ifndef __ASSEMBLY__
	68	extern unsigned long in32(unsigned int);
	69	extern void out32(unsigned int, unsigned long);
	70
6d0f6bcf JCPV	71	#define LED0_ON() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) & ~USR_LED0))
	72	#define LED1_ON() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) & ~USR_LED1))
	73	#define LED2_ON() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) & ~USR_LED2))
	74	#define LED3_ON() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) & ~USR_LED3))
ba56f625	75
6d0f6bcf JCPV	76	#define LED0_OFF() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) \| USR_LED0))
	77	#define LED1_OFF() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) \| USR_LED1))
	78	#define LED2_OFF() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) \| USR_LED2))
	79	#define LED3_OFF() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) \| USR_LED3))
ba56f625 WD	80	#endif
ba56f625 WD	81
4cdad5f4 PT	82	/*
	83	* Use internal SRAM for initial stack
	84	*/
e0299076 PT	85	#define CONFIG_SYS_TEMP_STACK_OCM 1
	86	#define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_ISRAM_BASE
	87	#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_ISRAM_BASE /* Initial RAM address */
553f0982	88	#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */
25ddd1fb	89	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
800eb096	90	#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
ba56f625	91
9b4ef1f5 PT	92	#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */
9b4ef1f5 PT	93	#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
ba56f625	94
4cdad5f4 PT	95	/*
	96	* Serial Port
	97	*/
550650dd	98	#define CONFIG_CONS_INDEX 1 /* Use UART0 */
550650dd SR	99	#define CONFIG_SYS_NS16550_SERIAL
	100	#define CONFIG_SYS_NS16550_REG_SIZE 1
	101	#define CONFIG_SYS_NS16550_CLK get_serial_clock()
	102
e0299076 PT	103	#define CONFIG_SYS_BAUDRATE_TABLE \
e0299076 PT	104	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400}
9b4ef1f5	105	#define CONFIG_BAUDRATE 115200
4cdad5f4 PT	106	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
4cdad5f4 PT	107	#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
ba56f625	108
e0299076	109	/*
4cdad5f4	110	* NOR flash configuration
e0299076	111	*/
42735815 PT	112	#define CONFIG_SYS_MAX_FLASH_BANKS 3
	113	#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, 0xf0000000, 0xf4000000 }
	114	#define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */
11ad309c PT	115	#define CONFIG_FLASH_CFI_DRIVER
	116	#define CONFIG_SYS_FLASH_CFI
	117	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
42735815	118	#define CONFIG_SYS_FLASH_QUIET_TEST /* MirrorBit flashes are optional */
e0299076 PT	119	#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
	120	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
	121
4cdad5f4 PT	122	/*
	123	* I2C
	124	*/
880540de DE	125	#define CONFIG_SYS_I2C
	126	#define CONFIG_SYS_I2C_PPC4XX
	127	#define CONFIG_SYS_I2C_PPC4XX_CH0
	128	#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
	129	#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7f
ba56f625	130
4cdad5f4 PT	131	/* I2C EEPROM */
4cdad5f4 PT	132	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
e0299076 PT	133	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
	134	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
	135	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
ba56f625	136
4cdad5f4 PT	137	/* I2C RTC: STMicro M41T00 */
	138	#define CONFIG_RTC_M41T11 1
	139	#define CONFIG_SYS_I2C_RTC_ADDR 0x68
	140	#define CONFIG_SYS_M41T11_BASE_YEAR 2000
	141
	142	/*
	143	* PCI
	144	*/
	145	/* General PCI */
	146	#define CONFIG_PCI /* include pci support */
842033e6	147	#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
4cdad5f4 PT	148	#define CONFIG_PCI_PNP /* do pci plug-and-play */
	149	#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
	150	#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE */
	151
	152	/* Board-specific PCI */
	153	#define CONFIG_SYS_PCI_TARGET_INIT /* let board init pci target */
	154	#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014 /* IBM */
	155	#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
	156	#define CONFIG_SYS_PCI_FORCE_PCI_CONV /* Force PCI Conventional Mode */
ba56f625	157
4cdad5f4 PT	158	/*
	159	* Networking options
	160	*/
96e21f86	161	#define CONFIG_PPC4xx_EMAC
6fb6af6d	162	#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
4cdad5f4	163	#define CONFIG_MII 1 /* MII PHY management */
e0299076 PT	164	#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
e0299076 PT	165	#define CONFIG_SYS_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
4cdad5f4 PT	166	#define CONFIG_ETHPRIME "ppc_4xx_eth2"
	167	#define CONFIG_PHY_ADDR 4 /* PHY address phy0 not populated */
	168	#define CONFIG_PHY2_ADDR 4 /* PHY address phy2 */
e0299076	169	#define CONFIG_HAS_ETH2 1 /* add support for "eth2addr" */
4cdad5f4	170	#define CONFIG_PHY3_ADDR 8 /* PHY address phy3 */
e0299076	171	#define CONFIG_HAS_ETH3 1 /* add support for "eth3addr" */
a5562901	172
e0299076	173	/* BOOTP options */
a1aa0bb5 JL	174	#define CONFIG_BOOTP_BOOTFILESIZE
	175	#define CONFIG_BOOTP_BOOTPATH
	176	#define CONFIG_BOOTP_GATEWAY
	177	#define CONFIG_BOOTP_HOSTNAME
	178
a5562901	179	/*
4cdad5f4	180	* Command configuration
a5562901	181	*/
a5562901	182	#define CONFIG_CMD_DATE
a5562901	183	#define CONFIG_CMD_EEPROM
c4ae1a02 PT	184	#define CONFIG_CMD_IRQ
c4ae1a02 PT	185	#define CONFIG_CMD_JFFS2
c4ae1a02	186	#define CONFIG_CMD_PCI
a5562901	187
ba56f625 WD	188	/*
	189	* Miscellaneous configurable options
	190	*/
e0299076	191	#define CONFIG_SYS_LONGHELP /* undef to save memory */
4cdad5f4	192	#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
e0299076	193	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
6d0f6bcf	194	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
e0299076 PT	195	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
e0299076 PT	196	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
9b4ef1f5	197	#define CONFIG_CMDLINE_EDITING 1 /* Command-line editing */
9b4ef1f5 PT	198	#define CONFIG_PANIC_HANG /* do not reset board on panic */
9b4ef1f5 PT	199	#define CONFIG_PREBOOT /* enable preboot variable */
9b4ef1f5 PT	200	#define CONFIG_INTEGRITY /* support booting INTEGRITY OS */
9b4ef1f5 PT	201	#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
e0299076	202
ba56f625 WD	203	/*
	204	* For booting Linux, the board info and command line data
	205	* have to be in the first 8 MB of memory, since this is
	206	* the maximum mapped by the Linux kernel during initialization.
	207	*/
6d0f6bcf	208	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
ba56f625	209
4cdad5f4 PT	210	/*
	211	* Environment Configuration
	212	*/
	213	#define CONFIG_ENV_IS_IN_FLASH 1
	214	#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k (one sector) for env */
	215	#define CONFIG_ENV_SIZE 0x8000
	216	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - (256 * 1024))
	217
c4ae1a02 PT	218	/*
	219	* Flash memory map:
	220	* fff80000 - ffffffff U-Boot (512 KB)
	221	* fff40000 - fff7ffff U-Boot Environment (256 KB)
	222	* fff00000 - fff3ffff FDT (256KB)
	223	* ffc00000 - ffefffff OS image (3MB)
	224	* ff000000 - ffbfffff OS Use/Filesystem (12MB)
	225	*/
	226
5368c55d MV	227	#define CONFIG_UBOOT_ENV_ADDR __stringify(CONFIG_SYS_TEXT_BASE)
	228	#define CONFIG_FDT_ENV_ADDR __stringify(0xfff00000)
	229	#define CONFIG_OS_ENV_ADDR __stringify(0xffc00000)
c4ae1a02 PT	230
	231	#define CONFIG_PROG_UBOOT \
	232	"$download_cmd $loadaddr $ubootfile; " \
	233	"if test $? -eq 0; then " \
	234	"protect off "CONFIG_UBOOT_ENV_ADDR" +80000; " \
	235	"erase "CONFIG_UBOOT_ENV_ADDR" +80000; " \
	236	"cp.w $loadaddr "CONFIG_UBOOT_ENV_ADDR" 40000; " \
	237	"protect on "CONFIG_UBOOT_ENV_ADDR" +80000; " \
	238	"cmp.b $loadaddr "CONFIG_UBOOT_ENV_ADDR" 80000; " \
	239	"if test $? -ne 0; then " \
	240	"echo PROGRAM FAILED; " \
	241	"else; " \
	242	"echo PROGRAM SUCCEEDED; " \
	243	"fi; " \
	244	"else; " \
	245	"echo DOWNLOAD FAILED; " \
	246	"fi;"
	247
	248	#define CONFIG_BOOT_OS_NET \
	249	"$download_cmd $osaddr $osfile; " \
	250	"if test $? -eq 0; then " \
	251	"if test -n $fdtaddr; then " \
	252	"$download_cmd $fdtaddr $fdtfile; " \
	253	"if test $? -eq 0; then " \
	254	"bootm $osaddr - $fdtaddr; " \
	255	"else; " \
	256	"echo FDT DOWNLOAD FAILED; " \
	257	"fi; " \
	258	"else; " \
	259	"bootm $osaddr; " \
	260	"fi; " \
	261	"else; " \
	262	"echo OS DOWNLOAD FAILED; " \
	263	"fi;"
	264
	265	#define CONFIG_PROG_OS \
	266	"$download_cmd $osaddr $osfile; " \
	267	"if test $? -eq 0; then " \
	268	"erase "CONFIG_OS_ENV_ADDR" +$filesize; " \
	269	"cp.b $osaddr "CONFIG_OS_ENV_ADDR" $filesize; " \
	270	"cmp.b $osaddr "CONFIG_OS_ENV_ADDR" $filesize; " \
	271	"if test $? -ne 0; then " \
	272	"echo OS PROGRAM FAILED; " \
	273	"else; " \
	274	"echo OS PROGRAM SUCCEEDED; " \
	275	"fi; " \
	276	"else; " \
	277	"echo OS DOWNLOAD FAILED; " \
	278	"fi;"
	279
	280	#define CONFIG_PROG_FDT \
	281	"$download_cmd $fdtaddr $fdtfile; " \
	282	"if test $? -eq 0; then " \
	283	"erase "CONFIG_FDT_ENV_ADDR" +$filesize;" \
	284	"cp.b $fdtaddr "CONFIG_FDT_ENV_ADDR" $filesize; " \
	285	"cmp.b $fdtaddr "CONFIG_FDT_ENV_ADDR" $filesize; " \
	286	"if test $? -ne 0; then " \
	287	"echo FDT PROGRAM FAILED; " \
	288	"else; " \
	289	"echo FDT PROGRAM SUCCEEDED; " \
	290	"fi; " \
	291	"else; " \
	292	"echo FDT DOWNLOAD FAILED; " \
	293	"fi;"
294
295	#define CONFIG_EXTRA_ENV_SETTINGS \
296	"autoload=yes\0" \
297	"download_cmd=tftp\0" \
298	"console_args=console=ttyS0,115200\0" \
299	"root_args=root=/dev/nfs rw\0" \
300	"misc_args=ip=on\0" \
301	"set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
302	"bootfile=/home/user/file\0" \
c00ac259 PT	303	"osfile=/home/user/board.uImage\0" \
c00ac259 PT	304	"fdtfile=/home/user/board.dtb\0" \
c4ae1a02	305	"ubootfile=/home/user/u-boot.bin\0" \
b24a4f62	306	"fdtaddr=0x1e00000\0" \
c4ae1a02 PT	307	"osaddr=0x1000000\0" \
	308	"loadaddr=0x1000000\0" \
	309	"prog_uboot="CONFIG_PROG_UBOOT"\0" \
	310	"prog_os="CONFIG_PROG_OS"\0" \
	311	"prog_fdt="CONFIG_PROG_FDT"\0" \
	312	"bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \
	313	"bootcmd_flash=run set_bootargs; " \
	314	"bootm "CONFIG_OS_ENV_ADDR" - "CONFIG_FDT_ENV_ADDR"\0" \
	315	"bootcmd=run bootcmd_flash\0"
ba56f625	316	#endif /* __CONFIG_H */