[people/ms/u-boot.git] / include / configs / xpedite520x.h

/*
 * Copyright 2008 Extreme Engineering Solutions, Inc.
 * Copyright 2004-2008 Freescale Semiconductor, Inc.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*
 * xpedite520x board configuration file
 */
#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 */
#define CONFIG_BOOKE		1	/* BOOKE */
#define CONFIG_E500		1	/* BOOKE e500 family */
#define CONFIG_MPC8548		1
#define CONFIG_XPEDITE5200	1
#define CONFIG_SYS_BOARD_NAME	"XPedite5200"
#define CONFIG_SYS_FORM_PMC_XMC	1
#define CONFIG_BOARD_EARLY_INIT_R	/* Call board_pre_init */

#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE	0xfff80000
#endif

#define CONFIG_PCI		1	/* Enable PCI/PCIE */
#define CONFIG_PCI_PNP		1	/* do pci plug-and-play */
#define CONFIG_PCI_SCAN_SHOW	1	/* show pci devices on startup */
#define CONFIG_PCI1		1	/* PCI controller 1 */
#define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
#define CONFIG_PCI_INDIRECT_BRIDGE 1	/* indirect PCI bridge support */
#define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
#define CONFIG_FSL_LAW		1	/* Use common FSL init code */

/*
 * DDR config
 */
#define CONFIG_SYS_FSL_DDR2
#undef CONFIG_FSL_DDR_INTERACTIVE
#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
#define CONFIG_DDR_SPD
#define CONFIG_MEM_INIT_VALUE		0xdeadbeef
#define SPD_EEPROM_ADDRESS		0x54
#define CONFIG_NUM_DDR_CONTROLLERS	1
#define CONFIG_DIMM_SLOTS_PER_CTLR	1
#define CONFIG_CHIP_SELECTS_PER_CTRL	2
#define CONFIG_DDR_ECC
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_VERY_BIG_RAM

#define CONFIG_SYS_CLK_FREQ	66666666

/*
 * These can be toggled for performance analysis, otherwise use default.
 */
#define CONFIG_L2_CACHE			/* toggle L2 cache */
#define CONFIG_BTB			/* toggle branch predition */
#define CONFIG_ENABLE_36BIT_PHYS	1

#define CONFIG_SYS_CCSRBAR		0xef000000
#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR

/*
 * Diagnostics
 */
#define CONFIG_SYS_ALT_MEMTEST
#define CONFIG_SYS_MEMTEST_START	0x10000000
#define CONFIG_SYS_MEMTEST_END		0x20000000
#define CONFIG_POST			(CONFIG_SYS_POST_MEMORY | \
					 CONFIG_SYS_POST_I2C)
#define I2C_ADDR_LIST			{CONFIG_SYS_I2C_MAX1237_ADDR,	\
					 CONFIG_SYS_I2C_EEPROM_ADDR,	\
					 CONFIG_SYS_I2C_PCA953X_ADDR0,	\
					 CONFIG_SYS_I2C_PCA953X_ADDR1,	\
					 CONFIG_SYS_I2C_RTC_ADDR}

/*
 * Memory map
 * 0x0000_0000	0x7fff_ffff	DDR			2G Cacheable
 * 0x8000_0000	0xbfff_ffff	PCI1 Mem		1G non-cacheable
 * 0xe000_0000	0xe7ff_ffff	SRAM/SSRAM/L1 Cache	128M non-cacheable
 * 0xe800_0000	0xe87f_ffff	PCI1 IO			8M non-cacheable
 * 0xef00_0000	0xef0f_ffff	CCSR/IMMR		1M non-cacheable
 * 0xef80_0000	0xef8f_ffff	NAND Flash		1M non-cacheable
 * 0xf800_0000	0xfbff_ffff	NOR Flash 2		64M non-cacheable
 * 0xfc00_0000	0xffff_ffff	NOR Flash 1		64M non-cacheable
 */

#define CONFIG_SYS_LBC_LCRR	(LCRR_CLKDIV_8 | LCRR_EADC_3)

/*
 * NAND flash configuration
 */
#define CONFIG_SYS_NAND_BASE		0xef800000
#define CONFIG_SYS_NAND_BASE2		0xef840000 /* Unused at this time */
#define CONFIG_SYS_MAX_NAND_DEVICE	1
#define CONFIG_NAND_ACTL
#define CONFIG_SYS_NAND_ACTL_CLE	(1 << 3)	/* ADDR3 is CLE */
#define CONFIG_SYS_NAND_ACTL_ALE	(1 << 4)	/* ADDR4 is ALE */
#define CONFIG_SYS_NAND_ACTL_NCE	(0)		/* NCE not controlled by ADDR */
#define CONFIG_SYS_NAND_ACTL_DELAY	25

/*
 * NOR flash configuration
 */
#define CONFIG_SYS_FLASH_BASE		0xfc000000
#define CONFIG_SYS_FLASH_BASE2		0xf8000000
#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
#define CONFIG_SYS_MAX_FLASH_BANKS	2		/* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT	1024		/* sectors per device */
#define CONFIG_SYS_FLASH_ERASE_TOUT	60000		/* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500		/* Flash Write Timeout (ms) */
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
#define CONFIG_SYS_FLASH_AUTOPROTECT_LIST	{ {0xfff40000, 0xc0000}, \
						  {0xfbf40000, 0xc0000} }
#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */

/*
 * Chip select configuration
 */
/* NOR Flash 0 on CS0 */
#define CONFIG_SYS_BR0_PRELIM	(CONFIG_SYS_FLASH_BASE	| \
				 BR_PS_16		| \
				 BR_V)
#define CONFIG_SYS_OR0_PRELIM	(OR_AM_64MB		| \
				 OR_GPCM_ACS_DIV4	| \
				 OR_GPCM_SCY_8)

/* NOR Flash 1 on CS1 */
#define CONFIG_SYS_BR1_PRELIM	(CONFIG_SYS_FLASH_BASE2	| \
				 BR_PS_16		| \
				 BR_V)
#define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_OR0_PRELIM

/* NAND flash on CS2 */
#define CONFIG_SYS_BR2_PRELIM	(CONFIG_SYS_NAND_BASE	| \
				 BR_PS_8		| \
				 BR_V)

/* NAND flash on CS2 */
#define CONFIG_SYS_OR2_PRELIM	(OR_AM_256KB		| \
				 OR_GPCM_BCTLD		| \
				 OR_GPCM_CSNT		| \
				 OR_GPCM_ACS_DIV4	| \
				 OR_GPCM_SCY_4		| \
				 OR_GPCM_TRLX		| \
				 OR_GPCM_EHTR)

/* NAND flash on CS3 */
#define CONFIG_SYS_BR3_PRELIM	(CONFIG_SYS_NAND_BASE2	| \
				 BR_PS_8		| \
				 BR_V)
#define CONFIG_SYS_OR3_PRELIM	CONFIG_SYS_OR2_PRELIM

/*
 * Use L1 as initial stack
 */
#define CONFIG_SYS_INIT_RAM_LOCK	1
#define CONFIG_SYS_INIT_RAM_ADDR	0xe0000000
#define CONFIG_SYS_INIT_RAM_SIZE		0x4000

#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)	/* Reserve 512 KB for Mon */
#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)	/* Reserved for malloc */

/*
 * Serial Port
 */
#define CONFIG_CONS_INDEX		1
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
#define CONFIG_SYS_BAUDRATE_TABLE	\
	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
#define CONFIG_BAUDRATE			115200
#define CONFIG_LOADS_ECHO		1	/* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */

/*
 * I2C
 */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED	400000
#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
#define CONFIG_SYS_FSL_I2C2_SPEED	400000
#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100

/* I2C EEPROM */
#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	6	/* 64 byte pages */
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* take up to 10 msec */

/* I2C RTC */
#define CONFIG_RTC_M41T11			1
#define CONFIG_SYS_I2C_RTC_ADDR			0x68
#define CONFIG_SYS_M41T11_BASE_YEAR		2000

/* GPIO */
#define CONFIG_PCA953X
#define CONFIG_SYS_I2C_PCA953X_ADDR0		0x18
#define CONFIG_SYS_I2C_PCA953X_ADDR1		0x19
#define CONFIG_SYS_I2C_PCA953X_ADDR		CONFIG_SYS_I2C_PCA953X_ADDR0

/* PCA957 @ 0x18 */
#define CONFIG_SYS_PCA953X_BRD_CFG0		0x01
#define CONFIG_SYS_PCA953X_BRD_CFG1		0x02
#define CONFIG_SYS_PCA953X_BRD_CFG2		0x04
#define CONFIG_SYS_PCA953X_XMC_ROOT0		0x08
#define CONFIG_SYS_PCA953X_FLASH_PASS_CS	0x10
#define CONFIG_SYS_PCA953X_NVM_WP		0x20
#define CONFIG_SYS_PCA953X_MONARCH		0x40
#define CONFIG_SYS_PCA953X_EREADY		0x80

/* PCA957 @ 0x19 */
#define CONFIG_SYS_PCA953X_P14_IO0		0x01
#define CONFIG_SYS_PCA953X_P14_IO1		0x02
#define CONFIG_SYS_PCA953X_P14_IO2		0x04
#define CONFIG_SYS_PCA953X_P14_IO3		0x08
#define CONFIG_SYS_PCA953X_P14_IO4		0x10
#define CONFIG_SYS_PCA953X_P14_IO5		0x20
#define CONFIG_SYS_PCA953X_P14_IO6		0x40
#define CONFIG_SYS_PCA953X_P14_IO7		0x80

/* 12-bit ADC used to measure CPU diode */
#define CONFIG_SYS_I2C_MAX1237_ADDR		0x34

/*
 * General PCI
 * Memory space is mapped 1-1, but I/O space must start from 0.
 */
#define CONFIG_SYS_PCI1_MEM_BUS		0x80000000
#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BUS
#define CONFIG_SYS_PCI1_MEM_SIZE	0x40000000	/* 1G */
#define CONFIG_SYS_PCI1_IO_BUS		0x00000000
#define CONFIG_SYS_PCI1_IO_PHYS		0xe8000000
#define CONFIG_SYS_PCI1_IO_SIZE		0x00800000	/* 1M */

/*
 * Networking options
 */
#define CONFIG_TSEC_ENET		/* tsec ethernet support */
#define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
#define CONFIG_MII		1	/* MII PHY management */
#define CONFIG_ETHPRIME		"eTSEC1"

#define CONFIG_TSEC1		1
#define CONFIG_TSEC1_NAME	"eTSEC1"
#define TSEC1_FLAGS		TSEC_GIGABIT
#define TSEC1_PHY_ADDR		1
#define TSEC1_PHYIDX		0
#define CONFIG_HAS_ETH0

#define CONFIG_TSEC2		1
#define CONFIG_TSEC2_NAME	"eTSEC2"
#define TSEC2_FLAGS		TSEC_GIGABIT
#define TSEC2_PHY_ADDR		2
#define TSEC2_PHYIDX		0
#define CONFIG_HAS_ETH1

#define CONFIG_TSEC3	1
#define CONFIG_TSEC3_NAME	"eTSEC3"
#define TSEC3_FLAGS		TSEC_GIGABIT
#define TSEC3_PHY_ADDR		3
#define TSEC3_PHYIDX		0
#define CONFIG_HAS_ETH2

#define CONFIG_TSEC4	1
#define CONFIG_TSEC4_NAME	"eTSEC4"
#define TSEC4_FLAGS		TSEC_GIGABIT
#define TSEC4_PHY_ADDR		4
#define TSEC4_PHYIDX		0
#define CONFIG_HAS_ETH3

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY

/*
 * Command configuration.
 */
#define CONFIG_CMD_DATE
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_NAND
#define CONFIG_CMD_PCA953X
#define CONFIG_CMD_PCA953X_INFO
#define CONFIG_CMD_PCI
#define CONFIG_CMD_PCI_ENUM
#define CONFIG_CMD_REGINFO

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
#define CONFIG_CMDLINE_EDITING	1		/* add command line history	*/
#define CONFIG_AUTO_COMPLETE	1		/* add autocompletion support */
#define CONFIG_LOADADDR		0x1000000	/* default location for tftp and bootm */
#define CONFIG_PANIC_HANG			/* do not reset board on panic */
#define CONFIG_PREBOOT				/* enable preboot variable */
#define CONFIG_INTEGRITY			/* support booting INTEGRITY OS */
#define CONFIG_INTERRUPTS		/* enable pci, srio, ddr interrupts */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 16 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ	(16 << 20)	/* Initial Memory map for Linux*/
#define CONFIG_SYS_BOOTM_LEN	(16 << 20)	/* Increase max gunzip size */

/*
 * Environment Configuration
 */
#define CONFIG_ENV_IS_IN_FLASH	1
#define CONFIG_ENV_SECT_SIZE	0x20000		/* 128k (one sector) for env */
#define CONFIG_ENV_SIZE		0x8000
#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - (256 * 1024))

/*
 * Flash memory map:
 * fff80000 - ffffffff     Pri U-Boot (512 KB)
 * fff40000 - fff7ffff     Pri U-Boot Environment (256 KB)
 * fff00000 - fff3ffff     Pri FDT (256KB)
 * fef00000 - ffefffff     Pri OS image (16MB)
 * fc000000 - feefffff     Pri OS Use/Filesystem (47MB)
 *
 * fbf80000 - fbffffff     Sec U-Boot (512 KB)
 * fbf40000 - fbf7ffff     Sec U-Boot Environment (256 KB)
 * fbf00000 - fbf3ffff     Sec FDT (256KB)
 * faf00000 - fbefffff     Sec OS image (16MB)
 * f8000000 - faefffff     Sec OS Use/Filesystem (47MB)
 */
#define CONFIG_UBOOT1_ENV_ADDR	__stringify(0xfff80000)
#define CONFIG_UBOOT2_ENV_ADDR	__stringify(0xfbf80000)
#define CONFIG_FDT1_ENV_ADDR	__stringify(0xfff00000)
#define CONFIG_FDT2_ENV_ADDR	__stringify(0xfbf00000)
#define CONFIG_OS1_ENV_ADDR	__stringify(0xfef00000)
#define CONFIG_OS2_ENV_ADDR	__stringify(0xfaf00000)

#define CONFIG_PROG_UBOOT1						\
	"$download_cmd $loadaddr $ubootfile; "				\
	"if test $? -eq 0; then "					\
		"protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; "		\
		"erase "CONFIG_UBOOT1_ENV_ADDR" +80000; "		\
		"cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; "	\
		"protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; "		\
		"cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; "	\
		"if test $? -ne 0; then "				\
			"echo PROGRAM FAILED; "				\
		"else; "						\
			"echo PROGRAM SUCCEEDED; "			\
		"fi; "							\
	"else; "							\
		"echo DOWNLOAD FAILED; "				\
	"fi;"

#define CONFIG_PROG_UBOOT2						\
	"$download_cmd $loadaddr $ubootfile; "				\
	"if test $? -eq 0; then "					\
		"protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; "		\
		"erase "CONFIG_UBOOT2_ENV_ADDR" +80000; "		\
		"cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; "	\
		"protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; "		\
		"cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; "	\
		"if test $? -ne 0; then "				\
			"echo PROGRAM FAILED; "				\
		"else; "						\
			"echo PROGRAM SUCCEEDED; "			\
		"fi; "							\
	"else; "							\
		"echo DOWNLOAD FAILED; "				\
	"fi;"

#define CONFIG_BOOT_OS_NET						\
	"$download_cmd $osaddr $osfile; "				\
	"if test $? -eq 0; then "					\
		"if test -n $fdtaddr; then "				\
			"$download_cmd $fdtaddr $fdtfile; "		\
			"if test $? -eq 0; then "			\
				"bootm $osaddr - $fdtaddr; "		\
			"else; "					\
				"echo FDT DOWNLOAD FAILED; "		\
			"fi; "						\
		"else; "						\
			"bootm $osaddr; "				\
		"fi; "							\
	"else; "							\
		"echo OS DOWNLOAD FAILED; "				\
	"fi;"

#define CONFIG_PROG_OS1							\
	"$download_cmd $osaddr $osfile; "				\
	"if test $? -eq 0; then "					\
		"erase "CONFIG_OS1_ENV_ADDR" +$filesize; "		\
		"cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; "	\
		"cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; "	\
		"if test $? -ne 0; then "				\
			"echo OS PROGRAM FAILED; "			\
		"else; "						\
			"echo OS PROGRAM SUCCEEDED; "			\
		"fi; "							\
	"else; "							\
		"echo OS DOWNLOAD FAILED; "				\
	"fi;"

#define CONFIG_PROG_OS2							\
	"$download_cmd $osaddr $osfile; "				\
	"if test $? -eq 0; then "					\
		"erase "CONFIG_OS2_ENV_ADDR" +$filesize; "		\
		"cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; "	\
		"cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; "	\
		"if test $? -ne 0; then "				\
			"echo OS PROGRAM FAILED; "			\
		"else; "						\
			"echo OS PROGRAM SUCCEEDED; "			\
		"fi; "							\
	"else; "							\
		"echo OS DOWNLOAD FAILED; "				\
	"fi;"

#define CONFIG_PROG_FDT1						\
	"$download_cmd $fdtaddr $fdtfile; "				\
	"if test $? -eq 0; then "					\
		"erase "CONFIG_FDT1_ENV_ADDR" +$filesize;"		\
		"cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; "	\
		"cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; "	\
		"if test $? -ne 0; then "				\
			"echo FDT PROGRAM FAILED; "			\
		"else; "						\
			"echo FDT PROGRAM SUCCEEDED; "			\
		"fi; "							\
	"else; "							\
		"echo FDT DOWNLOAD FAILED; "				\
	"fi;"

#define CONFIG_PROG_FDT2						\
	"$download_cmd $fdtaddr $fdtfile; "				\
	"if test $? -eq 0; then "					\
		"erase "CONFIG_FDT2_ENV_ADDR" +$filesize;"		\
		"cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; "	\
		"cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; "	\
		"if test $? -ne 0; then "				\
			"echo FDT PROGRAM FAILED; "			\
		"else; "						\
			"echo FDT PROGRAM SUCCEEDED; "			\
		"fi; "							\
	"else; "							\
		"echo FDT DOWNLOAD FAILED; "				\
	"fi;"

#define	CONFIG_EXTRA_ENV_SETTINGS					\
	"autoload=yes\0"						\
	"download_cmd=tftp\0"						\
	"console_args=console=ttyS0,115200\0"				\
	"root_args=root=/dev/nfs rw\0"					\
	"misc_args=ip=on\0"						\
	"set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
	"bootfile=/home/user/file\0"					\
	"osfile=/home/user/board.uImage\0"				\
	"fdtfile=/home/user/board.dtb\0"				\
	"ubootfile=/home/user/u-boot.bin\0"				\
	"fdtaddr=0x1e00000\0"						\
	"osaddr=0x1000000\0"						\
	"loadaddr=0x1000000\0"						\
	"prog_uboot1="CONFIG_PROG_UBOOT1"\0"				\
	"prog_uboot2="CONFIG_PROG_UBOOT2"\0"				\
	"prog_os1="CONFIG_PROG_OS1"\0"					\
	"prog_os2="CONFIG_PROG_OS2"\0"					\
	"prog_fdt1="CONFIG_PROG_FDT1"\0"				\
	"prog_fdt2="CONFIG_PROG_FDT2"\0"				\
	"bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0"		\
	"bootcmd_flash1=run set_bootargs; "				\
		"bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
	"bootcmd_flash2=run set_bootargs; "				\
		"bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
	"bootcmd=run bootcmd_flash1\0"
#endif	/* __CONFIG_H */
Commit	Line	Data
1f03cbfa PT	1	/*
	2	* Copyright 2008 Extreme Engineering Solutions, Inc.
	3	* Copyright 2004-2008 Freescale Semiconductor, Inc.
	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
1f03cbfa PT	6	*/
	7
	8	/*
c00ac259	9	* xpedite520x board configuration file
1f03cbfa PT	10	*/
	11	#ifndef __CONFIG_H
	12	#define __CONFIG_H
	13
	14	/*
	15	* High Level Configuration Options
	16	*/
	17	#define CONFIG_BOOKE 1 /* BOOKE */
	18	#define CONFIG_E500 1 /* BOOKE e500 family */
1f03cbfa PT	19	#define CONFIG_MPC8548 1
	20	#define CONFIG_XPEDITE5200 1
	21	#define CONFIG_SYS_BOARD_NAME "XPedite5200"
92af6549	22	#define CONFIG_SYS_FORM_PMC_XMC 1
1f03cbfa	23	#define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */
1f03cbfa	24
2ae18241 WD	25	#ifndef CONFIG_SYS_TEXT_BASE
	26	#define CONFIG_SYS_TEXT_BASE 0xfff80000
	27	#endif
	28
1f03cbfa PT	29	#define CONFIG_PCI 1 /* Enable PCI/PCIE */
	30	#define CONFIG_PCI_PNP 1 /* do pci plug-and-play */
	31	#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
	32	#define CONFIG_PCI1 1 /* PCI controller 1 */
	33	#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
842033e6	34	#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
1f03cbfa PT	35	#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
	36	#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
	37
	38	/*
	39	* DDR config
	40	*/
5614e71b	41	#define CONFIG_SYS_FSL_DDR2
1f03cbfa PT	42	#undef CONFIG_FSL_DDR_INTERACTIVE
	43	#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
	44	#define CONFIG_DDR_SPD
	45	#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
	46	#define SPD_EEPROM_ADDRESS 0x54
	47	#define CONFIG_NUM_DDR_CONTROLLERS 1
	48	#define CONFIG_DIMM_SLOTS_PER_CTLR 1
	49	#define CONFIG_CHIP_SELECTS_PER_CTRL 2
	50	#define CONFIG_DDR_ECC
	51	#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
	52	#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
	53	#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
	54	#define CONFIG_VERY_BIG_RAM
	55
	56	#define CONFIG_SYS_CLK_FREQ 66666666
	57
	58	/*
	59	* These can be toggled for performance analysis, otherwise use default.
	60	*/
	61	#define CONFIG_L2_CACHE /* toggle L2 cache */
	62	#define CONFIG_BTB /* toggle branch predition */
	63	#define CONFIG_ENABLE_36BIT_PHYS 1
	64
e46fedfe TT	65	#define CONFIG_SYS_CCSRBAR 0xef000000
e46fedfe TT	66	#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
1f03cbfa PT	67
	68	/*
	69	* Diagnostics
	70	*/
	71	#define CONFIG_SYS_ALT_MEMTEST
	72	#define CONFIG_SYS_MEMTEST_START 0x10000000
	73	#define CONFIG_SYS_MEMTEST_END 0x20000000
66a8b440 PT	74	#define CONFIG_POST (CONFIG_SYS_POST_MEMORY \| \
	75	CONFIG_SYS_POST_I2C)
	76	#define I2C_ADDR_LIST {CONFIG_SYS_I2C_MAX1237_ADDR, \
	77	CONFIG_SYS_I2C_EEPROM_ADDR, \
	78	CONFIG_SYS_I2C_PCA953X_ADDR0, \
	79	CONFIG_SYS_I2C_PCA953X_ADDR1, \
	80	CONFIG_SYS_I2C_RTC_ADDR}
1f03cbfa PT	81
	82	/*
	83	* Memory map
	84	* 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
	85	* 0x8000_0000 0xbfff_ffff PCI1 Mem 1G non-cacheable
	86	* 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable
	87	* 0xe800_0000 0xe87f_ffff PCI1 IO 8M non-cacheable
	88	* 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable
	89	* 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable
	90	* 0xf800_0000 0xfbff_ffff NOR Flash 2 64M non-cacheable
	91	* 0xfc00_0000 0xffff_ffff NOR Flash 1 64M non-cacheable
	92	*/
	93
202d9487	94	#define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_8 \| LCRR_EADC_3)
1f03cbfa PT	95
	96	/*
	97	* NAND flash configuration
	98	*/
	99	#define CONFIG_SYS_NAND_BASE 0xef800000
	100	#define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */
	101	#define CONFIG_SYS_MAX_NAND_DEVICE 1
	102	#define CONFIG_NAND_ACTL
	103	#define CONFIG_SYS_NAND_ACTL_CLE (1 << 3) /* ADDR3 is CLE */
	104	#define CONFIG_SYS_NAND_ACTL_ALE (1 << 4) /* ADDR4 is ALE */
	105	#define CONFIG_SYS_NAND_ACTL_NCE (0) /* NCE not controlled by ADDR */
	106	#define CONFIG_SYS_NAND_ACTL_DELAY 25
	107
	108	/*
	109	* NOR flash configuration
	110	*/
	111	#define CONFIG_SYS_FLASH_BASE 0xfc000000
	112	#define CONFIG_SYS_FLASH_BASE2 0xf8000000
	113	#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
	114	#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
	115	#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
	116	#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
	117	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
	118	#define CONFIG_FLASH_CFI_DRIVER
	119	#define CONFIG_SYS_FLASH_CFI
5ff82100	120	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
1f03cbfa PT	121	#define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff40000, 0xc0000}, \
1f03cbfa PT	122	{0xfbf40000, 0xc0000} }
14d0a02a	123	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
1f03cbfa PT	124
	125	/*
	126	* Chip select configuration
	127	*/
	128	/* NOR Flash 0 on CS0 */
	129	#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \| \
	130	BR_PS_16 \| \
	131	BR_V)
	132	#define CONFIG_SYS_OR0_PRELIM (OR_AM_64MB \| \
	133	OR_GPCM_ACS_DIV4 \| \
	134	OR_GPCM_SCY_8)
	135
	136	/* NOR Flash 1 on CS1 */
	137	#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 \| \
	138	BR_PS_16 \| \
	139	BR_V)
	140	#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
	141
	142	/* NAND flash on CS2 */
	143	#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE \| \
	144	BR_PS_8 \| \
	145	BR_V)
	146
	147	/* NAND flash on CS2 */
	148	#define CONFIG_SYS_OR2_PRELIM (OR_AM_256KB \| \
	149	OR_GPCM_BCTLD \| \
	150	OR_GPCM_CSNT \| \
	151	OR_GPCM_ACS_DIV4 \| \
	152	OR_GPCM_SCY_4 \| \
	153	OR_GPCM_TRLX \| \
	154	OR_GPCM_EHTR)
	155
	156	/* NAND flash on CS3 */
	157	#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE2 \| \
	158	BR_PS_8 \| \
	159	BR_V)
	160	#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
	161
	162	/*
	163	* Use L1 as initial stack
	164	*/
	165	#define CONFIG_SYS_INIT_RAM_LOCK 1
	166	#define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000
553f0982	167	#define CONFIG_SYS_INIT_RAM_SIZE 0x4000
1f03cbfa	168
25ddd1fb	169	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
1f03cbfa PT	170	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
	171
	172	#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */
	173	#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
	174
	175	/*
	176	* Serial Port
	177	*/
	178	#define CONFIG_CONS_INDEX 1
1f03cbfa PT	179	#define CONFIG_SYS_NS16550_SERIAL
	180	#define CONFIG_SYS_NS16550_REG_SIZE 1
	181	#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
	182	#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
	183	#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
	184	#define CONFIG_SYS_BAUDRATE_TABLE \
	185	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
	186	#define CONFIG_BAUDRATE 115200
	187	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
	188	#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
	189
1f03cbfa PT	190	/*
	191	* I2C
	192	*/
00f792e0 HS	193	#define CONFIG_SYS_I2C
	194	#define CONFIG_SYS_I2C_FSL
	195	#define CONFIG_SYS_FSL_I2C_SPEED 400000
	196	#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
	197	#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
	198	#define CONFIG_SYS_FSL_I2C2_SPEED 400000
	199	#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
	200	#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
1f03cbfa PT	201
	202	/* I2C EEPROM */
	203	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
	204	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
	205	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */
	206	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */
	207
	208	/* I2C RTC */
	209	#define CONFIG_RTC_M41T11 1
	210	#define CONFIG_SYS_I2C_RTC_ADDR 0x68
	211	#define CONFIG_SYS_M41T11_BASE_YEAR 2000
	212
	213	/* GPIO */
	214	#define CONFIG_PCA953X
	215	#define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18
	216	#define CONFIG_SYS_I2C_PCA953X_ADDR1 0x19
	217	#define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0
	218
	219	/* PCA957 @ 0x18 */
	220	#define CONFIG_SYS_PCA953X_BRD_CFG0 0x01
	221	#define CONFIG_SYS_PCA953X_BRD_CFG1 0x02
	222	#define CONFIG_SYS_PCA953X_BRD_CFG2 0x04
	223	#define CONFIG_SYS_PCA953X_XMC_ROOT0 0x08
	224	#define CONFIG_SYS_PCA953X_FLASH_PASS_CS 0x10
72fb68d5	225	#define CONFIG_SYS_PCA953X_NVM_WP 0x20
1f03cbfa PT	226	#define CONFIG_SYS_PCA953X_MONARCH 0x40
	227	#define CONFIG_SYS_PCA953X_EREADY 0x80
	228
	229	/* PCA957 @ 0x19 */
	230	#define CONFIG_SYS_PCA953X_P14_IO0 0x01
	231	#define CONFIG_SYS_PCA953X_P14_IO1 0x02
	232	#define CONFIG_SYS_PCA953X_P14_IO2 0x04
	233	#define CONFIG_SYS_PCA953X_P14_IO3 0x08
	234	#define CONFIG_SYS_PCA953X_P14_IO4 0x10
	235	#define CONFIG_SYS_PCA953X_P14_IO5 0x20
	236	#define CONFIG_SYS_PCA953X_P14_IO6 0x40
	237	#define CONFIG_SYS_PCA953X_P14_IO7 0x80
	238
66a8b440 PT	239	/* 12-bit ADC used to measure CPU diode */
	240	#define CONFIG_SYS_I2C_MAX1237_ADDR 0x34
	241
1f03cbfa PT	242	/*
	243	* General PCI
	244	* Memory space is mapped 1-1, but I/O space must start from 0.
	245	*/
9660c5de PT	246	#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
9660c5de PT	247	#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS
1f03cbfa	248	#define CONFIG_SYS_PCI1_MEM_SIZE 0x40000000 /* 1G */
9660c5de	249	#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
1f03cbfa PT	250	#define CONFIG_SYS_PCI1_IO_PHYS 0xe8000000
	251	#define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 1M */
	252
	253	/*
	254	* Networking options
	255	*/
	256	#define CONFIG_TSEC_ENET /* tsec ethernet support */
	257	#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
1f03cbfa PT	258	#define CONFIG_MII 1 /* MII PHY management */
	259	#define CONFIG_ETHPRIME "eTSEC1"
	260
	261	#define CONFIG_TSEC1 1
	262	#define CONFIG_TSEC1_NAME "eTSEC1"
	263	#define TSEC1_FLAGS TSEC_GIGABIT
	264	#define TSEC1_PHY_ADDR 1
	265	#define TSEC1_PHYIDX 0
	266	#define CONFIG_HAS_ETH0
	267
	268	#define CONFIG_TSEC2 1
	269	#define CONFIG_TSEC2_NAME "eTSEC2"
	270	#define TSEC2_FLAGS TSEC_GIGABIT
	271	#define TSEC2_PHY_ADDR 2
	272	#define TSEC2_PHYIDX 0
	273	#define CONFIG_HAS_ETH1
	274
	275	#define CONFIG_TSEC3 1
	276	#define CONFIG_TSEC3_NAME "eTSEC3"
	277	#define TSEC3_FLAGS TSEC_GIGABIT
	278	#define TSEC3_PHY_ADDR 3
	279	#define TSEC3_PHYIDX 0
	280	#define CONFIG_HAS_ETH2
	281
	282	#define CONFIG_TSEC4 1
	283	#define CONFIG_TSEC4_NAME "eTSEC4"
	284	#define TSEC4_FLAGS TSEC_GIGABIT
	285	#define TSEC4_PHY_ADDR 4
	286	#define TSEC4_PHYIDX 0
	287	#define CONFIG_HAS_ETH3
	288
	289	/*
	290	* BOOTP options
	291	*/
	292	#define CONFIG_BOOTP_BOOTFILESIZE
	293	#define CONFIG_BOOTP_BOOTPATH
	294	#define CONFIG_BOOTP_GATEWAY
	295
	296	/*
	297	* Command configuration.
	298	*/
1f03cbfa	299	#define CONFIG_CMD_DATE
1f03cbfa	300	#define CONFIG_CMD_EEPROM
1f03cbfa	301	#define CONFIG_CMD_JFFS2
1f03cbfa	302	#define CONFIG_CMD_NAND
1f03cbfa PT	303	#define CONFIG_CMD_PCA953X
	304	#define CONFIG_CMD_PCA953X_INFO
	305	#define CONFIG_CMD_PCI
96d61603	306	#define CONFIG_CMD_PCI_ENUM
199e262e	307	#define CONFIG_CMD_REGINFO
1f03cbfa PT	308
	309	/*
	310	* Miscellaneous configurable options
	311	*/
	312	#define CONFIG_SYS_LONGHELP /* undef to save memory */
	313	#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
1f03cbfa PT	314	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
	315	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	316	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	317	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
1f03cbfa	318	#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
5be58f5f	319	#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
1f03cbfa	320	#define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */
1f03cbfa PT	321	#define CONFIG_PANIC_HANG /* do not reset board on panic */
1f03cbfa PT	322	#define CONFIG_PREBOOT /* enable preboot variable */
1f03cbfa PT	323	#define CONFIG_INTEGRITY /* support booting INTEGRITY OS */
	324	#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
	325
	326	/*
	327	* For booting Linux, the board info and command line data
	328	* have to be in the first 16 MB of memory, since this is
	329	* the maximum mapped by the Linux kernel during initialization.
	330	*/
	331	#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
39121c08	332	#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
1f03cbfa	333
1f03cbfa PT	334	/*
	335	* Environment Configuration
	336	*/
	337	#define CONFIG_ENV_IS_IN_FLASH 1
	338	#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k (one sector) for env */
	339	#define CONFIG_ENV_SIZE 0x8000
	340	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - (256 * 1024))
	341
	342	/*
	343	* Flash memory map:
	344	* fff80000 - ffffffff Pri U-Boot (512 KB)
	345	* fff40000 - fff7ffff Pri U-Boot Environment (256 KB)
	346	* fff00000 - fff3ffff Pri FDT (256KB)
	347	* fef00000 - ffefffff Pri OS image (16MB)
	348	* fc000000 - feefffff Pri OS Use/Filesystem (47MB)
	349	*
	350	* fbf80000 - fbffffff Sec U-Boot (512 KB)
	351	* fbf40000 - fbf7ffff Sec U-Boot Environment (256 KB)
	352	* fbf00000 - fbf3ffff Sec FDT (256KB)
	353	* faf00000 - fbefffff Sec OS image (16MB)
	354	* f8000000 - faefffff Sec OS Use/Filesystem (47MB)
	355	*/
5368c55d MV	356	#define CONFIG_UBOOT1_ENV_ADDR __stringify(0xfff80000)
	357	#define CONFIG_UBOOT2_ENV_ADDR __stringify(0xfbf80000)
	358	#define CONFIG_FDT1_ENV_ADDR __stringify(0xfff00000)
	359	#define CONFIG_FDT2_ENV_ADDR __stringify(0xfbf00000)
	360	#define CONFIG_OS1_ENV_ADDR __stringify(0xfef00000)
	361	#define CONFIG_OS2_ENV_ADDR __stringify(0xfaf00000)
1f03cbfa PT	362
	363	#define CONFIG_PROG_UBOOT1 \
	364	"$download_cmd $loadaddr $ubootfile; " \
	365	"if test $? -eq 0; then " \
	366	"protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
	367	"erase "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
	368	"cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; " \
	369	"protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
	370	"cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; " \
	371	"if test $? -ne 0; then " \
	372	"echo PROGRAM FAILED; " \
	373	"else; " \
	374	"echo PROGRAM SUCCEEDED; " \
	375	"fi; " \
	376	"else; " \
	377	"echo DOWNLOAD FAILED; " \
	378	"fi;"
	379
	380	#define CONFIG_PROG_UBOOT2 \
	381	"$download_cmd $loadaddr $ubootfile; " \
	382	"if test $? -eq 0; then " \
	383	"protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
	384	"erase "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
	385	"cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; " \
	386	"protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
	387	"cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; " \
	388	"if test $? -ne 0; then " \
	389	"echo PROGRAM FAILED; " \
	390	"else; " \
	391	"echo PROGRAM SUCCEEDED; " \
	392	"fi; " \
	393	"else; " \
	394	"echo DOWNLOAD FAILED; " \
	395	"fi;"
	396
	397	#define CONFIG_BOOT_OS_NET \
	398	"$download_cmd $osaddr $osfile; " \
	399	"if test $? -eq 0; then " \
	400	"if test -n $fdtaddr; then " \
	401	"$download_cmd $fdtaddr $fdtfile; " \
	402	"if test $? -eq 0; then " \
	403	"bootm $osaddr - $fdtaddr; " \
	404	"else; " \
	405	"echo FDT DOWNLOAD FAILED; " \
	406	"fi; " \
	407	"else; " \
	408	"bootm $osaddr; " \
	409	"fi; " \
	410	"else; " \
	411	"echo OS DOWNLOAD FAILED; " \
	412	"fi;"
	413
	414	#define CONFIG_PROG_OS1 \
	415	"$download_cmd $osaddr $osfile; " \
	416	"if test $? -eq 0; then " \
	417	"erase "CONFIG_OS1_ENV_ADDR" +$filesize; " \
	418	"cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
	419	"cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
	420	"if test $? -ne 0; then " \
	421	"echo OS PROGRAM FAILED; " \
	422	"else; " \
	423	"echo OS PROGRAM SUCCEEDED; " \
	424	"fi; " \
	425	"else; " \
426	"echo OS DOWNLOAD FAILED; " \
427	"fi;"
428
429	#define CONFIG_PROG_OS2 \
430	"$download_cmd $osaddr $osfile; " \
431	"if test $? -eq 0; then " \
432	"erase "CONFIG_OS2_ENV_ADDR" +$filesize; " \
433	"cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
434	"cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
435	"if test $? -ne 0; then " \
436	"echo OS PROGRAM FAILED; " \
437	"else; " \
438	"echo OS PROGRAM SUCCEEDED; " \
439	"fi; " \
440	"else; " \
441	"echo OS DOWNLOAD FAILED; " \
442	"fi;"
443
444	#define CONFIG_PROG_FDT1 \
445	"$download_cmd $fdtaddr $fdtfile; " \
446	"if test $? -eq 0; then " \
447	"erase "CONFIG_FDT1_ENV_ADDR" +$filesize;" \
448	"cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
449	"cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
450	"if test $? -ne 0; then " \
451	"echo FDT PROGRAM FAILED; " \
452	"else; " \
453	"echo FDT PROGRAM SUCCEEDED; " \
454	"fi; " \
455	"else; " \
456	"echo FDT DOWNLOAD FAILED; " \
457	"fi;"
458
459	#define CONFIG_PROG_FDT2 \
460	"$download_cmd $fdtaddr $fdtfile; " \
461	"if test $? -eq 0; then " \
462	"erase "CONFIG_FDT2_ENV_ADDR" +$filesize;" \
463	"cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
464	"cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
465	"if test $? -ne 0; then " \
466	"echo FDT PROGRAM FAILED; " \
467	"else; " \
468	"echo FDT PROGRAM SUCCEEDED; " \
469	"fi; " \
470	"else; " \
471	"echo FDT DOWNLOAD FAILED; " \
472	"fi;"
473
474	#define CONFIG_EXTRA_ENV_SETTINGS \
475	"autoload=yes\0" \
476	"download_cmd=tftp\0" \
477	"console_args=console=ttyS0,115200\0" \
478	"root_args=root=/dev/nfs rw\0" \
479	"misc_args=ip=on\0" \
480	"set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
481	"bootfile=/home/user/file\0" \
c00ac259 PT	482	"osfile=/home/user/board.uImage\0" \
c00ac259 PT	483	"fdtfile=/home/user/board.dtb\0" \
1f03cbfa	484	"ubootfile=/home/user/u-boot.bin\0" \
b24a4f62	485	"fdtaddr=0x1e00000\0" \
1f03cbfa PT	486	"osaddr=0x1000000\0" \
	487	"loadaddr=0x1000000\0" \
	488	"prog_uboot1="CONFIG_PROG_UBOOT1"\0" \
	489	"prog_uboot2="CONFIG_PROG_UBOOT2"\0" \
	490	"prog_os1="CONFIG_PROG_OS1"\0" \
	491	"prog_os2="CONFIG_PROG_OS2"\0" \
	492	"prog_fdt1="CONFIG_PROG_FDT1"\0" \
	493	"prog_fdt2="CONFIG_PROG_FDT2"\0" \
	494	"bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \
	495	"bootcmd_flash1=run set_bootargs; " \
	496	"bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
	497	"bootcmd_flash2=run set_bootargs; " \
	498	"bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
	499	"bootcmd=run bootcmd_flash1\0"
	500	#endif /* __CONFIG_H */