[people/ms/u-boot.git] / include / configs / xpedite520x.h

/*
 * Copyright 2008 Extreme Engineering Solutions, Inc.
 * Copyright 2004-2008 Freescale Semiconductor, Inc.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*
 * xpedite520x board configuration file
 */
#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 */
#define CONFIG_SYS_BOARD_NAME	"XPedite5200"
#define CONFIG_SYS_FORM_PMC_XMC	1
#define CONFIG_BOARD_EARLY_INIT_R	/* Call board_pre_init */

#define CONFIG_PCI_SCAN_SHOW	1	/* show pci devices on startup */
#define CONFIG_PCI1		1	/* PCI controller 1 */
#define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
#define CONFIG_PCI_INDIRECT_BRIDGE 1	/* indirect PCI bridge support */
#define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */

/*
 * DDR config
 */
#undef CONFIG_FSL_DDR_INTERACTIVE
#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
#define CONFIG_DDR_SPD
#define CONFIG_MEM_INIT_VALUE		0xdeadbeef
#define SPD_EEPROM_ADDRESS		0x54
#define CONFIG_DIMM_SLOTS_PER_CTLR	1
#define CONFIG_CHIP_SELECTS_PER_CTRL	2
#define CONFIG_DDR_ECC
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_VERY_BIG_RAM

#define CONFIG_SYS_CLK_FREQ	66666666

/*
 * These can be toggled for performance analysis, otherwise use default.
 */
#define CONFIG_L2_CACHE			/* toggle L2 cache */
#define CONFIG_BTB			/* toggle branch predition */
#define CONFIG_ENABLE_36BIT_PHYS	1

#define CONFIG_SYS_CCSRBAR		0xef000000
#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR

/*
 * Diagnostics
 */
#define CONFIG_SYS_ALT_MEMTEST
#define CONFIG_SYS_MEMTEST_START	0x10000000
#define CONFIG_SYS_MEMTEST_END		0x20000000
#define CONFIG_POST			(CONFIG_SYS_POST_MEMORY | \
					 CONFIG_SYS_POST_I2C)
#define I2C_ADDR_LIST			{CONFIG_SYS_I2C_MAX1237_ADDR,	\
					 CONFIG_SYS_I2C_EEPROM_ADDR,	\
					 CONFIG_SYS_I2C_PCA953X_ADDR0,	\
					 CONFIG_SYS_I2C_PCA953X_ADDR1,	\
					 CONFIG_SYS_I2C_RTC_ADDR}

/*
 * Memory map
 * 0x0000_0000	0x7fff_ffff	DDR			2G Cacheable
 * 0x8000_0000	0xbfff_ffff	PCI1 Mem		1G non-cacheable
 * 0xe000_0000	0xe7ff_ffff	SRAM/SSRAM/L1 Cache	128M non-cacheable
 * 0xe800_0000	0xe87f_ffff	PCI1 IO			8M non-cacheable
 * 0xef00_0000	0xef0f_ffff	CCSR/IMMR		1M non-cacheable
 * 0xef80_0000	0xef8f_ffff	NAND Flash		1M non-cacheable
 * 0xf800_0000	0xfbff_ffff	NOR Flash 2		64M non-cacheable
 * 0xfc00_0000	0xffff_ffff	NOR Flash 1		64M non-cacheable
 */

#define CONFIG_SYS_LBC_LCRR	(LCRR_CLKDIV_8 | LCRR_EADC_3)

/*
 * NAND flash configuration
 */
#define CONFIG_SYS_NAND_BASE		0xef800000
#define CONFIG_SYS_NAND_BASE2		0xef840000 /* Unused at this time */
#define CONFIG_SYS_MAX_NAND_DEVICE	1
#define CONFIG_NAND_ACTL
#define CONFIG_SYS_NAND_ACTL_CLE	(1 << 3)	/* ADDR3 is CLE */
#define CONFIG_SYS_NAND_ACTL_ALE	(1 << 4)	/* ADDR4 is ALE */
#define CONFIG_SYS_NAND_ACTL_NCE	(0)		/* NCE not controlled by ADDR */
#define CONFIG_SYS_NAND_ACTL_DELAY	25

/*
 * NOR flash configuration
 */
#define CONFIG_SYS_FLASH_BASE		0xfc000000
#define CONFIG_SYS_FLASH_BASE2		0xf8000000
#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
#define CONFIG_SYS_MAX_FLASH_BANKS	2		/* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT	1024		/* sectors per device */
#define CONFIG_SYS_FLASH_ERASE_TOUT	60000		/* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500		/* Flash Write Timeout (ms) */
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
#define CONFIG_SYS_FLASH_AUTOPROTECT_LIST	{ {0xfff40000, 0xc0000}, \
						  {0xfbf40000, 0xc0000} }
#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */

/*
 * Chip select configuration
 */
/* NOR Flash 0 on CS0 */
#define CONFIG_SYS_BR0_PRELIM	(CONFIG_SYS_FLASH_BASE	| \
				 BR_PS_16		| \
				 BR_V)
#define CONFIG_SYS_OR0_PRELIM	(OR_AM_64MB		| \
				 OR_GPCM_ACS_DIV4	| \
				 OR_GPCM_SCY_8)

/* NOR Flash 1 on CS1 */
#define CONFIG_SYS_BR1_PRELIM	(CONFIG_SYS_FLASH_BASE2	| \
				 BR_PS_16		| \
				 BR_V)
#define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_OR0_PRELIM

/* NAND flash on CS2 */
#define CONFIG_SYS_BR2_PRELIM	(CONFIG_SYS_NAND_BASE	| \
				 BR_PS_8		| \
				 BR_V)

/* NAND flash on CS2 */
#define CONFIG_SYS_OR2_PRELIM	(OR_AM_256KB		| \
				 OR_GPCM_BCTLD		| \
				 OR_GPCM_CSNT		| \
				 OR_GPCM_ACS_DIV4	| \
				 OR_GPCM_SCY_4		| \
				 OR_GPCM_TRLX		| \
				 OR_GPCM_EHTR)

/* NAND flash on CS3 */
#define CONFIG_SYS_BR3_PRELIM	(CONFIG_SYS_NAND_BASE2	| \
				 BR_PS_8		| \
				 BR_V)
#define CONFIG_SYS_OR3_PRELIM	CONFIG_SYS_OR2_PRELIM

/*
 * Use L1 as initial stack
 */
#define CONFIG_SYS_INIT_RAM_LOCK	1
#define CONFIG_SYS_INIT_RAM_ADDR	0xe0000000
#define CONFIG_SYS_INIT_RAM_SIZE		0x4000

#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)	/* Reserve 512 KB for Mon */
#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)	/* Reserved for malloc */

/*
 * Serial Port
 */
#define CONFIG_CONS_INDEX		1
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
#define CONFIG_SYS_BAUDRATE_TABLE	\
	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
#define CONFIG_LOADS_ECHO		1	/* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */

/*
 * I2C
 */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED	400000
#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
#define CONFIG_SYS_FSL_I2C2_SPEED	400000
#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100

/* I2C EEPROM */
#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	6	/* 64 byte pages */
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* take up to 10 msec */

/* I2C RTC */
#define CONFIG_RTC_M41T11			1
#define CONFIG_SYS_I2C_RTC_ADDR			0x68
#define CONFIG_SYS_M41T11_BASE_YEAR		2000

/* GPIO */
#define CONFIG_PCA953X
#define CONFIG_SYS_I2C_PCA953X_ADDR0		0x18
#define CONFIG_SYS_I2C_PCA953X_ADDR1		0x19
#define CONFIG_SYS_I2C_PCA953X_ADDR		CONFIG_SYS_I2C_PCA953X_ADDR0

/* PCA957 @ 0x18 */
#define CONFIG_SYS_PCA953X_BRD_CFG0		0x01
#define CONFIG_SYS_PCA953X_BRD_CFG1		0x02
#define CONFIG_SYS_PCA953X_BRD_CFG2		0x04
#define CONFIG_SYS_PCA953X_XMC_ROOT0		0x08
#define CONFIG_SYS_PCA953X_FLASH_PASS_CS	0x10
#define CONFIG_SYS_PCA953X_NVM_WP		0x20
#define CONFIG_SYS_PCA953X_MONARCH		0x40
#define CONFIG_SYS_PCA953X_EREADY		0x80

/* PCA957 @ 0x19 */
#define CONFIG_SYS_PCA953X_P14_IO0		0x01
#define CONFIG_SYS_PCA953X_P14_IO1		0x02
#define CONFIG_SYS_PCA953X_P14_IO2		0x04
#define CONFIG_SYS_PCA953X_P14_IO3		0x08
#define CONFIG_SYS_PCA953X_P14_IO4		0x10
#define CONFIG_SYS_PCA953X_P14_IO5		0x20
#define CONFIG_SYS_PCA953X_P14_IO6		0x40
#define CONFIG_SYS_PCA953X_P14_IO7		0x80

/* 12-bit ADC used to measure CPU diode */
#define CONFIG_SYS_I2C_MAX1237_ADDR		0x34

/*
 * General PCI
 * Memory space is mapped 1-1, but I/O space must start from 0.
 */
#define CONFIG_SYS_PCI1_MEM_BUS		0x80000000
#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BUS
#define CONFIG_SYS_PCI1_MEM_SIZE	0x40000000	/* 1G */
#define CONFIG_SYS_PCI1_IO_BUS		0x00000000
#define CONFIG_SYS_PCI1_IO_PHYS		0xe8000000
#define CONFIG_SYS_PCI1_IO_SIZE		0x00800000	/* 1M */

/*
 * Networking options
 */
#define CONFIG_TSEC_ENET		/* tsec ethernet support */
#define CONFIG_MII		1	/* MII PHY management */
#define CONFIG_ETHPRIME		"eTSEC1"

#define CONFIG_TSEC1		1
#define CONFIG_TSEC1_NAME	"eTSEC1"
#define TSEC1_FLAGS		TSEC_GIGABIT
#define TSEC1_PHY_ADDR		1
#define TSEC1_PHYIDX		0
#define CONFIG_HAS_ETH0

#define CONFIG_TSEC2		1
#define CONFIG_TSEC2_NAME	"eTSEC2"
#define TSEC2_FLAGS		TSEC_GIGABIT
#define TSEC2_PHY_ADDR		2
#define TSEC2_PHYIDX		0
#define CONFIG_HAS_ETH1

#define CONFIG_TSEC3	1
#define CONFIG_TSEC3_NAME	"eTSEC3"
#define TSEC3_FLAGS		TSEC_GIGABIT
#define TSEC3_PHY_ADDR		3
#define TSEC3_PHYIDX		0
#define CONFIG_HAS_ETH2

#define CONFIG_TSEC4	1
#define CONFIG_TSEC4_NAME	"eTSEC4"
#define TSEC4_FLAGS		TSEC_GIGABIT
#define TSEC4_PHY_ADDR		4
#define TSEC4_PHYIDX		0
#define CONFIG_HAS_ETH3

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
#define CONFIG_LOADADDR		0x1000000	/* default location for tftp and bootm */
#define CONFIG_PREBOOT				/* enable preboot variable */
#define CONFIG_INTEGRITY			/* support booting INTEGRITY OS */
#define CONFIG_INTERRUPTS		/* enable pci, srio, ddr interrupts */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 16 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ	(16 << 20)	/* Initial Memory map for Linux*/
#define CONFIG_SYS_BOOTM_LEN	(16 << 20)	/* Increase max gunzip size */

/*
 * Environment Configuration
 */
#define CONFIG_ENV_SECT_SIZE	0x20000		/* 128k (one sector) for env */
#define CONFIG_ENV_SIZE		0x8000
#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - (256 * 1024))

/*
 * Flash memory map:
 * fff80000 - ffffffff     Pri U-Boot (512 KB)
 * fff40000 - fff7ffff     Pri U-Boot Environment (256 KB)
 * fff00000 - fff3ffff     Pri FDT (256KB)
 * fef00000 - ffefffff     Pri OS image (16MB)
 * fc000000 - feefffff     Pri OS Use/Filesystem (47MB)
 *
 * fbf80000 - fbffffff     Sec U-Boot (512 KB)
 * fbf40000 - fbf7ffff     Sec U-Boot Environment (256 KB)
 * fbf00000 - fbf3ffff     Sec FDT (256KB)
 * faf00000 - fbefffff     Sec OS image (16MB)
 * f8000000 - faefffff     Sec OS Use/Filesystem (47MB)
 */
#define CONFIG_UBOOT1_ENV_ADDR	__stringify(0xfff80000)
#define CONFIG_UBOOT2_ENV_ADDR	__stringify(0xfbf80000)
#define CONFIG_FDT1_ENV_ADDR	__stringify(0xfff00000)
#define CONFIG_FDT2_ENV_ADDR	__stringify(0xfbf00000)
#define CONFIG_OS1_ENV_ADDR	__stringify(0xfef00000)
#define CONFIG_OS2_ENV_ADDR	__stringify(0xfaf00000)

#define CONFIG_PROG_UBOOT1						\
	"$download_cmd $loadaddr $ubootfile; "				\
	"if test $? -eq 0; then "					\
		"protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; "		\
		"erase "CONFIG_UBOOT1_ENV_ADDR" +80000; "		\
		"cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; "	\
		"protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; "		\
		"cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; "	\
		"if test $? -ne 0; then "				\
			"echo PROGRAM FAILED; "				\
		"else; "						\
			"echo PROGRAM SUCCEEDED; "			\
		"fi; "							\
	"else; "							\
		"echo DOWNLOAD FAILED; "				\
	"fi;"

#define CONFIG_PROG_UBOOT2						\
	"$download_cmd $loadaddr $ubootfile; "				\
	"if test $? -eq 0; then "					\
		"protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; "		\
		"erase "CONFIG_UBOOT2_ENV_ADDR" +80000; "		\
		"cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; "	\
		"protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; "		\
		"cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; "	\
		"if test $? -ne 0; then "				\
			"echo PROGRAM FAILED; "				\
		"else; "						\
			"echo PROGRAM SUCCEEDED; "			\
		"fi; "							\
	"else; "							\
		"echo DOWNLOAD FAILED; "				\
	"fi;"

#define CONFIG_BOOT_OS_NET						\
	"$download_cmd $osaddr $osfile; "				\
	"if test $? -eq 0; then "					\
		"if test -n $fdtaddr; then "				\
			"$download_cmd $fdtaddr $fdtfile; "		\
			"if test $? -eq 0; then "			\
				"bootm $osaddr - $fdtaddr; "		\
			"else; "					\
				"echo FDT DOWNLOAD FAILED; "		\
			"fi; "						\
		"else; "						\
			"bootm $osaddr; "				\
		"fi; "							\
	"else; "							\
		"echo OS DOWNLOAD FAILED; "				\
	"fi;"

#define CONFIG_PROG_OS1							\
	"$download_cmd $osaddr $osfile; "				\
	"if test $? -eq 0; then "					\
		"erase "CONFIG_OS1_ENV_ADDR" +$filesize; "		\
		"cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; "	\
		"cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; "	\
		"if test $? -ne 0; then "				\
			"echo OS PROGRAM FAILED; "			\
		"else; "						\
			"echo OS PROGRAM SUCCEEDED; "			\
		"fi; "							\
	"else; "							\
		"echo OS DOWNLOAD FAILED; "				\
	"fi;"

#define CONFIG_PROG_OS2							\
	"$download_cmd $osaddr $osfile; "				\
	"if test $? -eq 0; then "					\
		"erase "CONFIG_OS2_ENV_ADDR" +$filesize; "		\
		"cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; "	\
		"cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; "	\
		"if test $? -ne 0; then "				\
			"echo OS PROGRAM FAILED; "			\
		"else; "						\
			"echo OS PROGRAM SUCCEEDED; "			\
		"fi; "							\
	"else; "							\
		"echo OS DOWNLOAD FAILED; "				\
	"fi;"

#define CONFIG_PROG_FDT1						\
	"$download_cmd $fdtaddr $fdtfile; "				\
	"if test $? -eq 0; then "					\
		"erase "CONFIG_FDT1_ENV_ADDR" +$filesize;"		\
		"cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; "	\
		"cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; "	\
		"if test $? -ne 0; then "				\
			"echo FDT PROGRAM FAILED; "			\
		"else; "						\
			"echo FDT PROGRAM SUCCEEDED; "			\
		"fi; "							\
	"else; "							\
		"echo FDT DOWNLOAD FAILED; "				\
	"fi;"

#define CONFIG_PROG_FDT2						\
	"$download_cmd $fdtaddr $fdtfile; "				\
	"if test $? -eq 0; then "					\
		"erase "CONFIG_FDT2_ENV_ADDR" +$filesize;"		\
		"cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; "	\
		"cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; "	\
		"if test $? -ne 0; then "				\
			"echo FDT PROGRAM FAILED; "			\
		"else; "						\
			"echo FDT PROGRAM SUCCEEDED; "			\
		"fi; "							\
	"else; "							\
		"echo FDT DOWNLOAD FAILED; "				\
	"fi;"

#define	CONFIG_EXTRA_ENV_SETTINGS					\
	"autoload=yes\0"						\
	"download_cmd=tftp\0"						\
	"console_args=console=ttyS0,115200\0"				\
	"root_args=root=/dev/nfs rw\0"					\
	"misc_args=ip=on\0"						\
	"set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
	"bootfile=/home/user/file\0"					\
	"osfile=/home/user/board.uImage\0"				\
	"fdtfile=/home/user/board.dtb\0"				\
	"ubootfile=/home/user/u-boot.bin\0"				\
	"fdtaddr=0x1e00000\0"						\
	"osaddr=0x1000000\0"						\
	"loadaddr=0x1000000\0"						\
	"prog_uboot1="CONFIG_PROG_UBOOT1"\0"				\
	"prog_uboot2="CONFIG_PROG_UBOOT2"\0"				\
	"prog_os1="CONFIG_PROG_OS1"\0"					\
	"prog_os2="CONFIG_PROG_OS2"\0"					\
	"prog_fdt1="CONFIG_PROG_FDT1"\0"				\
	"prog_fdt2="CONFIG_PROG_FDT2"\0"				\
	"bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0"		\
	"bootcmd_flash1=run set_bootargs; "				\
		"bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
	"bootcmd_flash2=run set_bootargs; "				\
		"bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
	"bootcmd=run bootcmd_flash1\0"
#endif	/* __CONFIG_H */
Commit	Line	Data
1f03cbfa PT	1	/*
	2	* Copyright 2008 Extreme Engineering Solutions, Inc.
	3	* Copyright 2004-2008 Freescale Semiconductor, Inc.
	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
1f03cbfa PT	6	*/
	7
	8	/*
c00ac259	9	* xpedite520x board configuration file
1f03cbfa PT	10	*/
	11	#ifndef __CONFIG_H
	12	#define __CONFIG_H
	13
	14	/*
	15	* High Level Configuration Options
	16	*/
1f03cbfa	17	#define CONFIG_SYS_BOARD_NAME "XPedite5200"
92af6549	18	#define CONFIG_SYS_FORM_PMC_XMC 1
1f03cbfa	19	#define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */
1f03cbfa	20
1f03cbfa PT	21	#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
	22	#define CONFIG_PCI1 1 /* PCI controller 1 */
	23	#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
842033e6	24	#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
1f03cbfa	25	#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
1f03cbfa PT	26
	27	/*
	28	* DDR config
	29	*/
1f03cbfa PT	30	#undef CONFIG_FSL_DDR_INTERACTIVE
	31	#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
	32	#define CONFIG_DDR_SPD
	33	#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
	34	#define SPD_EEPROM_ADDRESS 0x54
1f03cbfa PT	35	#define CONFIG_DIMM_SLOTS_PER_CTLR 1
	36	#define CONFIG_CHIP_SELECTS_PER_CTRL 2
	37	#define CONFIG_DDR_ECC
	38	#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
	39	#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
	40	#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
	41	#define CONFIG_VERY_BIG_RAM
	42
	43	#define CONFIG_SYS_CLK_FREQ 66666666
	44
	45	/*
	46	* These can be toggled for performance analysis, otherwise use default.
	47	*/
	48	#define CONFIG_L2_CACHE /* toggle L2 cache */
	49	#define CONFIG_BTB /* toggle branch predition */
	50	#define CONFIG_ENABLE_36BIT_PHYS 1
	51
e46fedfe TT	52	#define CONFIG_SYS_CCSRBAR 0xef000000
e46fedfe TT	53	#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
1f03cbfa PT	54
	55	/*
	56	* Diagnostics
	57	*/
	58	#define CONFIG_SYS_ALT_MEMTEST
	59	#define CONFIG_SYS_MEMTEST_START 0x10000000
	60	#define CONFIG_SYS_MEMTEST_END 0x20000000
66a8b440 PT	61	#define CONFIG_POST (CONFIG_SYS_POST_MEMORY \| \
	62	CONFIG_SYS_POST_I2C)
	63	#define I2C_ADDR_LIST {CONFIG_SYS_I2C_MAX1237_ADDR, \
	64	CONFIG_SYS_I2C_EEPROM_ADDR, \
	65	CONFIG_SYS_I2C_PCA953X_ADDR0, \
	66	CONFIG_SYS_I2C_PCA953X_ADDR1, \
	67	CONFIG_SYS_I2C_RTC_ADDR}
1f03cbfa PT	68
	69	/*
	70	* Memory map
	71	* 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
	72	* 0x8000_0000 0xbfff_ffff PCI1 Mem 1G non-cacheable
	73	* 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable
	74	* 0xe800_0000 0xe87f_ffff PCI1 IO 8M non-cacheable
	75	* 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable
	76	* 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable
	77	* 0xf800_0000 0xfbff_ffff NOR Flash 2 64M non-cacheable
	78	* 0xfc00_0000 0xffff_ffff NOR Flash 1 64M non-cacheable
	79	*/
	80
202d9487	81	#define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_8 \| LCRR_EADC_3)
1f03cbfa PT	82
	83	/*
	84	* NAND flash configuration
	85	*/
	86	#define CONFIG_SYS_NAND_BASE 0xef800000
	87	#define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */
	88	#define CONFIG_SYS_MAX_NAND_DEVICE 1
	89	#define CONFIG_NAND_ACTL
	90	#define CONFIG_SYS_NAND_ACTL_CLE (1 << 3) /* ADDR3 is CLE */
	91	#define CONFIG_SYS_NAND_ACTL_ALE (1 << 4) /* ADDR4 is ALE */
	92	#define CONFIG_SYS_NAND_ACTL_NCE (0) /* NCE not controlled by ADDR */
	93	#define CONFIG_SYS_NAND_ACTL_DELAY 25
	94
	95	/*
	96	* NOR flash configuration
	97	*/
	98	#define CONFIG_SYS_FLASH_BASE 0xfc000000
	99	#define CONFIG_SYS_FLASH_BASE2 0xf8000000
	100	#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
	101	#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
	102	#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
	103	#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
	104	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
	105	#define CONFIG_FLASH_CFI_DRIVER
	106	#define CONFIG_SYS_FLASH_CFI
5ff82100	107	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
1f03cbfa PT	108	#define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff40000, 0xc0000}, \
1f03cbfa PT	109	{0xfbf40000, 0xc0000} }
14d0a02a	110	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
1f03cbfa PT	111
	112	/*
	113	* Chip select configuration
	114	*/
	115	/* NOR Flash 0 on CS0 */
	116	#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \| \
	117	BR_PS_16 \| \
	118	BR_V)
	119	#define CONFIG_SYS_OR0_PRELIM (OR_AM_64MB \| \
	120	OR_GPCM_ACS_DIV4 \| \
	121	OR_GPCM_SCY_8)
	122
	123	/* NOR Flash 1 on CS1 */
	124	#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 \| \
	125	BR_PS_16 \| \
	126	BR_V)
	127	#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
	128
	129	/* NAND flash on CS2 */
	130	#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE \| \
	131	BR_PS_8 \| \
	132	BR_V)
	133
	134	/* NAND flash on CS2 */
	135	#define CONFIG_SYS_OR2_PRELIM (OR_AM_256KB \| \
	136	OR_GPCM_BCTLD \| \
	137	OR_GPCM_CSNT \| \
	138	OR_GPCM_ACS_DIV4 \| \
	139	OR_GPCM_SCY_4 \| \
	140	OR_GPCM_TRLX \| \
	141	OR_GPCM_EHTR)
	142
	143	/* NAND flash on CS3 */
	144	#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE2 \| \
	145	BR_PS_8 \| \
	146	BR_V)
	147	#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
	148
	149	/*
	150	* Use L1 as initial stack
	151	*/
	152	#define CONFIG_SYS_INIT_RAM_LOCK 1
	153	#define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000
553f0982	154	#define CONFIG_SYS_INIT_RAM_SIZE 0x4000
1f03cbfa	155
25ddd1fb	156	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
1f03cbfa PT	157	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
	158
	159	#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */
	160	#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
	161
	162	/*
	163	* Serial Port
	164	*/
	165	#define CONFIG_CONS_INDEX 1
1f03cbfa PT	166	#define CONFIG_SYS_NS16550_SERIAL
	167	#define CONFIG_SYS_NS16550_REG_SIZE 1
	168	#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
	169	#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
	170	#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
	171	#define CONFIG_SYS_BAUDRATE_TABLE \
	172	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
1f03cbfa PT	173	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
	174	#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
	175
1f03cbfa PT	176	/*
	177	* I2C
	178	*/
00f792e0 HS	179	#define CONFIG_SYS_I2C
	180	#define CONFIG_SYS_I2C_FSL
	181	#define CONFIG_SYS_FSL_I2C_SPEED 400000
	182	#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
	183	#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
	184	#define CONFIG_SYS_FSL_I2C2_SPEED 400000
	185	#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
	186	#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
1f03cbfa PT	187
	188	/* I2C EEPROM */
	189	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
	190	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
	191	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */
	192	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */
	193
	194	/* I2C RTC */
	195	#define CONFIG_RTC_M41T11 1
	196	#define CONFIG_SYS_I2C_RTC_ADDR 0x68
	197	#define CONFIG_SYS_M41T11_BASE_YEAR 2000
	198
	199	/* GPIO */
	200	#define CONFIG_PCA953X
	201	#define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18
	202	#define CONFIG_SYS_I2C_PCA953X_ADDR1 0x19
	203	#define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0
	204
	205	/* PCA957 @ 0x18 */
	206	#define CONFIG_SYS_PCA953X_BRD_CFG0 0x01
	207	#define CONFIG_SYS_PCA953X_BRD_CFG1 0x02
	208	#define CONFIG_SYS_PCA953X_BRD_CFG2 0x04
	209	#define CONFIG_SYS_PCA953X_XMC_ROOT0 0x08
	210	#define CONFIG_SYS_PCA953X_FLASH_PASS_CS 0x10
72fb68d5	211	#define CONFIG_SYS_PCA953X_NVM_WP 0x20
1f03cbfa PT	212	#define CONFIG_SYS_PCA953X_MONARCH 0x40
	213	#define CONFIG_SYS_PCA953X_EREADY 0x80
	214
	215	/* PCA957 @ 0x19 */
	216	#define CONFIG_SYS_PCA953X_P14_IO0 0x01
	217	#define CONFIG_SYS_PCA953X_P14_IO1 0x02
	218	#define CONFIG_SYS_PCA953X_P14_IO2 0x04
	219	#define CONFIG_SYS_PCA953X_P14_IO3 0x08
	220	#define CONFIG_SYS_PCA953X_P14_IO4 0x10
	221	#define CONFIG_SYS_PCA953X_P14_IO5 0x20
	222	#define CONFIG_SYS_PCA953X_P14_IO6 0x40
	223	#define CONFIG_SYS_PCA953X_P14_IO7 0x80
	224
66a8b440 PT	225	/* 12-bit ADC used to measure CPU diode */
	226	#define CONFIG_SYS_I2C_MAX1237_ADDR 0x34
	227
1f03cbfa PT	228	/*
	229	* General PCI
	230	* Memory space is mapped 1-1, but I/O space must start from 0.
	231	*/
9660c5de PT	232	#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
9660c5de PT	233	#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS
1f03cbfa	234	#define CONFIG_SYS_PCI1_MEM_SIZE 0x40000000 /* 1G */
9660c5de	235	#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
1f03cbfa PT	236	#define CONFIG_SYS_PCI1_IO_PHYS 0xe8000000
	237	#define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 1M */
	238
	239	/*
	240	* Networking options
	241	*/
	242	#define CONFIG_TSEC_ENET /* tsec ethernet support */
1f03cbfa PT	243	#define CONFIG_MII 1 /* MII PHY management */
	244	#define CONFIG_ETHPRIME "eTSEC1"
	245
	246	#define CONFIG_TSEC1 1
	247	#define CONFIG_TSEC1_NAME "eTSEC1"
	248	#define TSEC1_FLAGS TSEC_GIGABIT
	249	#define TSEC1_PHY_ADDR 1
	250	#define TSEC1_PHYIDX 0
	251	#define CONFIG_HAS_ETH0
	252
	253	#define CONFIG_TSEC2 1
	254	#define CONFIG_TSEC2_NAME "eTSEC2"
	255	#define TSEC2_FLAGS TSEC_GIGABIT
	256	#define TSEC2_PHY_ADDR 2
	257	#define TSEC2_PHYIDX 0
	258	#define CONFIG_HAS_ETH1
	259
	260	#define CONFIG_TSEC3 1
	261	#define CONFIG_TSEC3_NAME "eTSEC3"
	262	#define TSEC3_FLAGS TSEC_GIGABIT
	263	#define TSEC3_PHY_ADDR 3
	264	#define TSEC3_PHYIDX 0
	265	#define CONFIG_HAS_ETH2
	266
	267	#define CONFIG_TSEC4 1
	268	#define CONFIG_TSEC4_NAME "eTSEC4"
	269	#define TSEC4_FLAGS TSEC_GIGABIT
	270	#define TSEC4_PHY_ADDR 4
	271	#define TSEC4_PHYIDX 0
	272	#define CONFIG_HAS_ETH3
	273
	274	/*
	275	* BOOTP options
	276	*/
	277	#define CONFIG_BOOTP_BOOTFILESIZE
1f03cbfa	278
1f03cbfa PT	279	/*
	280	* Miscellaneous configurable options
	281	*/
1f03cbfa	282	#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
1f03cbfa	283	#define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */
1f03cbfa	284	#define CONFIG_PREBOOT /* enable preboot variable */
1f03cbfa PT	285	#define CONFIG_INTEGRITY /* support booting INTEGRITY OS */
	286	#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
	287
	288	/*
	289	* For booting Linux, the board info and command line data
	290	* have to be in the first 16 MB of memory, since this is
	291	* the maximum mapped by the Linux kernel during initialization.
	292	*/
	293	#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
39121c08	294	#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
1f03cbfa	295
1f03cbfa PT	296	/*
	297	* Environment Configuration
	298	*/
1f03cbfa PT	299	#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k (one sector) for env */
	300	#define CONFIG_ENV_SIZE 0x8000
	301	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - (256 * 1024))
	302
	303	/*
	304	* Flash memory map:
	305	* fff80000 - ffffffff Pri U-Boot (512 KB)
	306	* fff40000 - fff7ffff Pri U-Boot Environment (256 KB)
	307	* fff00000 - fff3ffff Pri FDT (256KB)
	308	* fef00000 - ffefffff Pri OS image (16MB)
	309	* fc000000 - feefffff Pri OS Use/Filesystem (47MB)
	310	*
	311	* fbf80000 - fbffffff Sec U-Boot (512 KB)
	312	* fbf40000 - fbf7ffff Sec U-Boot Environment (256 KB)
	313	* fbf00000 - fbf3ffff Sec FDT (256KB)
	314	* faf00000 - fbefffff Sec OS image (16MB)
	315	* f8000000 - faefffff Sec OS Use/Filesystem (47MB)
	316	*/
5368c55d MV	317	#define CONFIG_UBOOT1_ENV_ADDR __stringify(0xfff80000)
	318	#define CONFIG_UBOOT2_ENV_ADDR __stringify(0xfbf80000)
	319	#define CONFIG_FDT1_ENV_ADDR __stringify(0xfff00000)
	320	#define CONFIG_FDT2_ENV_ADDR __stringify(0xfbf00000)
	321	#define CONFIG_OS1_ENV_ADDR __stringify(0xfef00000)
	322	#define CONFIG_OS2_ENV_ADDR __stringify(0xfaf00000)
1f03cbfa PT	323
	324	#define CONFIG_PROG_UBOOT1 \
	325	"$download_cmd $loadaddr $ubootfile; " \
	326	"if test $? -eq 0; then " \
	327	"protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
	328	"erase "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
	329	"cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; " \
	330	"protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
	331	"cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; " \
	332	"if test $? -ne 0; then " \
	333	"echo PROGRAM FAILED; " \
	334	"else; " \
	335	"echo PROGRAM SUCCEEDED; " \
	336	"fi; " \
	337	"else; " \
	338	"echo DOWNLOAD FAILED; " \
	339	"fi;"
	340
	341	#define CONFIG_PROG_UBOOT2 \
	342	"$download_cmd $loadaddr $ubootfile; " \
	343	"if test $? -eq 0; then " \
	344	"protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
	345	"erase "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
	346	"cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; " \
	347	"protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
	348	"cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; " \
	349	"if test $? -ne 0; then " \
	350	"echo PROGRAM FAILED; " \
	351	"else; " \
	352	"echo PROGRAM SUCCEEDED; " \
	353	"fi; " \
	354	"else; " \
	355	"echo DOWNLOAD FAILED; " \
	356	"fi;"
	357
	358	#define CONFIG_BOOT_OS_NET \
	359	"$download_cmd $osaddr $osfile; " \
	360	"if test $? -eq 0; then " \
	361	"if test -n $fdtaddr; then " \
	362	"$download_cmd $fdtaddr $fdtfile; " \
	363	"if test $? -eq 0; then " \
	364	"bootm $osaddr - $fdtaddr; " \
	365	"else; " \
	366	"echo FDT DOWNLOAD FAILED; " \
	367	"fi; " \
	368	"else; " \
	369	"bootm $osaddr; " \
	370	"fi; " \
	371	"else; " \
	372	"echo OS DOWNLOAD FAILED; " \
	373	"fi;"
	374
	375	#define CONFIG_PROG_OS1 \
	376	"$download_cmd $osaddr $osfile; " \
	377	"if test $? -eq 0; then " \
	378	"erase "CONFIG_OS1_ENV_ADDR" +$filesize; " \
	379	"cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
	380	"cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
	381	"if test $? -ne 0; then " \
	382	"echo OS PROGRAM FAILED; " \
	383	"else; " \
	384	"echo OS PROGRAM SUCCEEDED; " \
	385	"fi; " \
	386	"else; " \
387	"echo OS DOWNLOAD FAILED; " \
388	"fi;"
389
390	#define CONFIG_PROG_OS2 \
391	"$download_cmd $osaddr $osfile; " \
392	"if test $? -eq 0; then " \
393	"erase "CONFIG_OS2_ENV_ADDR" +$filesize; " \
394	"cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
395	"cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
396	"if test $? -ne 0; then " \
397	"echo OS PROGRAM FAILED; " \
398	"else; " \
399	"echo OS PROGRAM SUCCEEDED; " \
400	"fi; " \
401	"else; " \
402	"echo OS DOWNLOAD FAILED; " \
403	"fi;"
404
405	#define CONFIG_PROG_FDT1 \
406	"$download_cmd $fdtaddr $fdtfile; " \
407	"if test $? -eq 0; then " \
408	"erase "CONFIG_FDT1_ENV_ADDR" +$filesize;" \
409	"cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
410	"cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
411	"if test $? -ne 0; then " \
412	"echo FDT PROGRAM FAILED; " \
413	"else; " \
414	"echo FDT PROGRAM SUCCEEDED; " \
415	"fi; " \
416	"else; " \
417	"echo FDT DOWNLOAD FAILED; " \
418	"fi;"
419
420	#define CONFIG_PROG_FDT2 \
421	"$download_cmd $fdtaddr $fdtfile; " \
422	"if test $? -eq 0; then " \
423	"erase "CONFIG_FDT2_ENV_ADDR" +$filesize;" \
424	"cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
425	"cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
426	"if test $? -ne 0; then " \
427	"echo FDT PROGRAM FAILED; " \
428	"else; " \
429	"echo FDT PROGRAM SUCCEEDED; " \
430	"fi; " \
431	"else; " \
432	"echo FDT DOWNLOAD FAILED; " \
433	"fi;"
434
435	#define CONFIG_EXTRA_ENV_SETTINGS \
436	"autoload=yes\0" \
437	"download_cmd=tftp\0" \
438	"console_args=console=ttyS0,115200\0" \
439	"root_args=root=/dev/nfs rw\0" \
440	"misc_args=ip=on\0" \
441	"set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
442	"bootfile=/home/user/file\0" \
c00ac259 PT	443	"osfile=/home/user/board.uImage\0" \
c00ac259 PT	444	"fdtfile=/home/user/board.dtb\0" \
1f03cbfa	445	"ubootfile=/home/user/u-boot.bin\0" \
b24a4f62	446	"fdtaddr=0x1e00000\0" \
1f03cbfa PT	447	"osaddr=0x1000000\0" \
	448	"loadaddr=0x1000000\0" \
	449	"prog_uboot1="CONFIG_PROG_UBOOT1"\0" \
	450	"prog_uboot2="CONFIG_PROG_UBOOT2"\0" \
	451	"prog_os1="CONFIG_PROG_OS1"\0" \
	452	"prog_os2="CONFIG_PROG_OS2"\0" \
	453	"prog_fdt1="CONFIG_PROG_FDT1"\0" \
	454	"prog_fdt2="CONFIG_PROG_FDT2"\0" \
	455	"bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \
	456	"bootcmd_flash1=run set_bootargs; " \
	457	"bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
	458	"bootcmd_flash2=run set_bootargs; " \
	459	"bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
	460	"bootcmd=run bootcmd_flash1\0"
	461	#endif /* __CONFIG_H */