[people/ms/u-boot.git] / include / configs / xpedite537x.h

/*
 * Copyright 2008 Extreme Engineering Solutions, Inc.
 * Copyright 2007-2008 Freescale Semiconductor, Inc.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*
 * xpedite537x board configuration file
 */
#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 */
#define CONFIG_SYS_BOARD_NAME	"XPedite5370"
#define CONFIG_SYS_FORM_3U_VPX	1
#define CONFIG_BOARD_EARLY_INIT_R	/* Call board_pre_init */

#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE	0xfff80000
#endif

#define CONFIG_PCI_SCAN_SHOW	1	/* show pci devices on startup */
#define CONFIG_PCIE1		1	/* PCIE controller 1 */
#define CONFIG_PCIE2		1	/* PCIE controller 2 */
#define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
#define CONFIG_PCI_INDIRECT_BRIDGE 1	/* indirect PCI bridge support */
#define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
#define CONFIG_FSL_PCIE_RESET	1	/* need PCIe reset errata */

/*
 * Multicore config
 */
#define CONFIG_MP
#define CONFIG_BPTR_VIRT_ADDR	0xee000000	/* virt boot page address */
#define CONFIG_MPC8xxx_DISABLE_BPTR		/* Don't leave BPTR enabled */

/*
 * DDR config
 */
#undef CONFIG_FSL_DDR_INTERACTIVE
#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
#define CONFIG_DDR_SPD
#define CONFIG_MEM_INIT_VALUE		0xdeadbeef
#define SPD_EEPROM_ADDRESS1		0x54	/* Both channels use the */
#define SPD_EEPROM_ADDRESS2		0x54	/* same SPD data         */
#define SPD_EEPROM_OFFSET		0x200	/* OFFSET of SPD in EEPROM */
#define CONFIG_DIMM_SLOTS_PER_CTLR	1
#define CONFIG_CHIP_SELECTS_PER_CTRL	1
#define CONFIG_DDR_ECC
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000 /* DDR is system memory*/
#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_VERY_BIG_RAM

#ifndef __ASSEMBLY__
extern unsigned long get_board_sys_clk(unsigned long dummy);
extern unsigned long get_board_ddr_clk(unsigned long dummy);
#endif

#define CONFIG_SYS_CLK_FREQ	get_board_sys_clk(0) /* sysclk for MPC85xx */
#define CONFIG_DDR_CLK_FREQ	get_board_ddr_clk(0) /* ddrclk for MPC85xx */

/*
 * These can be toggled for performance analysis, otherwise use default.
 */
#define CONFIG_L2_CACHE			/* toggle L2 cache */
#define CONFIG_BTB			/* toggle branch predition */
#define CONFIG_ENABLE_36BIT_PHYS	1

#define CONFIG_SYS_CCSRBAR		0xef000000
#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR

/*
 * Diagnostics
 */
#define CONFIG_SYS_ALT_MEMTEST
#define CONFIG_SYS_MEMTEST_START	0x10000000
#define CONFIG_SYS_MEMTEST_END		0x20000000
#define CONFIG_POST			(CONFIG_SYS_POST_MEMORY | \
					 CONFIG_SYS_POST_I2C)
/* The XPedite5370 can host an XMC which has an EEPROM at address 0x50 */
#define I2C_ADDR_IGNORE_LIST		{0x50}

/*
 * Memory map
 * 0x0000_0000	0x7fff_ffff	DDR			2G Cacheable
 * 0x8000_0000	0xbfff_ffff	PCIe1 Mem		1G non-cacheable
 * 0xc000_0000	0xcfff_ffff	PCIe2 Mem		256M non-cacheable
 * 0xe000_0000	0xe7ff_ffff	SRAM/SSRAM/L1 Cache	128M non-cacheable
 * 0xe800_0000	0xe87f_ffff	PCIe1 IO		8M non-cacheable
 * 0xe880_0000	0xe8ff_ffff	PCIe2 IO		8M non-cacheable
 * 0xee00_0000	0xee00_ffff	Boot page translation	4K non-cacheable
 * 0xef00_0000	0xef0f_ffff	CCSR/IMMR		1M non-cacheable
 * 0xef80_0000	0xef8f_ffff	NAND Flash		1M non-cacheable
 * 0xf000_0000	0xf7ff_ffff	NOR Flash 2		128M non-cacheable
 * 0xf800_0000	0xffff_ffff	NOR Flash 1		128M non-cacheable
 */

#define CONFIG_SYS_LBC_LCRR	(LCRR_CLKDIV_8 | LCRR_EADC_3)

/*
 * NAND flash configuration
 */
#define CONFIG_SYS_NAND_BASE		0xef800000
#define CONFIG_SYS_NAND_BASE2		0xef840000 /* Unused at this time */
#define CONFIG_SYS_NAND_BASE_LIST	{CONFIG_SYS_NAND_BASE, \
					 CONFIG_SYS_NAND_BASE2}
#define CONFIG_SYS_MAX_NAND_DEVICE	2
#define CONFIG_NAND_FSL_ELBC

/*
 * NOR flash configuration
 */
#define CONFIG_SYS_FLASH_BASE		0xf8000000
#define CONFIG_SYS_FLASH_BASE2		0xf0000000
#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
#define CONFIG_SYS_MAX_FLASH_BANKS	2		/* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT	1024		/* sectors per device */
#define CONFIG_SYS_FLASH_ERASE_TOUT	60000		/* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500		/* Flash Write Timeout (ms) */
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
#define CONFIG_SYS_FLASH_AUTOPROTECT_LIST	{ {0xfff40000, 0xc0000}, \
						  {0xf7f40000, 0xc0000} }
#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */

/*
 * Chip select configuration
 */
/* NOR Flash 0 on CS0 */
#define CONFIG_SYS_BR0_PRELIM	(CONFIG_SYS_FLASH_BASE	| \
				 BR_PS_16		| \
				 BR_V)
#define CONFIG_SYS_OR0_PRELIM	(OR_AM_128MB		| \
				 OR_GPCM_CSNT		| \
				 OR_GPCM_XACS		| \
				 OR_GPCM_ACS_DIV2	| \
				 OR_GPCM_SCY_8		| \
				 OR_GPCM_TRLX		| \
				 OR_GPCM_EHTR		| \
				 OR_GPCM_EAD)

/* NOR Flash 1 on CS1 */
#define CONFIG_SYS_BR1_PRELIM	(CONFIG_SYS_FLASH_BASE2	| \
				 BR_PS_16		| \
				 BR_V)
#define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_OR0_PRELIM

/* NAND flash on CS2 */
#define CONFIG_SYS_BR2_PRELIM	(CONFIG_SYS_NAND_BASE	| \
				 (2<<BR_DECC_SHIFT)	| \
				 BR_PS_8		| \
				 BR_MS_FCM		| \
				 BR_V)

/* NAND flash on CS2 */
#define CONFIG_SYS_OR2_PRELIM	(OR_AM_256KB	| \
				 OR_FCM_PGS	| \
				 OR_FCM_CSCT	| \
				 OR_FCM_CST	| \
				 OR_FCM_CHT	| \
				 OR_FCM_SCY_1	| \
				 OR_FCM_TRLX	| \
				 OR_FCM_EHTR)

/* NAND flash on CS3 */
#define CONFIG_SYS_BR3_PRELIM	(CONFIG_SYS_NAND_BASE2	| \
				 (2<<BR_DECC_SHIFT)	| \
				 BR_PS_8		| \
				 BR_MS_FCM		| \
				 BR_V)
#define CONFIG_SYS_OR3_PRELIM	CONFIG_SYS_OR2_PRELIM

/*
 * Use L1 as initial stack
 */
#define CONFIG_SYS_INIT_RAM_LOCK	1
#define CONFIG_SYS_INIT_RAM_ADDR	0xe0000000
#define CONFIG_SYS_INIT_RAM_SIZE		0x00004000

#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)	/* Reserve 512 KB for Mon */
#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)	/* Reserved for malloc */

/*
 * Serial Port
 */
#define CONFIG_CONS_INDEX		1
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
#define CONFIG_SYS_BAUDRATE_TABLE	\
	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
#define CONFIG_LOADS_ECHO		1	/* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */

/*
 * I2C
 */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED	400000
#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
#define CONFIG_SYS_FSL_I2C2_SPEED	400000
#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x69} }

/* PEX8518 slave I2C interface */
#define CONFIG_SYS_I2C_PEX8518_ADDR	0x70

/* I2C DS1631 temperature sensor */
#define CONFIG_SYS_I2C_LM90_ADDR	0x4c

/* I2C EEPROM - AT24C128B */
#define CONFIG_SYS_I2C_EEPROM_ADDR		0x54
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	6	/* 64 byte pages */
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* take up to 10 msec */

/* I2C RTC */
#define CONFIG_RTC_M41T11		1
#define CONFIG_SYS_I2C_RTC_ADDR		0x68
#define CONFIG_SYS_M41T11_BASE_YEAR	2000

/* GPIO */
#define CONFIG_PCA953X
#define CONFIG_SYS_I2C_PCA953X_ADDR0	0x18
#define CONFIG_SYS_I2C_PCA953X_ADDR1	0x1c
#define CONFIG_SYS_I2C_PCA953X_ADDR2	0x1e
#define CONFIG_SYS_I2C_PCA953X_ADDR3	0x1f
#define CONFIG_SYS_I2C_PCA953X_ADDR	CONFIG_SYS_I2C_PCA953X_ADDR0

/*
 * PU = pulled high, PD = pulled low
 * I = input, O = output, IO = input/output
 */
/* PCA9557 @ 0x18*/
#define CONFIG_SYS_PCA953X_C0_SER0_EN		0x01 /* PU; UART0 enable (1: enabled) */
#define CONFIG_SYS_PCA953X_C0_SER0_MODE		0x02 /* PU; UART0 serial mode select */
#define CONFIG_SYS_PCA953X_C0_SER1_EN		0x04 /* PU; UART1 enable (1: enabled) */
#define CONFIG_SYS_PCA953X_C0_SER1_MODE		0x08 /* PU; UART1 serial mode select */
#define CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS	0x10 /* PU; Boot flash CS select */
#define CONFIG_SYS_PCA953X_NVM_WP		0x20 /* PU; Set to 0 to enable NVM writing */
#define CONFIG_SYS_PCA953X_C0_VCORE_VID2	0x40 /* VID2 of ISL6262 */
#define CONFIG_SYS_PCA953X_C0_VCORE_VID3	0x80 /* VID3 of ISL6262 */

/* PCA9557 @ 0x1c*/
#define CONFIG_SYS_PCA953X_XMC0_ROOT0		0x01 /* PU; Low if XMC is RC */
#define CONFIG_SYS_PCA953X_XMC0_MVMR0		0x02 /* XMC EEPROM write protect */
#define CONFIG_SYS_PCA953X_XMC0_WAKE		0x04 /* PU; XMC wake */
#define CONFIG_SYS_PCA953X_XMC0_BIST		0x08 /* PU; XMC built in self test */
#define CONFIG_SYS_PCA953X_XMC_PRESENT		0x10 /* PU; Low if XMC module installed */
#define CONFIG_SYS_PCA953X_PMC_PRESENT		0x20 /* PU; Low if PMC module installed */
#define CONFIG_SYS_PCA953X_PMC0_MONARCH		0x40 /* PMC monarch mode enable */
#define CONFIG_SYS_PCA953X_PMC0_EREADY		0x80 /* PU; PMC PCI eready */

/* PCA9557 @ 0x1e*/
#define CONFIG_SYS_PCA953X_P0_GA0		0x01 /* PU; VPX Geographical address */
#define CONFIG_SYS_PCA953X_P0_GA1		0x02 /* PU; VPX Geographical address */
#define CONFIG_SYS_PCA953X_P0_GA2		0x04 /* PU; VPX Geographical address */
#define CONFIG_SYS_PCA953X_P0_GA3		0x08 /* PU; VPX Geographical address */
#define CONFIG_SYS_PCA953X_P0_GA4		0x10 /* PU; VPX Geographical address */
#define CONFIG_SYS_PCA953X_P0_GAP		0x20 /* PU; tied to VPX P0.GAP */
#define CONFIG_SYS_PCA953X_P1_SYSEN		0x80 /* PU; Pulled high; tied to VPX P1.SYSCON */

/* PCA9557 @ 0x1f */
#define CONFIG_SYS_PCA953X_GPIO_VPX0		0x01 /* PU */
#define CONFIG_SYS_PCA953X_GPIO_VPX1		0x02 /* PU */
#define CONFIG_SYS_PCA953X_GPIO_VPX2		0x04 /* PU */
#define CONFIG_SYS_PCA953X_GPIO_VPX3		0x08 /* PU */
#define CONFIG_SYS_PCA953X_VPX_FRU_WRCTL	0x10 /* PD; I2C master source for FRU SEEPROM */

/*
 * General PCI
 * Memory space is mapped 1-1, but I/O space must start from 0.
 */
/* PCIE1 - VPX P1 */
#define CONFIG_SYS_PCIE1_MEM_BUS	0x80000000
#define CONFIG_SYS_PCIE1_MEM_PHYS	CONFIG_SYS_PCIE1_MEM_BUS
#define CONFIG_SYS_PCIE1_MEM_SIZE	0x40000000	/* 1G */
#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
#define CONFIG_SYS_PCIE1_IO_PHYS	0xe8000000
#define CONFIG_SYS_PCIE1_IO_SIZE	0x00800000	/* 8M */

/* PCIE2 - PEX8518 */
#define CONFIG_SYS_PCIE2_MEM_BUS	0xc0000000
#define CONFIG_SYS_PCIE2_MEM_PHYS	CONFIG_SYS_PCIE2_MEM_BUS
#define CONFIG_SYS_PCIE2_MEM_SIZE	0x10000000	/* 256M */
#define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
#define CONFIG_SYS_PCIE2_IO_PHYS	0xe8800000
#define CONFIG_SYS_PCIE2_IO_SIZE	0x00800000	/* 8M */

/*
 * Networking options
 */
#define CONFIG_TSEC_ENET		/* tsec ethernet support */
#define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
#define CONFIG_TSEC_TBI
#define CONFIG_MII		1	/* MII PHY management */
#define CONFIG_MII_DEFAULT_TSEC	1	/* Allow unregistered phys */
#define CONFIG_ETHPRIME		"eTSEC2"

/*
 * In-band SGMII auto-negotiation between TBI and BCM5482S PHY fails, force
 * 1000mbps SGMII link
 */
#define CONFIG_TSEC_TBICR_SETTINGS ( \
		TBICR_PHY_RESET \
		| TBICR_FULL_DUPLEX \
		| TBICR_SPEED1_SET \
		)

#define CONFIG_TSEC1		1
#define CONFIG_TSEC1_NAME	"eTSEC1"
#define TSEC1_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
#define TSEC1_PHY_ADDR		1
#define TSEC1_PHYIDX		0
#define CONFIG_HAS_ETH0

#define CONFIG_TSEC2		1
#define CONFIG_TSEC2_NAME	"eTSEC2"
#define TSEC2_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
#define TSEC2_PHY_ADDR		2
#define TSEC2_PHYIDX		0
#define CONFIG_HAS_ETH1

/*
 * Command configuration.
 */
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_NAND
#define CONFIG_CMD_PCA953X
#define CONFIG_CMD_PCA953X_INFO
#define CONFIG_CMD_PCI
#define CONFIG_CMD_PCI_ENUM
#define CONFIG_CMD_REGINFO

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
#define CONFIG_CMDLINE_EDITING	1		/* add command line history	*/
#define CONFIG_AUTO_COMPLETE	1		/* add autocompletion support */
#define CONFIG_LOADADDR		0x1000000	/* default location for tftp and bootm */
#define CONFIG_PANIC_HANG			/* do not reset board on panic */
#define CONFIG_PREBOOT				/* enable preboot variable */
#define CONFIG_INTEGRITY			/* support booting INTEGRITY OS */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 16 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ	(16 << 20)	/* Initial Memory map for Linux*/
#define CONFIG_SYS_BOOTM_LEN	(16 << 20)	/* Increase max gunzip size */

/*
 * Environment Configuration
 */
#define CONFIG_ENV_IS_IN_FLASH	1
#define CONFIG_ENV_SECT_SIZE	0x20000		/* 128k (one sector) for env */
#define CONFIG_ENV_SIZE		0x8000
#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - (256 * 1024))

/*
 * Flash memory map:
 * fff80000 - ffffffff     Pri U-Boot (512 KB)
 * fff40000 - fff7ffff     Pri U-Boot Environment (256 KB)
 * fff00000 - fff3ffff     Pri FDT (256KB)
 * fef00000 - ffefffff     Pri OS image (16MB)
 * f8000000 - feefffff     Pri OS Use/Filesystem (111MB)
 *
 * f7f80000 - f7ffffff     Sec U-Boot (512 KB)
 * f7f40000 - f7f7ffff     Sec U-Boot Environment (256 KB)
 * f7f00000 - f7f3ffff     Sec FDT (256KB)
 * f6f00000 - f7efffff     Sec OS image (16MB)
 * f0000000 - f6efffff     Sec OS Use/Filesystem (111MB)
 */
#define CONFIG_UBOOT1_ENV_ADDR	__stringify(0xfff80000)
#define CONFIG_UBOOT2_ENV_ADDR	__stringify(0xf7f80000)
#define CONFIG_FDT1_ENV_ADDR	__stringify(0xfff00000)
#define CONFIG_FDT2_ENV_ADDR	__stringify(0xf7f00000)
#define CONFIG_OS1_ENV_ADDR	__stringify(0xfef00000)
#define CONFIG_OS2_ENV_ADDR	__stringify(0xf6f00000)

#define CONFIG_PROG_UBOOT1						\
	"$download_cmd $loadaddr $ubootfile; "				\
	"if test $? -eq 0; then "					\
		"protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; "		\
		"erase "CONFIG_UBOOT1_ENV_ADDR" +80000; "		\
		"cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; "	\
		"protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; "		\
		"cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; "	\
		"if test $? -ne 0; then "				\
			"echo PROGRAM FAILED; "				\
		"else; "						\
			"echo PROGRAM SUCCEEDED; "			\
		"fi; "							\
	"else; "							\
		"echo DOWNLOAD FAILED; "				\
	"fi;"

#define CONFIG_PROG_UBOOT2						\
	"$download_cmd $loadaddr $ubootfile; "				\
	"if test $? -eq 0; then "					\
		"protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; "		\
		"erase "CONFIG_UBOOT2_ENV_ADDR" +80000; "		\
		"cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; "	\
		"protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; "		\
		"cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; "	\
		"if test $? -ne 0; then "				\
			"echo PROGRAM FAILED; "				\
		"else; "						\
			"echo PROGRAM SUCCEEDED; "			\
		"fi; "							\
	"else; "							\
		"echo DOWNLOAD FAILED; "				\
	"fi;"

#define CONFIG_BOOT_OS_NET						\
	"$download_cmd $osaddr $osfile; "				\
	"if test $? -eq 0; then "					\
		"if test -n $fdtaddr; then "				\
			"$download_cmd $fdtaddr $fdtfile; "		\
			"if test $? -eq 0; then "			\
				"bootm $osaddr - $fdtaddr; "		\
			"else; "					\
				"echo FDT DOWNLOAD FAILED; "		\
			"fi; "						\
		"else; "						\
			"bootm $osaddr; "				\
		"fi; "							\
	"else; "							\
		"echo OS DOWNLOAD FAILED; "				\
	"fi;"

#define CONFIG_PROG_OS1							\
	"$download_cmd $osaddr $osfile; "				\
	"if test $? -eq 0; then "					\
		"erase "CONFIG_OS1_ENV_ADDR" +$filesize; "		\
		"cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; "	\
		"cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; "	\
		"if test $? -ne 0; then "				\
			"echo OS PROGRAM FAILED; "			\
		"else; "						\
			"echo OS PROGRAM SUCCEEDED; "			\
		"fi; "							\
	"else; "							\
		"echo OS DOWNLOAD FAILED; "				\
	"fi;"

#define CONFIG_PROG_OS2							\
	"$download_cmd $osaddr $osfile; "				\
	"if test $? -eq 0; then "					\
		"erase "CONFIG_OS2_ENV_ADDR" +$filesize; "		\
		"cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; "	\
		"cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; "	\
		"if test $? -ne 0; then "				\
			"echo OS PROGRAM FAILED; "			\
		"else; "						\
			"echo OS PROGRAM SUCCEEDED; "			\
		"fi; "							\
	"else; "							\
		"echo OS DOWNLOAD FAILED; "				\
	"fi;"

#define CONFIG_PROG_FDT1						\
	"$download_cmd $fdtaddr $fdtfile; "				\
	"if test $? -eq 0; then "					\
		"erase "CONFIG_FDT1_ENV_ADDR" +$filesize;"		\
		"cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; "	\
		"cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; "	\
		"if test $? -ne 0; then "				\
			"echo FDT PROGRAM FAILED; "			\
		"else; "						\
			"echo FDT PROGRAM SUCCEEDED; "			\
		"fi; "							\
	"else; "							\
		"echo FDT DOWNLOAD FAILED; "				\
	"fi;"

#define CONFIG_PROG_FDT2						\
	"$download_cmd $fdtaddr $fdtfile; "				\
	"if test $? -eq 0; then "					\
		"erase "CONFIG_FDT2_ENV_ADDR" +$filesize;"		\
		"cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; "	\
		"cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; "	\
		"if test $? -ne 0; then "				\
			"echo FDT PROGRAM FAILED; "			\
		"else; "						\
			"echo FDT PROGRAM SUCCEEDED; "			\
		"fi; "							\
	"else; "							\
		"echo FDT DOWNLOAD FAILED; "				\
	"fi;"

#define	CONFIG_EXTRA_ENV_SETTINGS					\
	"autoload=yes\0"						\
	"download_cmd=tftp\0"						\
	"console_args=console=ttyS0,115200\0"				\
	"root_args=root=/dev/nfs rw\0"					\
	"misc_args=ip=on\0"						\
	"set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
	"bootfile=/home/user/file\0"					\
	"osfile=/home/user/board.uImage\0"				\
	"fdtfile=/home/user/board.dtb\0"				\
	"ubootfile=/home/user/u-boot.bin\0"				\
	"fdtaddr=0x1e00000\0"						\
	"osaddr=0x1000000\0"						\
	"loadaddr=0x1000000\0"						\
	"prog_uboot1="CONFIG_PROG_UBOOT1"\0"				\
	"prog_uboot2="CONFIG_PROG_UBOOT2"\0"				\
	"prog_os1="CONFIG_PROG_OS1"\0"					\
	"prog_os2="CONFIG_PROG_OS2"\0"					\
	"prog_fdt1="CONFIG_PROG_FDT1"\0"				\
	"prog_fdt2="CONFIG_PROG_FDT2"\0"				\
	"bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0"		\
	"bootcmd_flash1=run set_bootargs; "				\
		"bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
	"bootcmd_flash2=run set_bootargs; "				\
		"bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
	"bootcmd=run bootcmd_flash1\0"
#endif	/* __CONFIG_H */
Commit	Line	Data
ccf0fdd0 PT	1	/*
	2	* Copyright 2008 Extreme Engineering Solutions, Inc.
	3	* Copyright 2007-2008 Freescale Semiconductor, Inc.
	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
ccf0fdd0 PT	6	*/
	7
	8	/*
c00ac259	9	* xpedite537x board configuration file
ccf0fdd0 PT	10	*/
	11	#ifndef __CONFIG_H
	12	#define __CONFIG_H
	13
	14	/*
	15	* High Level Configuration Options
	16	*/
ccf0fdd0	17	#define CONFIG_SYS_BOARD_NAME "XPedite5370"
92af6549	18	#define CONFIG_SYS_FORM_3U_VPX 1
ccf0fdd0	19	#define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */
ccf0fdd0	20
2ae18241 WD	21	#ifndef CONFIG_SYS_TEXT_BASE
	22	#define CONFIG_SYS_TEXT_BASE 0xfff80000
	23	#endif
	24
ccf0fdd0	25	#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
b38eaec5 RD	26	#define CONFIG_PCIE1 1 /* PCIE controller 1 */
b38eaec5 RD	27	#define CONFIG_PCIE2 1 /* PCIE controller 2 */
ccf0fdd0	28	#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
842033e6	29	#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
ccf0fdd0 PT	30	#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
ccf0fdd0 PT	31	#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
ccf0fdd0	32
48618126 PT	33	/*
	34	* Multicore config
	35	*/
	36	#define CONFIG_MP
	37	#define CONFIG_BPTR_VIRT_ADDR 0xee000000 /* virt boot page address */
	38	#define CONFIG_MPC8xxx_DISABLE_BPTR /* Don't leave BPTR enabled */
	39
ccf0fdd0 PT	40	/*
	41	* DDR config
	42	*/
ccf0fdd0 PT	43	#undef CONFIG_FSL_DDR_INTERACTIVE
	44	#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
	45	#define CONFIG_DDR_SPD
	46	#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
	47	#define SPD_EEPROM_ADDRESS1 0x54 /* Both channels use the */
	48	#define SPD_EEPROM_ADDRESS2 0x54 /* same SPD data */
	49	#define SPD_EEPROM_OFFSET 0x200 /* OFFSET of SPD in EEPROM */
ccf0fdd0 PT	50	#define CONFIG_DIMM_SLOTS_PER_CTLR 1
	51	#define CONFIG_CHIP_SELECTS_PER_CTRL 1
	52	#define CONFIG_DDR_ECC
	53	#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
	54	#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
	55	#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
	56	#define CONFIG_VERY_BIG_RAM
	57
	58	#ifndef __ASSEMBLY__
	59	extern unsigned long get_board_sys_clk(unsigned long dummy);
	60	extern unsigned long get_board_ddr_clk(unsigned long dummy);
	61	#endif
	62
	63	#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */
	64	#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0) /* ddrclk for MPC85xx */
	65
	66	/*
	67	* These can be toggled for performance analysis, otherwise use default.
	68	*/
	69	#define CONFIG_L2_CACHE /* toggle L2 cache */
	70	#define CONFIG_BTB /* toggle branch predition */
	71	#define CONFIG_ENABLE_36BIT_PHYS 1
	72
e46fedfe TT	73	#define CONFIG_SYS_CCSRBAR 0xef000000
e46fedfe TT	74	#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
ccf0fdd0 PT	75
	76	/*
	77	* Diagnostics
	78	*/
	79	#define CONFIG_SYS_ALT_MEMTEST
	80	#define CONFIG_SYS_MEMTEST_START 0x10000000
	81	#define CONFIG_SYS_MEMTEST_END 0x20000000
66a8b440 PT	82	#define CONFIG_POST (CONFIG_SYS_POST_MEMORY \| \
66a8b440 PT	83	CONFIG_SYS_POST_I2C)
66a8b440 PT	84	/* The XPedite5370 can host an XMC which has an EEPROM at address 0x50 */
66a8b440 PT	85	#define I2C_ADDR_IGNORE_LIST {0x50}
ccf0fdd0 PT	86
	87	/*
	88	* Memory map
	89	* 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
	90	* 0x8000_0000 0xbfff_ffff PCIe1 Mem 1G non-cacheable
	91	* 0xc000_0000 0xcfff_ffff PCIe2 Mem 256M non-cacheable
	92	* 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable
	93	* 0xe800_0000 0xe87f_ffff PCIe1 IO 8M non-cacheable
	94	* 0xe880_0000 0xe8ff_ffff PCIe2 IO 8M non-cacheable
48618126	95	* 0xee00_0000 0xee00_ffff Boot page translation 4K non-cacheable
ccf0fdd0 PT	96	* 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable
	97	* 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable
	98	* 0xf000_0000 0xf7ff_ffff NOR Flash 2 128M non-cacheable
	99	* 0xf800_0000 0xffff_ffff NOR Flash 1 128M non-cacheable
	100	*/
	101
202d9487	102	#define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_8 \| LCRR_EADC_3)
ccf0fdd0 PT	103
	104	/*
	105	* NAND flash configuration
	106	*/
	107	#define CONFIG_SYS_NAND_BASE 0xef800000
	108	#define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */
0a6d0c63 PT	109	#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE, \
	110	CONFIG_SYS_NAND_BASE2}
	111	#define CONFIG_SYS_MAX_NAND_DEVICE 2
0a6d0c63	112	#define CONFIG_NAND_FSL_ELBC
ccf0fdd0 PT	113
	114	/*
	115	* NOR flash configuration
	116	*/
	117	#define CONFIG_SYS_FLASH_BASE 0xf8000000
	118	#define CONFIG_SYS_FLASH_BASE2 0xf0000000
	119	#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
	120	#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
	121	#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
	122	#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
	123	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
	124	#define CONFIG_FLASH_CFI_DRIVER
	125	#define CONFIG_SYS_FLASH_CFI
5ff82100	126	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
ccf0fdd0 PT	127	#define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff40000, 0xc0000}, \
ccf0fdd0 PT	128	{0xf7f40000, 0xc0000} }
14d0a02a	129	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
ccf0fdd0 PT	130
	131	/*
	132	* Chip select configuration
	133	*/
	134	/* NOR Flash 0 on CS0 */
	135	#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \| \
	136	BR_PS_16 \| \
	137	BR_V)
	138	#define CONFIG_SYS_OR0_PRELIM (OR_AM_128MB \| \
	139	OR_GPCM_CSNT \| \
	140	OR_GPCM_XACS \| \
	141	OR_GPCM_ACS_DIV2 \| \
	142	OR_GPCM_SCY_8 \| \
	143	OR_GPCM_TRLX \| \
	144	OR_GPCM_EHTR \| \
	145	OR_GPCM_EAD)
	146
	147	/* NOR Flash 1 on CS1 */
	148	#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 \| \
	149	BR_PS_16 \| \
	150	BR_V)
	151	#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
	152
	153	/* NAND flash on CS2 */
	154	#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE \| \
	155	(2<<BR_DECC_SHIFT) \| \
	156	BR_PS_8 \| \
	157	BR_MS_FCM \| \
	158	BR_V)
	159
	160	/* NAND flash on CS2 */
	161	#define CONFIG_SYS_OR2_PRELIM (OR_AM_256KB \| \
	162	OR_FCM_PGS \| \
	163	OR_FCM_CSCT \| \
	164	OR_FCM_CST \| \
	165	OR_FCM_CHT \| \
	166	OR_FCM_SCY_1 \| \
	167	OR_FCM_TRLX \| \
	168	OR_FCM_EHTR)
	169
	170	/* NAND flash on CS3 */
	171	#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE2 \| \
	172	(2<<BR_DECC_SHIFT) \| \
	173	BR_PS_8 \| \
	174	BR_MS_FCM \| \
	175	BR_V)
	176	#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
	177
	178	/*
	179	* Use L1 as initial stack
	180	*/
	181	#define CONFIG_SYS_INIT_RAM_LOCK 1
	182	#define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000
553f0982	183	#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
ccf0fdd0	184
25ddd1fb	185	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
ccf0fdd0 PT	186	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
	187
	188	#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */
	189	#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
	190
	191	/*
	192	* Serial Port
	193	*/
	194	#define CONFIG_CONS_INDEX 1
ccf0fdd0 PT	195	#define CONFIG_SYS_NS16550_SERIAL
	196	#define CONFIG_SYS_NS16550_REG_SIZE 1
	197	#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
	198	#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
	199	#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
	200	#define CONFIG_SYS_BAUDRATE_TABLE \
	201	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
ccf0fdd0 PT	202	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
	203	#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
	204
ccf0fdd0 PT	205	/*
	206	* I2C
	207	*/
00f792e0 HS	208	#define CONFIG_SYS_I2C
	209	#define CONFIG_SYS_I2C_FSL
	210	#define CONFIG_SYS_FSL_I2C_SPEED 400000
	211	#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
	212	#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
	213	#define CONFIG_SYS_FSL_I2C2_SPEED 400000
	214	#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
	215	#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
	216	#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
ccf0fdd0 PT	217
	218	/* PEX8518 slave I2C interface */
	219	#define CONFIG_SYS_I2C_PEX8518_ADDR 0x70
	220
	221	/* I2C DS1631 temperature sensor */
66a8b440	222	#define CONFIG_SYS_I2C_LM90_ADDR 0x4c
ccf0fdd0 PT	223
	224	/* I2C EEPROM - AT24C128B */
	225	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
	226	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
	227	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */
	228	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */
	229
	230	/* I2C RTC */
	231	#define CONFIG_RTC_M41T11 1
	232	#define CONFIG_SYS_I2C_RTC_ADDR 0x68
	233	#define CONFIG_SYS_M41T11_BASE_YEAR 2000
	234
ccf0fdd0 PT	235	/* GPIO */
	236	#define CONFIG_PCA953X
	237	#define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18
	238	#define CONFIG_SYS_I2C_PCA953X_ADDR1 0x1c
	239	#define CONFIG_SYS_I2C_PCA953X_ADDR2 0x1e
	240	#define CONFIG_SYS_I2C_PCA953X_ADDR3 0x1f
	241	#define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0
	242
	243	/*
	244	* PU = pulled high, PD = pulled low
	245	* I = input, O = output, IO = input/output
	246	*/
	247	/* PCA9557 @ 0x18*/
	248	#define CONFIG_SYS_PCA953X_C0_SER0_EN 0x01 /* PU; UART0 enable (1: enabled) */
	249	#define CONFIG_SYS_PCA953X_C0_SER0_MODE 0x02 /* PU; UART0 serial mode select */
	250	#define CONFIG_SYS_PCA953X_C0_SER1_EN 0x04 /* PU; UART1 enable (1: enabled) */
	251	#define CONFIG_SYS_PCA953X_C0_SER1_MODE 0x08 /* PU; UART1 serial mode select */
	252	#define CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS 0x10 /* PU; Boot flash CS select */
	253	#define CONFIG_SYS_PCA953X_NVM_WP 0x20 /* PU; Set to 0 to enable NVM writing */
	254	#define CONFIG_SYS_PCA953X_C0_VCORE_VID2 0x40 /* VID2 of ISL6262 */
	255	#define CONFIG_SYS_PCA953X_C0_VCORE_VID3 0x80 /* VID3 of ISL6262 */
	256
	257	/* PCA9557 @ 0x1c*/
	258	#define CONFIG_SYS_PCA953X_XMC0_ROOT0 0x01 /* PU; Low if XMC is RC */
	259	#define CONFIG_SYS_PCA953X_XMC0_MVMR0 0x02 /* XMC EEPROM write protect */
	260	#define CONFIG_SYS_PCA953X_XMC0_WAKE 0x04 /* PU; XMC wake */
	261	#define CONFIG_SYS_PCA953X_XMC0_BIST 0x08 /* PU; XMC built in self test */
	262	#define CONFIG_SYS_PCA953X_XMC_PRESENT 0x10 /* PU; Low if XMC module installed */
	263	#define CONFIG_SYS_PCA953X_PMC_PRESENT 0x20 /* PU; Low if PMC module installed */
	264	#define CONFIG_SYS_PCA953X_PMC0_MONARCH 0x40 /* PMC monarch mode enable */
	265	#define CONFIG_SYS_PCA953X_PMC0_EREADY 0x80 /* PU; PMC PCI eready */
	266
	267	/* PCA9557 @ 0x1e*/
	268	#define CONFIG_SYS_PCA953X_P0_GA0 0x01 /* PU; VPX Geographical address */
	269	#define CONFIG_SYS_PCA953X_P0_GA1 0x02 /* PU; VPX Geographical address */
	270	#define CONFIG_SYS_PCA953X_P0_GA2 0x04 /* PU; VPX Geographical address */
	271	#define CONFIG_SYS_PCA953X_P0_GA3 0x08 /* PU; VPX Geographical address */
	272	#define CONFIG_SYS_PCA953X_P0_GA4 0x10 /* PU; VPX Geographical address */
	273	#define CONFIG_SYS_PCA953X_P0_GAP 0x20 /* PU; tied to VPX P0.GAP */
	274	#define CONFIG_SYS_PCA953X_P1_SYSEN 0x80 /* PU; Pulled high; tied to VPX P1.SYSCON */
	275
	276	/* PCA9557 @ 0x1f */
	277	#define CONFIG_SYS_PCA953X_GPIO_VPX0 0x01 /* PU */
	278	#define CONFIG_SYS_PCA953X_GPIO_VPX1 0x02 /* PU */
	279	#define CONFIG_SYS_PCA953X_GPIO_VPX2 0x04 /* PU */
	280	#define CONFIG_SYS_PCA953X_GPIO_VPX3 0x08 /* PU */
	281	#define CONFIG_SYS_PCA953X_VPX_FRU_WRCTL 0x10 /* PD; I2C master source for FRU SEEPROM */
	282
	283	/*
	284	* General PCI
	285	* Memory space is mapped 1-1, but I/O space must start from 0.
	286	*/
	287	/* PCIE1 - VPX P1 */
9660c5de PT	288	#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
9660c5de PT	289	#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS
ccf0fdd0	290	#define CONFIG_SYS_PCIE1_MEM_SIZE 0x40000000 /* 1G */
9660c5de	291	#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
ccf0fdd0 PT	292	#define CONFIG_SYS_PCIE1_IO_PHYS 0xe8000000
	293	#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */
	294
	295	/* PCIE2 - PEX8518 */
9660c5de PT	296	#define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000
9660c5de PT	297	#define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS
ccf0fdd0	298	#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
9660c5de	299	#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
ccf0fdd0 PT	300	#define CONFIG_SYS_PCIE2_IO_PHYS 0xe8800000
	301	#define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 /* 8M */
	302
	303	/*
	304	* Networking options
	305	*/
	306	#define CONFIG_TSEC_ENET /* tsec ethernet support */
	307	#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
ccf0fdd0 PT	308	#define CONFIG_TSEC_TBI
	309	#define CONFIG_MII 1 /* MII PHY management */
	310	#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
	311	#define CONFIG_ETHPRIME "eTSEC2"
	312
72c96a68 KG	313	/*
	314	* In-band SGMII auto-negotiation between TBI and BCM5482S PHY fails, force
	315	* 1000mbps SGMII link
	316	*/
	317	#define CONFIG_TSEC_TBICR_SETTINGS ( \
	318	TBICR_PHY_RESET \
	319	\| TBICR_FULL_DUPLEX \
	320	\| TBICR_SPEED1_SET \
	321	)
	322
ccf0fdd0 PT	323	#define CONFIG_TSEC1 1
	324	#define CONFIG_TSEC1_NAME "eTSEC1"
	325	#define TSEC1_FLAGS (TSEC_GIGABIT \| TSEC_REDUCED)
	326	#define TSEC1_PHY_ADDR 1
	327	#define TSEC1_PHYIDX 0
	328	#define CONFIG_HAS_ETH0
	329
	330	#define CONFIG_TSEC2 1
	331	#define CONFIG_TSEC2_NAME "eTSEC2"
	332	#define TSEC2_FLAGS (TSEC_GIGABIT \| TSEC_REDUCED)
	333	#define TSEC2_PHY_ADDR 2
	334	#define TSEC2_PHYIDX 0
	335	#define CONFIG_HAS_ETH1
	336
	337	/*
	338	* Command configuration.
	339	*/
ccf0fdd0	340	#define CONFIG_CMD_JFFS2
0a6d0c63	341	#define CONFIG_CMD_NAND
ccf0fdd0 PT	342	#define CONFIG_CMD_PCA953X
	343	#define CONFIG_CMD_PCA953X_INFO
	344	#define CONFIG_CMD_PCI
96d61603	345	#define CONFIG_CMD_PCI_ENUM
199e262e	346	#define CONFIG_CMD_REGINFO
ccf0fdd0 PT	347
	348	/*
	349	* Miscellaneous configurable options
	350	*/
	351	#define CONFIG_SYS_LONGHELP /* undef to save memory */
	352	#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
ccf0fdd0 PT	353	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
	354	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	355	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	356	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
ccf0fdd0	357	#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
5be58f5f	358	#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
ccf0fdd0	359	#define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */
ccf0fdd0 PT	360	#define CONFIG_PANIC_HANG /* do not reset board on panic */
ccf0fdd0 PT	361	#define CONFIG_PREBOOT /* enable preboot variable */
ccf0fdd0 PT	362	#define CONFIG_INTEGRITY /* support booting INTEGRITY OS */
	363
	364	/*
	365	* For booting Linux, the board info and command line data
	366	* have to be in the first 16 MB of memory, since this is
	367	* the maximum mapped by the Linux kernel during initialization.
	368	*/
	369	#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
39121c08	370	#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
ccf0fdd0	371
ccf0fdd0 PT	372	/*
	373	* Environment Configuration
	374	*/
	375	#define CONFIG_ENV_IS_IN_FLASH 1
	376	#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k (one sector) for env */
	377	#define CONFIG_ENV_SIZE 0x8000
	378	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - (256 * 1024))
	379
	380	/*
	381	* Flash memory map:
	382	* fff80000 - ffffffff Pri U-Boot (512 KB)
	383	* fff40000 - fff7ffff Pri U-Boot Environment (256 KB)
	384	* fff00000 - fff3ffff Pri FDT (256KB)
	385	* fef00000 - ffefffff Pri OS image (16MB)
	386	* f8000000 - feefffff Pri OS Use/Filesystem (111MB)
	387	*
	388	* f7f80000 - f7ffffff Sec U-Boot (512 KB)
	389	* f7f40000 - f7f7ffff Sec U-Boot Environment (256 KB)
	390	* f7f00000 - f7f3ffff Sec FDT (256KB)
	391	* f6f00000 - f7efffff Sec OS image (16MB)
	392	* f0000000 - f6efffff Sec OS Use/Filesystem (111MB)
	393	*/
5368c55d MV	394	#define CONFIG_UBOOT1_ENV_ADDR __stringify(0xfff80000)
	395	#define CONFIG_UBOOT2_ENV_ADDR __stringify(0xf7f80000)
	396	#define CONFIG_FDT1_ENV_ADDR __stringify(0xfff00000)
	397	#define CONFIG_FDT2_ENV_ADDR __stringify(0xf7f00000)
	398	#define CONFIG_OS1_ENV_ADDR __stringify(0xfef00000)
	399	#define CONFIG_OS2_ENV_ADDR __stringify(0xf6f00000)
ccf0fdd0 PT	400
	401	#define CONFIG_PROG_UBOOT1 \
	402	"$download_cmd $loadaddr $ubootfile; " \
	403	"if test $? -eq 0; then " \
	404	"protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
	405	"erase "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
	406	"cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; " \
	407	"protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
	408	"cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; " \
	409	"if test $? -ne 0; then " \
	410	"echo PROGRAM FAILED; " \
	411	"else; " \
	412	"echo PROGRAM SUCCEEDED; " \
	413	"fi; " \
	414	"else; " \
	415	"echo DOWNLOAD FAILED; " \
	416	"fi;"
	417
	418	#define CONFIG_PROG_UBOOT2 \
	419	"$download_cmd $loadaddr $ubootfile; " \
	420	"if test $? -eq 0; then " \
	421	"protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
	422	"erase "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
	423	"cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; " \
	424	"protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
	425	"cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; " \
	426	"if test $? -ne 0; then " \
	427	"echo PROGRAM FAILED; " \
	428	"else; " \
	429	"echo PROGRAM SUCCEEDED; " \
	430	"fi; " \
	431	"else; " \
	432	"echo DOWNLOAD FAILED; " \
	433	"fi;"
	434
	435	#define CONFIG_BOOT_OS_NET \
	436	"$download_cmd $osaddr $osfile; " \
	437	"if test $? -eq 0; then " \
	438	"if test -n $fdtaddr; then " \
	439	"$download_cmd $fdtaddr $fdtfile; " \
	440	"if test $? -eq 0; then " \
	441	"bootm $osaddr - $fdtaddr; " \
	442	"else; " \
	443	"echo FDT DOWNLOAD FAILED; " \
	444	"fi; " \
	445	"else; " \
	446	"bootm $osaddr; " \
	447	"fi; " \
	448	"else; " \
	449	"echo OS DOWNLOAD FAILED; " \
	450	"fi;"
	451
	452	#define CONFIG_PROG_OS1 \
	453	"$download_cmd $osaddr $osfile; " \
	454	"if test $? -eq 0; then " \
	455	"erase "CONFIG_OS1_ENV_ADDR" +$filesize; " \
	456	"cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
	457	"cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
	458	"if test $? -ne 0; then " \
	459	"echo OS PROGRAM FAILED; " \
	460	"else; " \
	461	"echo OS PROGRAM SUCCEEDED; " \
	462	"fi; " \
	463	"else; " \
464	"echo OS DOWNLOAD FAILED; " \
465	"fi;"
466
467	#define CONFIG_PROG_OS2 \
468	"$download_cmd $osaddr $osfile; " \
469	"if test $? -eq 0; then " \
470	"erase "CONFIG_OS2_ENV_ADDR" +$filesize; " \
471	"cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
472	"cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
473	"if test $? -ne 0; then " \
474	"echo OS PROGRAM FAILED; " \
475	"else; " \
476	"echo OS PROGRAM SUCCEEDED; " \
477	"fi; " \
478	"else; " \
479	"echo OS DOWNLOAD FAILED; " \
480	"fi;"
481
482	#define CONFIG_PROG_FDT1 \
483	"$download_cmd $fdtaddr $fdtfile; " \
484	"if test $? -eq 0; then " \
485	"erase "CONFIG_FDT1_ENV_ADDR" +$filesize;" \
486	"cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
487	"cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
488	"if test $? -ne 0; then " \
489	"echo FDT PROGRAM FAILED; " \
490	"else; " \
491	"echo FDT PROGRAM SUCCEEDED; " \
492	"fi; " \
493	"else; " \
494	"echo FDT DOWNLOAD FAILED; " \
495	"fi;"
496
497	#define CONFIG_PROG_FDT2 \
498	"$download_cmd $fdtaddr $fdtfile; " \
499	"if test $? -eq 0; then " \
500	"erase "CONFIG_FDT2_ENV_ADDR" +$filesize;" \
501	"cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
502	"cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
503	"if test $? -ne 0; then " \
504	"echo FDT PROGRAM FAILED; " \
505	"else; " \
506	"echo FDT PROGRAM SUCCEEDED; " \
507	"fi; " \
508	"else; " \
509	"echo FDT DOWNLOAD FAILED; " \
510	"fi;"
511
512	#define CONFIG_EXTRA_ENV_SETTINGS \
513	"autoload=yes\0" \
514	"download_cmd=tftp\0" \
515	"console_args=console=ttyS0,115200\0" \
516	"root_args=root=/dev/nfs rw\0" \
517	"misc_args=ip=on\0" \
518	"set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
519	"bootfile=/home/user/file\0" \
c00ac259 PT	520	"osfile=/home/user/board.uImage\0" \
c00ac259 PT	521	"fdtfile=/home/user/board.dtb\0" \
ccf0fdd0	522	"ubootfile=/home/user/u-boot.bin\0" \
b24a4f62	523	"fdtaddr=0x1e00000\0" \
ccf0fdd0 PT	524	"osaddr=0x1000000\0" \
	525	"loadaddr=0x1000000\0" \
	526	"prog_uboot1="CONFIG_PROG_UBOOT1"\0" \
	527	"prog_uboot2="CONFIG_PROG_UBOOT2"\0" \
	528	"prog_os1="CONFIG_PROG_OS1"\0" \
	529	"prog_os2="CONFIG_PROG_OS2"\0" \
	530	"prog_fdt1="CONFIG_PROG_FDT1"\0" \
	531	"prog_fdt2="CONFIG_PROG_FDT2"\0" \
	532	"bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \
	533	"bootcmd_flash1=run set_bootargs; " \
	534	"bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
	535	"bootcmd_flash2=run set_bootargs; " \
	536	"bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
	537	"bootcmd=run bootcmd_flash1\0"
	538	#endif /* __CONFIG_H */