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bfe18815 JS |
1 | /* |
2 | * Copyright 2010 Extreme Engineering Solutions, Inc. | |
3 | * Copyright 2007-2008 Freescale Semiconductor, Inc. | |
4 | * | |
1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
bfe18815 JS |
6 | */ |
7 | ||
8 | /* | |
9 | * xpedite550x board configuration file | |
10 | */ | |
11 | #ifndef __CONFIG_H | |
12 | #define __CONFIG_H | |
13 | ||
14 | /* | |
15 | * High Level Configuration Options | |
16 | */ | |
bfe18815 JS |
17 | #define CONFIG_XPEDITE550X 1 |
18 | #define CONFIG_SYS_BOARD_NAME "XPedite5500" | |
19 | #define CONFIG_SYS_FORM_PMC_XMC 1 | |
20 | #define CONFIG_PRPMC_PCI_ALIAS "pci0" /* Processor PMC interface on pci0 */ | |
21 | #define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */ | |
22 | ||
23 | #ifndef CONFIG_SYS_TEXT_BASE | |
24 | #define CONFIG_SYS_TEXT_BASE 0xfff80000 | |
25 | #endif | |
26 | ||
bfe18815 | 27 | #define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */ |
b38eaec5 | 28 | #define CONFIG_PCIE1 1 /* PCIE controller 1 (PEX8112 or XMC) */ |
bfe18815 | 29 | #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ |
842033e6 | 30 | #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ |
bfe18815 JS |
31 | #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ |
32 | #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ | |
bfe18815 JS |
33 | |
34 | /* | |
35 | * Multicore config | |
36 | */ | |
37 | #define CONFIG_MP | |
38 | #define CONFIG_BPTR_VIRT_ADDR 0xee000000 /* virt boot page address */ | |
39 | #define CONFIG_MPC8xxx_DISABLE_BPTR /* Don't leave BPTR enabled */ | |
40 | ||
41 | /* | |
42 | * DDR config | |
43 | */ | |
bfe18815 JS |
44 | #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ |
45 | #define CONFIG_DDR_SPD | |
46 | #define CONFIG_MEM_INIT_VALUE 0xdeadbeef | |
c39f44dc | 47 | #define SPD_EEPROM_ADDRESS 0x54 |
bfe18815 | 48 | #define SPD_EEPROM_OFFSET 0x200 /* OFFSET of SPD in EEPROM */ |
bfe18815 JS |
49 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 |
50 | #define CONFIG_CHIP_SELECTS_PER_CTRL 2 | |
51 | #define CONFIG_DDR_ECC | |
52 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER | |
53 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ | |
54 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
55 | #define CONFIG_VERY_BIG_RAM | |
56 | ||
57 | #ifndef __ASSEMBLY__ | |
58 | extern unsigned long get_board_sys_clk(unsigned long dummy); | |
59 | extern unsigned long get_board_ddr_clk(unsigned long dummy); | |
60 | #endif | |
61 | ||
62 | #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */ | |
63 | #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0) /* ddrclk for MPC85xx */ | |
64 | ||
65 | /* | |
66 | * These can be toggled for performance analysis, otherwise use default. | |
67 | */ | |
68 | #define CONFIG_L2_CACHE /* toggle L2 cache */ | |
69 | #define CONFIG_BTB /* toggle branch predition */ | |
70 | #define CONFIG_ENABLE_36BIT_PHYS 1 | |
71 | ||
e46fedfe TT |
72 | #define CONFIG_SYS_CCSRBAR 0xef000000 |
73 | #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR | |
bfe18815 JS |
74 | |
75 | /* | |
76 | * Diagnostics | |
77 | */ | |
78 | #define CONFIG_SYS_ALT_MEMTEST | |
79 | #define CONFIG_SYS_MEMTEST_START 0x10000000 | |
80 | #define CONFIG_SYS_MEMTEST_END 0x20000000 | |
81 | #define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \ | |
82 | CONFIG_SYS_POST_I2C) | |
83 | #define I2C_ADDR_LIST {CONFIG_SYS_I2C_EEPROM_ADDR, \ | |
84 | CONFIG_SYS_I2C_LM75_ADDR, \ | |
85 | CONFIG_SYS_I2C_LM90_ADDR, \ | |
86 | CONFIG_SYS_I2C_PCA953X_ADDR0, \ | |
87 | CONFIG_SYS_I2C_PCA953X_ADDR2, \ | |
88 | CONFIG_SYS_I2C_PCA953X_ADDR3, \ | |
89 | CONFIG_SYS_I2C_RTC_ADDR} | |
90 | ||
91 | /* | |
92 | * Memory map | |
93 | * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable | |
94 | * 0x8000_0000 0xbfff_ffff PCIe1 Mem 1G non-cacheable | |
95 | * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable | |
96 | * 0xe800_0000 0xe87f_ffff PCIe1 IO 8M non-cacheable | |
97 | * 0xee00_0000 0xee00_ffff Boot page translation 4K non-cacheable | |
98 | * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable | |
99 | * 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable | |
100 | * 0xf000_0000 0xf7ff_ffff NOR Flash 2 128M non-cacheable | |
101 | * 0xf800_0000 0xffff_ffff NOR Flash 1 128M non-cacheable | |
102 | */ | |
103 | ||
104 | #define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_8 | LCRR_EADC_3) | |
105 | ||
106 | /* | |
107 | * NAND flash configuration | |
108 | */ | |
109 | #define CONFIG_SYS_NAND_BASE 0xef800000 | |
110 | #define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */ | |
111 | #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE, \ | |
112 | CONFIG_SYS_NAND_BASE2} | |
113 | #define CONFIG_SYS_MAX_NAND_DEVICE 2 | |
bfe18815 JS |
114 | #define CONFIG_NAND_FSL_ELBC |
115 | ||
116 | /* | |
117 | * NOR flash configuration | |
118 | */ | |
119 | #define CONFIG_SYS_FLASH_BASE 0xf8000000 | |
120 | #define CONFIG_SYS_FLASH_BASE2 0xf0000000 | |
121 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2} | |
122 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ | |
123 | #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ | |
124 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
125 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
126 | #define CONFIG_FLASH_CFI_DRIVER | |
127 | #define CONFIG_SYS_FLASH_CFI | |
128 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE | |
129 | #define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff40000, 0xc0000}, \ | |
130 | {0xf7f40000, 0xc0000} } | |
131 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ | |
132 | ||
133 | /* | |
134 | * Chip select configuration | |
135 | */ | |
136 | /* NOR Flash 0 on CS0 */ | |
137 | #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ | |
138 | BR_PS_16 | \ | |
139 | BR_V) | |
140 | #define CONFIG_SYS_OR0_PRELIM (OR_AM_128MB | \ | |
141 | OR_GPCM_CSNT | \ | |
142 | OR_GPCM_XACS | \ | |
143 | OR_GPCM_ACS_DIV2 | \ | |
144 | OR_GPCM_SCY_8 | \ | |
145 | OR_GPCM_TRLX | \ | |
146 | OR_GPCM_EHTR | \ | |
147 | OR_GPCM_EAD) | |
148 | ||
149 | /* NOR Flash 1 on CS1 */ | |
150 | #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 | \ | |
151 | BR_PS_16 | \ | |
152 | BR_V) | |
153 | #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM | |
154 | ||
155 | /* NAND flash on CS2 */ | |
156 | #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE | \ | |
157 | (2<<BR_DECC_SHIFT) | \ | |
158 | BR_PS_8 | \ | |
159 | BR_MS_FCM | \ | |
160 | BR_V) | |
161 | ||
162 | /* NAND flash on CS2 */ | |
163 | #define CONFIG_SYS_OR2_PRELIM (OR_AM_256KB | \ | |
164 | OR_FCM_PGS | \ | |
165 | OR_FCM_CSCT | \ | |
166 | OR_FCM_CST | \ | |
167 | OR_FCM_CHT | \ | |
168 | OR_FCM_SCY_1 | \ | |
169 | OR_FCM_TRLX | \ | |
170 | OR_FCM_EHTR) | |
171 | ||
172 | /* NAND flash on CS3 */ | |
173 | #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE2 | \ | |
174 | (2<<BR_DECC_SHIFT) | \ | |
175 | BR_PS_8 | \ | |
176 | BR_MS_FCM | \ | |
177 | BR_V) | |
178 | #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM | |
179 | ||
180 | /* | |
181 | * Use L1 as initial stack | |
182 | */ | |
183 | #define CONFIG_SYS_INIT_RAM_LOCK 1 | |
184 | #define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000 | |
553f0982 | 185 | #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 |
bfe18815 | 186 | |
25ddd1fb | 187 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
bfe18815 JS |
188 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
189 | ||
190 | #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */ | |
191 | #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ | |
192 | ||
193 | /* | |
194 | * Serial Port | |
195 | */ | |
196 | #define CONFIG_CONS_INDEX 1 | |
bfe18815 JS |
197 | #define CONFIG_SYS_NS16550_SERIAL |
198 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
199 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
200 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) | |
201 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) | |
202 | #define CONFIG_SYS_BAUDRATE_TABLE \ | |
203 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} | |
bfe18815 JS |
204 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
205 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ | |
206 | ||
bfe18815 JS |
207 | #define CONFIG_FDT_FIXUP_PCI_IRQ 1 |
208 | ||
209 | /* | |
210 | * I2C | |
211 | */ | |
00f792e0 HS |
212 | #define CONFIG_SYS_I2C |
213 | #define CONFIG_SYS_I2C_FSL | |
214 | #define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
215 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
216 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
217 | #define CONFIG_SYS_FSL_I2C2_SPEED 400000 | |
218 | #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F | |
219 | #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 | |
bfe18815 JS |
220 | |
221 | /* I2C DS7505 temperature sensor */ | |
bfe18815 JS |
222 | #define CONFIG_SYS_I2C_LM75_ADDR 0x48 |
223 | ||
224 | /* I2C ADT7461 temperature sensor */ | |
225 | #define CONFIG_SYS_I2C_LM90_ADDR 0x4C | |
226 | ||
227 | /* I2C EEPROM - AT24C128B */ | |
228 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x54 | |
229 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 | |
230 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */ | |
231 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */ | |
232 | ||
233 | /* I2C RTC */ | |
234 | #define CONFIG_RTC_M41T11 1 | |
235 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 | |
236 | #define CONFIG_SYS_M41T11_BASE_YEAR 2000 | |
237 | ||
238 | /* GPIO */ | |
239 | #define CONFIG_PCA953X | |
240 | #define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18 | |
241 | #define CONFIG_SYS_I2C_PCA953X_ADDR1 0x1c | |
242 | #define CONFIG_SYS_I2C_PCA953X_ADDR2 0x1e | |
243 | #define CONFIG_SYS_I2C_PCA953X_ADDR3 0x1f | |
244 | #define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0 | |
245 | ||
246 | /* | |
247 | * GPIO pin definitions, PU = pulled high, PD = pulled low | |
248 | */ | |
249 | /* PCA9557 @ 0x18*/ | |
250 | #define CONFIG_SYS_PCA953X_C0_SER0_EN 0x01 /* PU; UART0 enable (1: enabled) */ | |
251 | #define CONFIG_SYS_PCA953X_C0_SER0_MODE 0x02 /* PU; UART0 serial mode select (1: RS-485, 0: RS-232) */ | |
252 | #define CONFIG_SYS_PCA953X_C0_SER1_EN 0x04 /* PU; UART1 enable (1: enabled) */ | |
253 | #define CONFIG_SYS_PCA953X_C0_SER1_MODE 0x08 /* PU; UART1 serial mode select (1: RS-485, 0: RS-232) */ | |
254 | #define CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS 0x10 /* PU; Boot flash CS select */ | |
255 | #define CONFIG_SYS_PCA953X_NVM_WP 0x20 /* PU; Write protection (0: disabled, 1: enabled) */ | |
256 | ||
257 | /* PCA9557 @ 0x1e*/ | |
258 | #define CONFIG_SYS_PCA953X_XMC_GA0 0x01 /* PU; */ | |
259 | #define CONFIG_SYS_PCA953X_XMC_GA1 0x02 /* PU; */ | |
260 | #define CONFIG_SYS_PCA953X_XMC_GA2 0x04 /* PU; */ | |
261 | #define CONFIG_SYS_PCA953X_XMC_WAKE 0x10 /* PU; */ | |
262 | #define CONFIG_SYS_PCA953X_XMC_BIST 0x20 /* Enable XMC BIST */ | |
263 | #define CONFIG_SYS_PCA953X_PMC_EREADY 0x40 /* PU; PMC PCI eready */ | |
264 | #define CONFIG_SYS_PCA953X_PMC_MONARCH 0x80 /* PMC monarch mode enable */ | |
265 | ||
266 | /* PCA9557 @ 0x1f */ | |
267 | #define CONFIG_SYS_PCA953X_MC_GPIO0 0x01 /* PU; */ | |
268 | #define CONFIG_SYS_PCA953X_MC_GPIO1 0x02 /* PU; */ | |
269 | #define CONFIG_SYS_PCA953X_MC_GPIO2 0x04 /* PU; */ | |
270 | #define CONFIG_SYS_PCA953X_MC_GPIO3 0x08 /* PU; */ | |
271 | #define CONFIG_SYS_PCA953X_MC_GPIO4 0x10 /* PU; */ | |
272 | #define CONFIG_SYS_PCA953X_MC_GPIO5 0x20 /* PU; */ | |
273 | #define CONFIG_SYS_PCA953X_MC_GPIO6 0x40 /* PU; */ | |
274 | #define CONFIG_SYS_PCA953X_MC_GPIO7 0x80 /* PU; */ | |
275 | ||
276 | /* | |
277 | * General PCI | |
278 | * Memory space is mapped 1-1, but I/O space must start from 0. | |
279 | */ | |
280 | ||
281 | /* controller 1 - PEX8112 or XMC, depending on build option */ | |
282 | #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 | |
283 | #define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS | |
284 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x40000000 /* 1G */ | |
285 | #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 | |
286 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xe8000000 | |
287 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */ | |
288 | ||
bfe18815 JS |
289 | /* |
290 | * Networking options | |
291 | */ | |
292 | #define CONFIG_TSEC_ENET /* tsec ethernet support */ | |
293 | #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ | |
bfe18815 JS |
294 | #define CONFIG_TSEC_TBI |
295 | #define CONFIG_MII 1 /* MII PHY management */ | |
296 | #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ | |
297 | #define CONFIG_ETHPRIME "eTSEC2" | |
298 | ||
72c96a68 KG |
299 | /* |
300 | * In-band SGMII auto-negotiation between TBI and BCM5482S PHY fails, force | |
301 | * 1000mbps SGMII link | |
302 | */ | |
303 | #define CONFIG_TSEC_TBICR_SETTINGS ( \ | |
304 | TBICR_PHY_RESET \ | |
305 | | TBICR_FULL_DUPLEX \ | |
306 | | TBICR_SPEED1_SET \ | |
307 | ) | |
308 | ||
bfe18815 JS |
309 | #define CONFIG_TSEC1 1 |
310 | #define CONFIG_TSEC1_NAME "eTSEC1" | |
311 | #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
312 | #define TSEC1_PHY_ADDR 1 | |
313 | #define TSEC1_PHYIDX 0 | |
314 | #define CONFIG_HAS_ETH0 | |
315 | ||
316 | #define CONFIG_TSEC2 1 | |
317 | #define CONFIG_TSEC2_NAME "eTSEC2" | |
318 | #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
319 | #define TSEC2_PHY_ADDR 2 | |
320 | #define TSEC2_PHYIDX 0 | |
321 | #define CONFIG_HAS_ETH1 | |
322 | ||
323 | #define CONFIG_TSEC3 1 | |
324 | #define CONFIG_TSEC3_NAME "eTSEC3" | |
325 | #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
326 | #define TSEC3_PHY_ADDR 3 | |
327 | #define TSEC3_PHYIDX 0 | |
328 | #define CONFIG_HAS_ETH2 | |
329 | ||
330 | /* | |
331 | * USB | |
332 | */ | |
bfe18815 JS |
333 | #define CONFIG_USB_EHCI_FSL |
334 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET | |
bfe18815 JS |
335 | |
336 | /* | |
337 | * Command configuration. | |
338 | */ | |
bfe18815 JS |
339 | #define CONFIG_CMD_PCA953X |
340 | #define CONFIG_CMD_PCA953X_INFO | |
341 | #define CONFIG_CMD_PCI | |
342 | #define CONFIG_CMD_PCI_ENUM | |
bfe18815 | 343 | #define CONFIG_CMD_REGINFO |
bfe18815 JS |
344 | |
345 | /* | |
346 | * Miscellaneous configurable options | |
347 | */ | |
348 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
349 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ | |
bfe18815 JS |
350 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
351 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ | |
352 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
353 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
bfe18815 JS |
354 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ |
355 | #define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ | |
356 | #define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */ | |
bfe18815 JS |
357 | #define CONFIG_PANIC_HANG /* do not reset board on panic */ |
358 | #define CONFIG_PREBOOT /* enable preboot variable */ | |
bfe18815 JS |
359 | #define CONFIG_INTEGRITY /* support booting INTEGRITY OS */ |
360 | ||
361 | /* | |
362 | * For booting Linux, the board info and command line data | |
363 | * have to be in the first 16 MB of memory, since this is | |
364 | * the maximum mapped by the Linux kernel during initialization. | |
365 | */ | |
366 | #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ | |
367 | #define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */ | |
368 | ||
bfe18815 JS |
369 | /* |
370 | * Environment Configuration | |
371 | */ | |
bfe18815 JS |
372 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k (one sector) for env */ |
373 | #define CONFIG_ENV_SIZE 0x8000 | |
374 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - (256 * 1024)) | |
375 | ||
376 | /* | |
377 | * Flash memory map: | |
378 | * fff80000 - ffffffff Pri U-Boot (512 KB) | |
379 | * fff40000 - fff7ffff Pri U-Boot Environment (256 KB) | |
380 | * fff00000 - fff3ffff Pri FDT (256KB) | |
381 | * fef00000 - ffefffff Pri OS image (16MB) | |
382 | * f8000000 - feefffff Pri OS Use/Filesystem (111MB) | |
383 | * | |
384 | * f7f80000 - f7ffffff Sec U-Boot (512 KB) | |
385 | * f7f40000 - f7f7ffff Sec U-Boot Environment (256 KB) | |
386 | * f7f00000 - f7f3ffff Sec FDT (256KB) | |
387 | * f6f00000 - f7efffff Sec OS image (16MB) | |
388 | * f0000000 - f6efffff Sec OS Use/Filesystem (111MB) | |
389 | */ | |
5368c55d MV |
390 | #define CONFIG_UBOOT1_ENV_ADDR __stringify(0xfff80000) |
391 | #define CONFIG_UBOOT2_ENV_ADDR __stringify(0xf7f80000) | |
392 | #define CONFIG_FDT1_ENV_ADDR __stringify(0xfff00000) | |
393 | #define CONFIG_FDT2_ENV_ADDR __stringify(0xf7f00000) | |
394 | #define CONFIG_OS1_ENV_ADDR __stringify(0xfef00000) | |
395 | #define CONFIG_OS2_ENV_ADDR __stringify(0xf6f00000) | |
bfe18815 JS |
396 | |
397 | #define CONFIG_PROG_UBOOT1 \ | |
398 | "$download_cmd $loadaddr $ubootfile; " \ | |
399 | "if test $? -eq 0; then " \ | |
400 | "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ | |
401 | "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ | |
402 | "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; " \ | |
403 | "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ | |
404 | "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; " \ | |
405 | "if test $? -ne 0; then " \ | |
406 | "echo PROGRAM FAILED; " \ | |
407 | "else; " \ | |
408 | "echo PROGRAM SUCCEEDED; " \ | |
409 | "fi; " \ | |
410 | "else; " \ | |
411 | "echo DOWNLOAD FAILED; " \ | |
412 | "fi;" | |
413 | ||
414 | #define CONFIG_PROG_UBOOT2 \ | |
415 | "$download_cmd $loadaddr $ubootfile; " \ | |
416 | "if test $? -eq 0; then " \ | |
417 | "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ | |
418 | "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ | |
419 | "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; " \ | |
420 | "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ | |
421 | "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; " \ | |
422 | "if test $? -ne 0; then " \ | |
423 | "echo PROGRAM FAILED; " \ | |
424 | "else; " \ | |
425 | "echo PROGRAM SUCCEEDED; " \ | |
426 | "fi; " \ | |
427 | "else; " \ | |
428 | "echo DOWNLOAD FAILED; " \ | |
429 | "fi;" | |
430 | ||
431 | #define CONFIG_BOOT_OS_NET \ | |
432 | "$download_cmd $osaddr $osfile; " \ | |
433 | "if test $? -eq 0; then " \ | |
434 | "if test -n $fdtaddr; then " \ | |
435 | "$download_cmd $fdtaddr $fdtfile; " \ | |
436 | "if test $? -eq 0; then " \ | |
437 | "bootm $osaddr - $fdtaddr; " \ | |
438 | "else; " \ | |
439 | "echo FDT DOWNLOAD FAILED; " \ | |
440 | "fi; " \ | |
441 | "else; " \ | |
442 | "bootm $osaddr; " \ | |
443 | "fi; " \ | |
444 | "else; " \ | |
445 | "echo OS DOWNLOAD FAILED; " \ | |
446 | "fi;" | |
447 | ||
448 | #define CONFIG_PROG_OS1 \ | |
449 | "$download_cmd $osaddr $osfile; " \ | |
450 | "if test $? -eq 0; then " \ | |
451 | "erase "CONFIG_OS1_ENV_ADDR" +$filesize; " \ | |
452 | "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \ | |
453 | "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \ | |
454 | "if test $? -ne 0; then " \ | |
455 | "echo OS PROGRAM FAILED; " \ | |
456 | "else; " \ | |
457 | "echo OS PROGRAM SUCCEEDED; " \ | |
458 | "fi; " \ | |
459 | "else; " \ | |
460 | "echo OS DOWNLOAD FAILED; " \ | |
461 | "fi;" | |
462 | ||
463 | #define CONFIG_PROG_OS2 \ | |
464 | "$download_cmd $osaddr $osfile; " \ | |
465 | "if test $? -eq 0; then " \ | |
466 | "erase "CONFIG_OS2_ENV_ADDR" +$filesize; " \ | |
467 | "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \ | |
468 | "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \ | |
469 | "if test $? -ne 0; then " \ | |
470 | "echo OS PROGRAM FAILED; " \ | |
471 | "else; " \ | |
472 | "echo OS PROGRAM SUCCEEDED; " \ | |
473 | "fi; " \ | |
474 | "else; " \ | |
475 | "echo OS DOWNLOAD FAILED; " \ | |
476 | "fi;" | |
477 | ||
478 | #define CONFIG_PROG_FDT1 \ | |
479 | "$download_cmd $fdtaddr $fdtfile; " \ | |
480 | "if test $? -eq 0; then " \ | |
481 | "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;" \ | |
482 | "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \ | |
483 | "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \ | |
484 | "if test $? -ne 0; then " \ | |
485 | "echo FDT PROGRAM FAILED; " \ | |
486 | "else; " \ | |
487 | "echo FDT PROGRAM SUCCEEDED; " \ | |
488 | "fi; " \ | |
489 | "else; " \ | |
490 | "echo FDT DOWNLOAD FAILED; " \ | |
491 | "fi;" | |
492 | ||
493 | #define CONFIG_PROG_FDT2 \ | |
494 | "$download_cmd $fdtaddr $fdtfile; " \ | |
495 | "if test $? -eq 0; then " \ | |
496 | "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;" \ | |
497 | "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \ | |
498 | "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \ | |
499 | "if test $? -ne 0; then " \ | |
500 | "echo FDT PROGRAM FAILED; " \ | |
501 | "else; " \ | |
502 | "echo FDT PROGRAM SUCCEEDED; " \ | |
503 | "fi; " \ | |
504 | "else; " \ | |
505 | "echo FDT DOWNLOAD FAILED; " \ | |
506 | "fi;" | |
507 | ||
508 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
509 | "autoload=yes\0" \ | |
510 | "download_cmd=tftp\0" \ | |
511 | "console_args=console=ttyS0,115200\0" \ | |
512 | "root_args=root=/dev/nfs rw\0" \ | |
513 | "misc_args=ip=on\0" \ | |
514 | "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \ | |
515 | "bootfile=/home/user/file\0" \ | |
516 | "osfile=/home/user/board.uImage\0" \ | |
517 | "fdtfile=/home/user/board.dtb\0" \ | |
518 | "ubootfile=/home/user/u-boot.bin\0" \ | |
b24a4f62 | 519 | "fdtaddr=0x1e00000\0" \ |
bfe18815 JS |
520 | "osaddr=0x1000000\0" \ |
521 | "loadaddr=0x1000000\0" \ | |
522 | "prog_uboot1="CONFIG_PROG_UBOOT1"\0" \ | |
523 | "prog_uboot2="CONFIG_PROG_UBOOT2"\0" \ | |
524 | "prog_os1="CONFIG_PROG_OS1"\0" \ | |
525 | "prog_os2="CONFIG_PROG_OS2"\0" \ | |
526 | "prog_fdt1="CONFIG_PROG_FDT1"\0" \ | |
527 | "prog_fdt2="CONFIG_PROG_FDT2"\0" \ | |
528 | "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \ | |
529 | "bootcmd_flash1=run set_bootargs; " \ | |
530 | "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\ | |
531 | "bootcmd_flash2=run set_bootargs; " \ | |
532 | "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\ | |
533 | "bootcmd=run bootcmd_flash1\0" | |
534 | #endif /* __CONFIG_H */ |