[people/ms/u-boot.git] / include / configs / yellowstone.h

/*
 * (C) Copyright 2005-2006
 * Stefan Roese, DENX Software Engineering, sr@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/************************************************************************
 * yellowstone.h - configuration for YELLOWSTONE board
 ***********************************************************************/
#ifndef __CONFIG_H
#define __CONFIG_H

/*-----------------------------------------------------------------------
 * High Level Configuration Options
 *----------------------------------------------------------------------*/
#define CONFIG_YOLLOWSTONE	1	/* Board is Yellowstone         */
#define CONFIG_440GR		1	/* Specific PPC440EP support    */
#define CONFIG_4xx		1	/* ... PPC4xx family	        */
#define CONFIG_SYS_CLK_FREQ	66666666    /* external freq to pll	*/

#define CONFIG_BOARD_EARLY_INIT_F 1     /* Call board_early_init_f	*/
#define CONFIG_MISC_INIT_R	1	/* call misc_init_r()		*/

/*-----------------------------------------------------------------------
 * Base addresses -- Note these are effective addresses where the
 * actual resources get mapped (not physical addresses)
 *----------------------------------------------------------------------*/
#define CFG_MONITOR_LEN		(512 * 1024)	/* Reserve 512 kB for Monitor	*/
#define CFG_MALLOC_LEN		(256 * 1024)	/* Reserve 256 kB for malloc()	*/
#define CFG_MONITOR_BASE	(-CFG_MONITOR_LEN)
#define CFG_SDRAM_BASE	        0x00000000	    /* _must_ be 0	*/
#define CFG_FLASH_BASE	        0xfc000000	    /* start of FLASH	*/
#define CFG_PCI_MEMBASE	        0xa0000000	    /* mapped pci memory*/
#define CFG_PCI_MEMBASE1        CFG_PCI_MEMBASE  + 0x10000000
#define CFG_PCI_MEMBASE2        CFG_PCI_MEMBASE1 + 0x10000000
#define CFG_PCI_MEMBASE3        CFG_PCI_MEMBASE2 + 0x10000000

/*Don't change either of these*/
#define CFG_PERIPHERAL_BASE     0xef600000	    /* internal peripherals*/
#define CFG_PCI_BASE	        0xe0000000	    /* internal PCI regs*/
/*Don't change either of these*/

#define CFG_USB_DEVICE          0x50000000
#define CFG_NVRAM_BASE_ADDR     0x80000000
#define CFG_BCSR_BASE	        (CFG_NVRAM_BASE_ADDR | 0x2000)
#define CFG_BOOT_BASE_ADDR      0xf0000000

/*-----------------------------------------------------------------------
 * Initial RAM & stack pointer (placed in SDRAM)
 *----------------------------------------------------------------------*/
#define CFG_INIT_RAM_DCACHE	1		/* d-cache as init ram	*/
#define CFG_INIT_RAM_ADDR	0x70000000		/* DCache       */
#define CFG_INIT_RAM_END	(8 << 10)
#define CFG_GBL_DATA_SIZE	256			/* num bytes initial data*/
#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * Serial Port
 *----------------------------------------------------------------------*/
#define CFG_EXT_SERIAL_CLOCK	11059200 /* use external 11.059MHz clk	*/
#define CONFIG_BAUDRATE		115200
#define CONFIG_SERIAL_MULTI     1
/*define this if you want console on UART1*/
#undef CONFIG_UART1_CONSOLE

#define CFG_BAUDRATE_TABLE  \
    {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}

/*-----------------------------------------------------------------------
 * Environment
 *----------------------------------------------------------------------*/
/*
 * Define here the location of the environment variables (FLASH or EEPROM).
 * Note: DENX encourages to use redundant environment in FLASH.
 */
#if 1
#define CFG_ENV_IS_IN_FLASH     1	/* use FLASH for environment vars	*/
#else
#define CFG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars	*/
#endif

/*-----------------------------------------------------------------------
 * FLASH related
 *----------------------------------------------------------------------*/
#define CFG_FLASH_CFI				/* The flash is CFI compatible	*/
#define CFG_FLASH_CFI_DRIVER			/* Use common CFI driver	*/
#define CFG_FLASH_CFI_AMD_RESET 1		/* AMD RESET for STM 29W320DB!	*/

#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
#define CFG_MAX_FLASH_SECT	512	/* max number of sectors on one chip	*/

#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */

#ifdef CFG_ENV_IS_IN_FLASH
#define CFG_ENV_SECT_SIZE	0x20000 	/* size of one complete sector	*/
#define CFG_ENV_ADDR		(CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
#define	CFG_ENV_SIZE		0x2000	/* Total Size of Environment Sector	*/

/* Address and size of Redundant Environment Sector	*/
#define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)
#endif /* CFG_ENV_IS_IN_FLASH */

/*-----------------------------------------------------------------------
 * DDR SDRAM
 *----------------------------------------------------------------------*/
#undef CONFIG_SPD_EEPROM	       /* Don't use SPD EEPROM for setup    */
#define CFG_KBYTES_SDRAM        (128 * 1024)    /* 128MB		    */
#define CFG_SDRAM_BANKS	        (2)


/*-----------------------------------------------------------------------
 * I2C
 *----------------------------------------------------------------------*/
#define CONFIG_HARD_I2C		1	    /* I2C with hardware support	*/
#undef	CONFIG_SOFT_I2C			    /* I2C bit-banged		*/
#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
#define CFG_I2C_SLAVE		0x7F

#define CFG_I2C_MULTI_EEPROMS
#define CFG_I2C_EEPROM_ADDR	(0xa8>>1)
#define CFG_I2C_EEPROM_ADDR_LEN 1
#define CFG_EEPROM_PAGE_WRITE_ENABLE
#define CFG_EEPROM_PAGE_WRITE_BITS 3
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10

#ifdef CFG_ENV_IS_IN_EEPROM
#define CFG_ENV_SIZE		0x200	    /* Size of Environment vars */
#define CFG_ENV_OFFSET		0x0
#endif /* CFG_ENV_IS_IN_EEPROM */

#define CONFIG_PREBOOT	"echo;"	\
	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
	"echo"

#undef	CONFIG_BOOTARGS

#define	CONFIG_EXTRA_ENV_SETTINGS					\
	"netdev=eth0\0"							\
	"hostname=yellowstone\0"					\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=${serverip}:${rootpath}\0"			\
	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
	"addip=setenv bootargs ${bootargs} "				\
		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
		":${hostname}:${netdev}:off panic=1\0"			\
	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
	"flash_nfs=run nfsargs addip addtty;"				\
		"bootm ${kernel_addr}\0"				\
	"flash_self=run ramargs addip addtty;"				\
		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
	        "bootm\0"						\
	"rootpath=/opt/eldk/ppc_4xx\0"					\
	"bootfile=/tftpboot/yellowstone/uImage\0"			\
	"kernel_addr=fc000000\0"					\
	"ramdisk_addr=fc180000\0"					\
	"load=tftp 100000 /tftpboot/yellowstone/u-boot.bin\0"		\
	"update=protect off fff80000 ffffffff;era fff80000 ffffffff;"	\
		"cp.b 100000 fff80000 80000;"			        \
		"setenv filesize;saveenv\0"				\
	"upd=run load;run update\0"					\
	""
#define CONFIG_BOOTCOMMAND	"run flash_self"

#if 0
#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
#else
#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
#endif

#define CONFIG_BAUDRATE		115200

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/

#define CONFIG_MII		1	/* MII PHY management		*/
#define CONFIG_NET_MULTI        1	/* required for netconsole      */
#define CONFIG_PHY1_ADDR        3
#define CONFIG_HAS_ETH1		1	/* add support for "eth1addr"	*/
#define CONFIG_PHY_ADDR		1	/* PHY address, See schematics	*/

#define CFG_RX_ETH_BUFFER	32	/* Number of ethernet rx buffers & descriptors */

#define CONFIG_NETCONSOLE		/* include NetConsole support	*/

/* Partitions */
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_ISO_PARTITION

#ifdef CONFIG_440EP
/* USB */
#define CONFIG_USB_OHCI
#define CONFIG_USB_STORAGE

/*Comment this out to enable USB 1.1 device*/
#define USB_2_0_DEVICE
#endif /*CONFIG_440EP*/

#ifdef DEBUG
#define CONFIG_PANIC_HANG
#else
#define CONFIG_HW_WATCHDOG			/* watchdog */
#endif

#define CONFIG_COMMANDS	       (CONFIG_CMD_DFL	| \
				CFG_CMD_ASKENV	| \
				CFG_CMD_DHCP	| \
				CFG_CMD_DIAG	| \
				CFG_CMD_ELF	| \
				CFG_CMD_EEPROM	| \
				CFG_CMD_I2C	| \
				CFG_CMD_IRQ	| \
				CFG_CMD_MII	| \
				CFG_CMD_NET	| \
				CFG_CMD_NFS	| \
				CFG_CMD_PCI	| \
				CFG_CMD_PING	| \
				CFG_CMD_REGINFO	| \
				CFG_CMD_SDRAM)

/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>

/*
 * Miscellaneous configurable options
 */
#define CFG_LONGHELP			/* undef to save memory		*/
#define CFG_PROMPT	        "=> "	/* Monitor Command Prompt	*/
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CBSIZE	        1024	/* Console I/O Buffer Size	*/
#else
#define CFG_CBSIZE	        256	/* Console I/O Buffer Size	*/
#endif
#define CFG_PBSIZE              (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS	        16	/* max number of command args	*/
#define CFG_BARGSIZE	        CFG_CBSIZE /* Boot Argument Buffer Size	*/

#define CFG_MEMTEST_START	0x0400000 /* memtest works on	        */
#define CFG_MEMTEST_END		0x0C00000 /* 4 ... 12 MB in DRAM	*/

#define CFG_LOAD_ADDR		0x100000	/* default load address */
#define CFG_EXTBDINFO		1	/* To use extended board_into (bd_t) */
#define CONFIG_LYNXKDI          1       /* support kdi files            */

#define CFG_HZ		        1000	/* decrementer freq: 1 ms ticks */

#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
#define CONFIG_LOOPW            1       /* enable loopw command         */
#define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */

/*-----------------------------------------------------------------------
 * PCI stuff
 *-----------------------------------------------------------------------
 */
/* General PCI */
#define CONFIG_PCI			/* include pci support	        */
#undef  CONFIG_PCI_PNP			/* do (not) pci plug-and-play   */
#define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup  */
#define CFG_PCI_TARGBASE        0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/

/* Board-specific PCI */
#define CFG_PCI_PRE_INIT                /* enable board pci_pre_init()  */
#define CFG_PCI_TARGET_INIT
#define CFG_PCI_MASTER_INIT

#define CFG_PCI_SUBSYS_VENDORID 0x10e8	/* AMCC */
#define CFG_PCI_SUBSYS_ID       0xcafe	/* Whatever */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CFG_DCACHE_SIZE		(32<<10) /* For AMCC 440 CPUs			*/
#define CFG_CACHELINE_SIZE	32	/* ...			*/
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
#endif

/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
#define BOOTFLAG_WARM	0x02		/* Software reboot			*/

#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
#endif

#endif	/* __CONFIG_H */
Commit	Line	Data
c157d8e2	1	/*
56ced709	2	* (C) Copyright 2005-2006
34c0a5e9	3	* Stefan Roese, DENX Software Engineering, sr@denx.de.
c157d8e2 SR	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	/************************************************************************
	25	* yellowstone.h - configuration for YELLOWSTONE board
	26	***********************************************************************/
	27	#ifndef __CONFIG_H
	28	#define __CONFIG_H
	29
	30	/*-----------------------------------------------------------------------
	31	* High Level Configuration Options
	32	----------------------------------------------------------------------/
34c0a5e9 SR	33	#define CONFIG_YOLLOWSTONE 1 /* Board is Yellowstone */
	34	#define CONFIG_440GR 1 /* Specific PPC440EP support */
	35	#define CONFIG_4xx 1 /* ... PPC4xx family */
c157d8e2 SR	36	#define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */
c157d8e2 SR	37
34c0a5e9 SR	38	#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
	39	#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
	40
c157d8e2 SR	41	/*-----------------------------------------------------------------------
	42	* Base addresses -- Note these are effective addresses where the
	43	* actual resources get mapped (not physical addresses)
	44	----------------------------------------------------------------------/
34c0a5e9 SR	45	#define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */
	46	#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
	47	#define CFG_MONITOR_BASE (-CFG_MONITOR_LEN)
	48	#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
	49	#define CFG_FLASH_BASE 0xfc000000 /* start of FLASH */
	50	#define CFG_PCI_MEMBASE 0xa0000000 /* mapped pci memory*/
	51	#define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000
	52	#define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000
	53	#define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000
c157d8e2 SR	54
c157d8e2 SR	55	/Don't change either of these/
34c0a5e9 SR	56	#define CFG_PERIPHERAL_BASE 0xef600000 /* internal peripherals*/
34c0a5e9 SR	57	#define CFG_PCI_BASE 0xe0000000 /* internal PCI regs*/
c157d8e2 SR	58	/Don't change either of these/
c157d8e2 SR	59
34c0a5e9 SR	60	#define CFG_USB_DEVICE 0x50000000
	61	#define CFG_NVRAM_BASE_ADDR 0x80000000
	62	#define CFG_BCSR_BASE (CFG_NVRAM_BASE_ADDR \| 0x2000)
	63	#define CFG_BOOT_BASE_ADDR 0xf0000000
c157d8e2 SR	64
	65	/*-----------------------------------------------------------------------
	66	* Initial RAM & stack pointer (placed in SDRAM)
	67	----------------------------------------------------------------------/
887e2ec9	68	#define CFG_INIT_RAM_DCACHE 1 /* d-cache as init ram */
34c0a5e9 SR	69	#define CFG_INIT_RAM_ADDR 0x70000000 /* DCache */
	70	#define CFG_INIT_RAM_END (8 << 10)
	71	#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data*/
c157d8e2 SR	72	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
	73	#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
	74
c157d8e2 SR	75	/*-----------------------------------------------------------------------
	76	* Serial Port
	77	----------------------------------------------------------------------/
c157d8e2	78	#define CFG_EXT_SERIAL_CLOCK 11059200 /* use external 11.059MHz clk */
34c0a5e9 SR	79	#define CONFIG_BAUDRATE 115200
34c0a5e9 SR	80	#define CONFIG_SERIAL_MULTI 1
c157d8e2 SR	81	/define this if you want console on UART1/
	82	#undef CONFIG_UART1_CONSOLE
	83
	84	#define CFG_BAUDRATE_TABLE \
	85	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
	86
	87	/*-----------------------------------------------------------------------
34c0a5e9	88	* Environment
c157d8e2	89	----------------------------------------------------------------------/
34c0a5e9 SR	90	/*
	91	* Define here the location of the environment variables (FLASH or EEPROM).
	92	* Note: DENX encourages to use redundant environment in FLASH.
	93	*/
	94	#if 1
	95	#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
	96	#else
	97	#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
	98	#endif
c157d8e2 SR	99
	100	/*-----------------------------------------------------------------------
	101	* FLASH related
	102	----------------------------------------------------------------------/
34c0a5e9 SR	103	#define CFG_FLASH_CFI /* The flash is CFI compatible */
	104	#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
	105	#define CFG_FLASH_CFI_AMD_RESET 1 /* AMD RESET for STM 29W320DB! */
	106
	107	#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
	108	#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
c157d8e2	109
c157d8e2	110	#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
34c0a5e9 SR	111	#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
	112
	113	#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
	114
	115	#ifdef CFG_ENV_IS_IN_FLASH
	116	#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
	117	#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
	118	#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
	119
	120	/* Address and size of Redundant Environment Sector */
	121	#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
	122	#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
	123	#endif /* CFG_ENV_IS_IN_FLASH */
c157d8e2 SR	124
	125	/*-----------------------------------------------------------------------
	126	* DDR SDRAM
	127	----------------------------------------------------------------------/
095b8a37	128	#undef CONFIG_SPD_EEPROM /* Don't use SPD EEPROM for setup */
34c0a5e9 SR	129	#define CFG_KBYTES_SDRAM (128 * 1024) /* 128MB */
	130	#define CFG_SDRAM_BANKS (2)
	131
c157d8e2 SR	132
	133	/*-----------------------------------------------------------------------
	134	* I2C
	135	----------------------------------------------------------------------/
	136	#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
	137	#undef CONFIG_SOFT_I2C /* I2C bit-banged */
	138	#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
	139	#define CFG_I2C_SLAVE 0x7F
	140
c157d8e2	141	#define CFG_I2C_MULTI_EEPROMS
c157d8e2 SR	142	#define CFG_I2C_EEPROM_ADDR (0xa8>>1)
	143	#define CFG_I2C_EEPROM_ADDR_LEN 1
	144	#define CFG_EEPROM_PAGE_WRITE_ENABLE
	145	#define CFG_EEPROM_PAGE_WRITE_BITS 3
	146	#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
	147
34c0a5e9 SR	148	#ifdef CFG_ENV_IS_IN_EEPROM
	149	#define CFG_ENV_SIZE 0x200 /* Size of Environment vars */
	150	#define CFG_ENV_OFFSET 0x0
	151	#endif /* CFG_ENV_IS_IN_EEPROM */
	152
	153	#define CONFIG_PREBOOT "echo;" \
	154	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
	155	"echo"
	156
	157	#undef CONFIG_BOOTARGS
	158
	159	#define CONFIG_EXTRA_ENV_SETTINGS \
	160	"netdev=eth0\0" \
	161	"hostname=yellowstone\0" \
	162	"nfsargs=setenv bootargs root=/dev/nfs rw " \
fe126d8b	163	"nfsroot=${serverip}:${rootpath}\0" \
34c0a5e9	164	"ramargs=setenv bootargs root=/dev/ram rw\0" \
fe126d8b WD	165	"addip=setenv bootargs ${bootargs} " \
	166	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
	167	":${hostname}:${netdev}:off panic=1\0" \
	168	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
34c0a5e9	169	"flash_nfs=run nfsargs addip addtty;" \
fe126d8b	170	"bootm ${kernel_addr}\0" \
34c0a5e9	171	"flash_self=run ramargs addip addtty;" \
fe126d8b WD	172	"bootm ${kernel_addr} ${ramdisk_addr}\0" \
fe126d8b WD	173	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
34c0a5e9 SR	174	"bootm\0" \
	175	"rootpath=/opt/eldk/ppc_4xx\0" \
	176	"bootfile=/tftpboot/yellowstone/uImage\0" \
	177	"kernel_addr=fc000000\0" \
56ced709	178	"ramdisk_addr=fc180000\0" \
34c0a5e9 SR	179	"load=tftp 100000 /tftpboot/yellowstone/u-boot.bin\0" \
	180	"update=protect off fff80000 ffffffff;era fff80000 ffffffff;" \
	181	"cp.b 100000 fff80000 80000;" \
	182	"setenv filesize;saveenv\0" \
	183	"upd=run load;run update\0" \
	184	""
	185	#define CONFIG_BOOTCOMMAND "run flash_self"
	186
	187	#if 0
	188	#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
	189	#else
	190	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
	191	#endif
	192
	193	#define CONFIG_BAUDRATE 115200
c157d8e2	194
34c0a5e9	195	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
c157d8e2 SR	196	#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
c157d8e2 SR	197
34c0a5e9 SR	198	#define CONFIG_MII 1 /* MII PHY management */
	199	#define CONFIG_NET_MULTI 1 /* required for netconsole */
	200	#define CONFIG_PHY1_ADDR 3
c157d8e2 SR	201	#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
c157d8e2 SR	202	#define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */
c157d8e2	203
1e25f957 SR	204	#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
	205
	206	#define CONFIG_NETCONSOLE /* include NetConsole support */
c157d8e2 SR	207
	208	/* Partitions */
	209	#define CONFIG_MAC_PARTITION
	210	#define CONFIG_DOS_PARTITION
	211	#define CONFIG_ISO_PARTITION
	212
846b0dd2	213	#ifdef CONFIG_440EP
c157d8e2 SR	214	/* USB */
	215	#define CONFIG_USB_OHCI
	216	#define CONFIG_USB_STORAGE
	217
	218	/Comment this out to enable USB 1.1 device/
	219	#define USB_2_0_DEVICE
846b0dd2	220	#endif /CONFIG_440EP/
c157d8e2 SR	221
	222	#ifdef DEBUG
	223	#define CONFIG_PANIC_HANG
	224	#else
	225	#define CONFIG_HW_WATCHDOG /* watchdog */
	226	#endif
	227
34c0a5e9 SR	228	#define CONFIG_COMMANDS (CONFIG_CMD_DFL \| \
	229	CFG_CMD_ASKENV \| \
	230	CFG_CMD_DHCP \| \
	231	CFG_CMD_DIAG \| \
	232	CFG_CMD_ELF \| \
4f92ed5f	233	CFG_CMD_EEPROM \| \
34c0a5e9 SR	234	CFG_CMD_I2C \| \
	235	CFG_CMD_IRQ \| \
	236	CFG_CMD_MII \| \
	237	CFG_CMD_NET \| \
	238	CFG_CMD_NFS \| \
	239	CFG_CMD_PCI \| \
	240	CFG_CMD_PING \| \
	241	CFG_CMD_REGINFO \| \
	242	CFG_CMD_SDRAM)
c157d8e2 SR	243
	244	/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
	245	#include <cmd_confdefs.h>
	246
	247	/*
	248	* Miscellaneous configurable options
	249	*/
	250	#define CFG_LONGHELP /* undef to save memory */
34c0a5e9	251	#define CFG_PROMPT "=> " /* Monitor Command Prompt */
c157d8e2	252	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
34c0a5e9	253	#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
c157d8e2	254	#else
34c0a5e9	255	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
c157d8e2	256	#endif
34c0a5e9 SR	257	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
	258	#define CFG_MAXARGS 16 /* max number of command args */
	259	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
c157d8e2	260
34c0a5e9 SR	261	#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
34c0a5e9 SR	262	#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
c157d8e2 SR	263
c157d8e2 SR	264	#define CFG_LOAD_ADDR 0x100000 /* default load address */
34c0a5e9 SR	265	#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
34c0a5e9 SR	266	#define CONFIG_LYNXKDI 1 /* support kdi files */
c157d8e2	267
34c0a5e9	268	#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
c157d8e2	269
4f92ed5f SR	270	#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
	271	#define CONFIG_LOOPW 1 /* enable loopw command */
	272	#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
	273	#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
	274	#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
	275
c157d8e2 SR	276	/*-----------------------------------------------------------------------
	277	* PCI stuff
	278	*-----------------------------------------------------------------------
	279	*/
	280	/* General PCI */
34c0a5e9 SR	281	#define CONFIG_PCI /* include pci support */
	282	#undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */
	283	#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
	284	#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/
c157d8e2 SR	285
c157d8e2 SR	286	/* Board-specific PCI */
34c0a5e9	287	#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */
c157d8e2 SR	288	#define CFG_PCI_TARGET_INIT
	289	#define CFG_PCI_MASTER_INIT
	290
34c0a5e9 SR	291	#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
34c0a5e9 SR	292	#define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */
c157d8e2 SR	293
	294	/*
	295	* For booting Linux, the board info and command line data
	296	* have to be in the first 8 MB of memory, since this is
	297	* the maximum mapped by the Linux kernel during initialization.
	298	*/
	299	#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
34c0a5e9	300
c157d8e2 SR	301	/*-----------------------------------------------------------------------
	302	* Cache Configuration
	303	*/
0c8721a4	304	#define CFG_DCACHE_SIZE (32<<10) /* For AMCC 440 CPUs */
c157d8e2 SR	305	#define CFG_CACHELINE_SIZE 32 /* ... */
	306	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
	307	#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
	308	#endif
	309
	310	/*
	311	* Internal Definitions
	312	*
	313	* Boot Flags
	314	*/
	315	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
	316	#define BOOTFLAG_WARM 0x02 /* Software reboot */
	317
	318	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
	319	#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
	320	#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
	321	#endif
34c0a5e9	322
c157d8e2	323	#endif /* __CONFIG_H */