[people/ms/u-boot.git] / include / configs / yosemite.h

/*
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/************************************************************************
 * yosemite.h - configuration for YOSEMITE board
 ***********************************************************************/
#ifndef __CONFIG_H
#define __CONFIG_H

/*-----------------------------------------------------------------------
 * High Level Configuration Options
 *----------------------------------------------------------------------*/
#define CONFIG_YOSEMITE				1	/* Board is BAMBOO           */
#define CONFIG_440_EP				1	/* Specific PPC440EP support */

#define CONFIG_4xx					1	/* ... PPC4xx family	*/
#define CONFIG_BOARD_EARLY_INIT_F 	1   /* Call board_early_init_f	*/
#undef	CFG_DRAM_TEST					/* disable - takes long time! */
#define CONFIG_SYS_CLK_FREQ	66666666    /* external freq to pll	*/

/*-----------------------------------------------------------------------
 * Base addresses -- Note these are effective addresses where the
 * actual resources get mapped (not physical addresses)
 *----------------------------------------------------------------------*/
#define CFG_SDRAM_BASE	    0x00000000	    /* _must_ be 0		    */
#define CFG_FLASH_BASE	    0xfe000000	    /* start of FLASH		*/
#define CFG_MONITOR_BASE    TEXT_BASE	    /* start of monitor		*/
#define CFG_PCI_MEMBASE	    0xa0000000	    /* mapped pci memory	*/
#define CFG_PCI_MEMBASE1    CFG_PCI_MEMBASE  + 0x10000000
#define CFG_PCI_MEMBASE2    CFG_PCI_MEMBASE1 + 0x10000000
#define CFG_PCI_MEMBASE3    CFG_PCI_MEMBASE2 + 0x10000000


/*Don't change either of these*/
#define CFG_PERIPHERAL_BASE 0xef600000	    /* internal peripherals	*/
#define CFG_PCI_BASE	    0xe0000000	    /* internal PCI regs	*/
/*Don't change either of these*/

#define CFG_USB_DEVICE 0x50000000
#define CFG_NVRAM_BASE_ADDR 0x80000000
#define CFG_BCSR_BASE	    (CFG_NVRAM_BASE_ADDR | 0x2000)

/*-----------------------------------------------------------------------
 * Initial RAM & stack pointer (placed in SDRAM)
 *----------------------------------------------------------------------*/
#define CFG_INIT_RAM_ADDR	  0xf0000000		/* DCache */
#define CFG_INIT_RAM_END	0x2000
#define CFG_GBL_DATA_SIZE	256		    	/* num bytes initial data	*/
#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET

#define CFG_MONITOR_LEN	    (256 * 1024)    /* Reserve 256 kB for Mon	*/
#define CFG_MALLOC_LEN	    (128 * 1024)    /* Reserve 128 kB for malloc*/
#define CFG_KBYTES_SDRAM	( 128 * 1024)	/* 128MB                     */
#define CFG_SDRAM_BANKS     (2)
/*-----------------------------------------------------------------------
 * Serial Port
 *----------------------------------------------------------------------*/
#undef	CONFIG_SERIAL_SOFTWARE_FIFO
#define CFG_EXT_SERIAL_CLOCK	11059200 /* use external 11.059MHz clk	*/
#define CONFIG_BAUDRATE			9600
#define CONFIG_SERIAL_MULTI   1
/*define this if you want console on UART1*/
#undef CONFIG_UART1_CONSOLE

#define CFG_BAUDRATE_TABLE  \
    {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}

/*-----------------------------------------------------------------------
 * NVRAM/RTC
 *
 * NOTE: The RTC registers are located at 0x7FFF0 - 0x7FFFF
 * The DS1558 code assumes this condition
 *
 *----------------------------------------------------------------------*/
#define CFG_NVRAM_SIZE	    (0x2000 - 0x10) /* NVRAM size(8k)- RTC regs */
#define CONFIG_RTC_DS1556	1		         /* DS1556 RTC		*/

/*-----------------------------------------------------------------------
 * FLASH related
 *----------------------------------------------------------------------*/
#if 1 /* test-only */
#define CFG_MAX_FLASH_BANKS	1		    /* number of banks	    */
#define CFG_MAX_FLASH_SECT	256		    /* sectors per device   */

#undef	CFG_FLASH_CHECKSUM
#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CFG_FLASH_WRITE_TOUT	120000	    /* Timeout for Flash Write (in ms)	*/
#else
#define CFG_FLASH_CFI				/* The flash is CFI compatible  */
#define CFG_FLASH_CFI_DRIVER			/* Use common CFI driver        */
#define CFG_FLASH_CFI_AMD_RESET	1		/* AMD RESET for STM 29W320DB!  */

#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
#define CFG_MAX_FLASH_SECT	512	/* max number of sectors on one chip	*/

#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
#endif

/*-----------------------------------------------------------------------
 * DDR SDRAM
 *----------------------------------------------------------------------*/
#undef CONFIG_SPD_EEPROM               /* Don't use SPD EEPROM for setup    */

/*-----------------------------------------------------------------------
 * I2C
 *----------------------------------------------------------------------*/
#define CONFIG_HARD_I2C		1	    /* I2C with hardware support	*/
#undef	CONFIG_SOFT_I2C			    /* I2C bit-banged		*/
#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
#define CFG_I2C_SLAVE		0x7F


/*-----------------------------------------------------------------------
 * Environment
 *----------------------------------------------------------------------*/
#undef  CFG_ENV_IS_IN_NVRAM		    /*No NVRAM on board*/
#undef	CFG_ENV_IS_IN_FLASH		    /* ... not in flash		*/
#define CFG_ENV_IS_IN_EEPROM 1

/* Define to allow the user to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE

#define CFG_I2C_MULTI_EEPROMS
#define CFG_ENV_SIZE		0x200	    /* Size of Environment vars */
#define CFG_ENV_OFFSET		0x0
#define CFG_I2C_EEPROM_ADDR	(0xa8>>1)
#define CFG_I2C_EEPROM_ADDR_LEN 1
#define CFG_EEPROM_PAGE_WRITE_ENABLE
#define CFG_EEPROM_PAGE_WRITE_BITS 3
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10

#define CONFIG_BOOTCOMMAND	"bootm 0xfe000000"    /* autoboot command */
#define CONFIG_BOOTDELAY	3		    /* disable autoboot */

#define CONFIG_LOADS_ECHO		1	/* echo on for serial download	*/
#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/

#define CONFIG_MII			1	/* MII PHY management		*/
#define CONFIG_NET_MULTI    1   /* required for netconsole  */
#define CONFIG_PHY1_ADDR    3
#define CONFIG_HAS_ETH1		1	/* add support for "eth1addr"	*/
#define CONFIG_PHY_ADDR		1	/* PHY address, See schematics	*/
#define CONFIG_NETMASK		255.255.255.0
#define CONFIG_IPADDR		10.0.4.251
#define CONFIG_ETHADDR		00:10:EC:00:12:34
#define CONFIG_ETH1ADDR		00:10:EC:00:12:35

#define CFG_RX_ETH_BUFFER	32	  /* Number of ethernet rx buffers & descriptors */
#define CONFIG_SERVERIP		10.0.4.115

/* Partitions */
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_ISO_PARTITION

#ifdef CONFIG_440_EP
/* USB */
#define CONFIG_USB_OHCI
#define CONFIG_USB_STORAGE

/*Comment this out to enable USB 1.1 device*/
#define USB_2_0_DEVICE
#endif /*CONFIG_440_EP*/

#ifdef DEBUG
#define CONFIG_PANIC_HANG
#else
#define CONFIG_HW_WATCHDOG			/* watchdog */
#endif

#ifdef CONFIG_440_EP
	/* Need to define POST */
#define CONFIG_COMMANDS	       ((CONFIG_CMD_DFL	| \
			CFG_CMD_DATE	|   \
			CFG_CMD_DHCP	|   \
			CFG_CMD_DIAG	|   \
			CFG_CMD_ECHO	|   \
			CFG_CMD_EEPROM	|   \
			CFG_CMD_ELF	|   \
    /*      CFG_CMD_EXT2    |*/ \
	/*		CFG_CMD_FAT		|*/	\
			CFG_CMD_I2C	|	\
	/*		CFG_CMD_IDE		|*/	\
			CFG_CMD_IRQ	|	\
    /*     	CFG_CMD_KGDB	|*/	\
            		CFG_CMD_MII     |   \
			CFG_CMD_PCI		|	\
			CFG_CMD_PING	| 	\
			CFG_CMD_REGINFO | 	\
			CFG_CMD_SDRAM	|   \
			CFG_CMD_FLASH   |   \
	/*		CFG_CMD_SPI		|*/	\
			CFG_CMD_USB	|	\
			0 ) & ~CFG_CMD_IMLS)
#else
#define CONFIG_COMMANDS	       ((CONFIG_CMD_DFL	| \
			CFG_CMD_DATE	|   \
			CFG_CMD_DHCP	|   \
			CFG_CMD_DIAG	|   \
			CFG_CMD_ECHO	|   \
			CFG_CMD_EEPROM	|   \
			CFG_CMD_ELF	|   \
    /*      CFG_CMD_EXT2    |*/ \
	/*		CFG_CMD_FAT		|*/	\
			CFG_CMD_I2C	|	\
	/*		CFG_CMD_IDE		|*/	\
			CFG_CMD_IRQ	|	\
    /*     	CFG_CMD_KGDB	|*/	\
            		CFG_CMD_MII     |   \
			CFG_CMD_PCI		|	\
			CFG_CMD_PING	| 	\
			CFG_CMD_REGINFO | 	\
			CFG_CMD_SDRAM	|   \
			CFG_CMD_FLASH   |   \
	/*		CFG_CMD_SPI		|*/	\
			0 ) & ~CFG_CMD_IMLS)
#endif

/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>

/*
 * Miscellaneous configurable options
 */
#define CFG_LONGHELP			/* undef to save memory		*/
#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
#else
#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS	16		/* max number of command args	*/
#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/

#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/

#define CFG_LOAD_ADDR		0x100000	/* default load address */
#define CFG_EXTBDINFO		    1	/* To use extended board_into (bd_t) */
#define CONFIG_LYNXKDI          1   /* support kdi files */

#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */

/*-----------------------------------------------------------------------
 * PCI stuff
 *-----------------------------------------------------------------------
 */
/* General PCI */
#define CONFIG_PCI			            /* include pci support	        */
#undef  CONFIG_PCI_PNP			        /* do (not) pci plug-and-play         */
#define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup  */
#define CFG_PCI_TARGBASE    0x80000000  /* PCIaddr mapped to CFG_PCI_MEMBASE */

/* Board-specific PCI */
#define CFG_PCI_PRE_INIT                /* enable board pci_pre_init()  */
#define CFG_PCI_TARGET_INIT
#define CFG_PCI_MASTER_INIT

#define CFG_PCI_SUBSYS_VENDORID 0x1014  /* IBM */
#define CFG_PCI_SUBSYS_ID 0xcafe        /* Whatever */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CFG_DCACHE_SIZE		8192	/* For IBM 405 CPUs			*/
#define CFG_CACHELINE_SIZE	32	/* ...			*/
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
#endif

/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
#define BOOTFLAG_WARM	0x02		/* Software reboot			*/

#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
#endif
#endif	/* __CONFIG_H */
Commit	Line	Data
c157d8e2 SR	1	/*
	2	*
	3	* See file CREDITS for list of people who contributed to this
	4	* project.
	5	*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public License as
	8	* published by the Free Software Foundation; either version 2 of
	9	* the License, or (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, write to the Free Software
	18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	19	* MA 02111-1307 USA
	20	*/
	21
	22	/************************************************************************
	23	* yosemite.h - configuration for YOSEMITE board
	24	***********************************************************************/
	25	#ifndef __CONFIG_H
	26	#define __CONFIG_H
	27
	28	/*-----------------------------------------------------------------------
	29	* High Level Configuration Options
	30	----------------------------------------------------------------------/
	31	#define CONFIG_YOSEMITE 1 /* Board is BAMBOO */
	32	#define CONFIG_440_EP 1 /* Specific PPC440EP support */
	33
	34	#define CONFIG_4xx 1 /* ... PPC4xx family */
	35	#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
	36	#undef CFG_DRAM_TEST /* disable - takes long time! */
	37	#define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */
	38
	39	/*-----------------------------------------------------------------------
	40	* Base addresses -- Note these are effective addresses where the
	41	* actual resources get mapped (not physical addresses)
	42	----------------------------------------------------------------------/
	43	#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
	44	#define CFG_FLASH_BASE 0xfe000000 /* start of FLASH */
	45	#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
	46	#define CFG_PCI_MEMBASE 0xa0000000 /* mapped pci memory */
	47	#define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000
	48	#define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000
	49	#define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000
	50
	51
	52	/Don't change either of these/
	53	#define CFG_PERIPHERAL_BASE 0xef600000 /* internal peripherals */
	54	#define CFG_PCI_BASE 0xe0000000 /* internal PCI regs */
	55	/Don't change either of these/
	56
	57	#define CFG_USB_DEVICE 0x50000000
	58	#define CFG_NVRAM_BASE_ADDR 0x80000000
	59	#define CFG_BCSR_BASE (CFG_NVRAM_BASE_ADDR \| 0x2000)
	60
	61	/*-----------------------------------------------------------------------
	62	* Initial RAM & stack pointer (placed in SDRAM)
	63	----------------------------------------------------------------------/
	64	#define CFG_INIT_RAM_ADDR 0xf0000000 /* DCache */
65	#define CFG_INIT_RAM_END 0x2000
66	#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
67	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
68	#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
69
70	#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
71	#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc*/
72	#define CFG_KBYTES_SDRAM ( 128 * 1024) /* 128MB */
73	#define CFG_SDRAM_BANKS (2)
74	/*-----------------------------------------------------------------------
75	* Serial Port
76	----------------------------------------------------------------------/
77	#undef CONFIG_SERIAL_SOFTWARE_FIFO
78	#define CFG_EXT_SERIAL_CLOCK 11059200 /* use external 11.059MHz clk */
79	#define CONFIG_BAUDRATE 9600
80	#define CONFIG_SERIAL_MULTI 1
81	/define this if you want console on UART1/
82	#undef CONFIG_UART1_CONSOLE
83
84	#define CFG_BAUDRATE_TABLE \
85	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
86
87	/*-----------------------------------------------------------------------
88	* NVRAM/RTC
89	*
90	* NOTE: The RTC registers are located at 0x7FFF0 - 0x7FFFF
91	* The DS1558 code assumes this condition
92	*
93	----------------------------------------------------------------------/
94	#define CFG_NVRAM_SIZE (0x2000 - 0x10) /* NVRAM size(8k)- RTC regs */
95	#define CONFIG_RTC_DS1556 1 /* DS1556 RTC */
96
97	/*-----------------------------------------------------------------------
98	* FLASH related
99	----------------------------------------------------------------------/
100	#if 1 /* test-only */
101	#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
102	#define CFG_MAX_FLASH_SECT 256 /* sectors per device */
103
104	#undef CFG_FLASH_CHECKSUM
105	#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
106	#define CFG_FLASH_WRITE_TOUT 120000 /* Timeout for Flash Write (in ms) */
107	#else
108	#define CFG_FLASH_CFI /* The flash is CFI compatible */
109	#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
110	#define CFG_FLASH_CFI_AMD_RESET 1 /* AMD RESET for STM 29W320DB! */
111
112	#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
113	#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
114
115	#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
116	#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
117
118	#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
119	#endif
120
121	/*-----------------------------------------------------------------------
122	* DDR SDRAM
123	----------------------------------------------------------------------/
124	#undef CONFIG_SPD_EEPROM /* Don't use SPD EEPROM for setup */
125
126	/*-----------------------------------------------------------------------
127	* I2C
128	----------------------------------------------------------------------/
129	#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
130	#undef CONFIG_SOFT_I2C /* I2C bit-banged */
131	#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
132	#define CFG_I2C_SLAVE 0x7F
133
134
135	/*-----------------------------------------------------------------------
136	* Environment
137	----------------------------------------------------------------------/
138	#undef CFG_ENV_IS_IN_NVRAM /No NVRAM on board/
139	#undef CFG_ENV_IS_IN_FLASH /* ... not in flash */
140	#define CFG_ENV_IS_IN_EEPROM 1
141
142	/* Define to allow the user to overwrite serial and ethaddr */
143	#define CONFIG_ENV_OVERWRITE
144
145	#define CFG_I2C_MULTI_EEPROMS
146	#define CFG_ENV_SIZE 0x200 /* Size of Environment vars */
147	#define CFG_ENV_OFFSET 0x0
148	#define CFG_I2C_EEPROM_ADDR (0xa8>>1)
149	#define CFG_I2C_EEPROM_ADDR_LEN 1
150	#define CFG_EEPROM_PAGE_WRITE_ENABLE
151	#define CFG_EEPROM_PAGE_WRITE_BITS 3
152	#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
153
154	#define CONFIG_BOOTCOMMAND "bootm 0xfe000000" /* autoboot command */
155	#define CONFIG_BOOTDELAY 3 /* disable autoboot */
156
157	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
158	#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
159
160	#define CONFIG_MII 1 /* MII PHY management */
161	#define CONFIG_NET_MULTI 1 /* required for netconsole */
162	#define CONFIG_PHY1_ADDR 3
163	#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
164	#define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */
165	#define CONFIG_NETMASK 255.255.255.0
166	#define CONFIG_IPADDR 10.0.4.251
167	#define CONFIG_ETHADDR 00:10:EC:00:12:34
168	#define CONFIG_ETH1ADDR 00:10:EC:00:12:35
169
170	#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
171	#define CONFIG_SERVERIP 10.0.4.115
172
173	/* Partitions */
174	#define CONFIG_MAC_PARTITION
175	#define CONFIG_DOS_PARTITION
176	#define CONFIG_ISO_PARTITION
177
178	#ifdef CONFIG_440_EP
179	/* USB */
180	#define CONFIG_USB_OHCI
181	#define CONFIG_USB_STORAGE
182
183	/Comment this out to enable USB 1.1 device/
184	#define USB_2_0_DEVICE
185	#endif /CONFIG_440_EP/
186
187	#ifdef DEBUG
188	#define CONFIG_PANIC_HANG
189	#else
190	#define CONFIG_HW_WATCHDOG /* watchdog */
191	#endif
192
193	#ifdef CONFIG_440_EP
194	/* Need to define POST */
195	#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \| \
196	CFG_CMD_DATE \| \
197	CFG_CMD_DHCP \| \
198	CFG_CMD_DIAG \| \
199	CFG_CMD_ECHO \| \
200	CFG_CMD_EEPROM \| \
201	CFG_CMD_ELF \| \
202	/* CFG_CMD_EXT2 \|*/ \
203	/* CFG_CMD_FAT \|*/ \
204	CFG_CMD_I2C \| \
205	/* CFG_CMD_IDE \|*/ \
206	CFG_CMD_IRQ \| \
207	/* CFG_CMD_KGDB \|*/ \
208	CFG_CMD_MII \| \
209	CFG_CMD_PCI \| \
210	CFG_CMD_PING \| \
211	CFG_CMD_REGINFO \| \
212	CFG_CMD_SDRAM \| \
213	CFG_CMD_FLASH \| \
214	/* CFG_CMD_SPI \|*/ \
215	CFG_CMD_USB \| \
216	0 ) & ~CFG_CMD_IMLS)
217	#else
218	#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \| \
219	CFG_CMD_DATE \| \
220	CFG_CMD_DHCP \| \
221	CFG_CMD_DIAG \| \
222	CFG_CMD_ECHO \| \
223	CFG_CMD_EEPROM \| \
224	CFG_CMD_ELF \| \
225	/* CFG_CMD_EXT2 \|*/ \
226	/* CFG_CMD_FAT \|*/ \
227	CFG_CMD_I2C \| \
228	/* CFG_CMD_IDE \|*/ \
229	CFG_CMD_IRQ \| \
230	/* CFG_CMD_KGDB \|*/ \
231	CFG_CMD_MII \| \
232	CFG_CMD_PCI \| \
233	CFG_CMD_PING \| \
234	CFG_CMD_REGINFO \| \
235	CFG_CMD_SDRAM \| \
236	CFG_CMD_FLASH \| \
237	/* CFG_CMD_SPI \|*/ \
238	0 ) & ~CFG_CMD_IMLS)
239	#endif
240
241	/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
242	#include <cmd_confdefs.h>
243
244	/*
245	* Miscellaneous configurable options
246	*/
247	#define CFG_LONGHELP /* undef to save memory */
248	#define CFG_PROMPT "=> " /* Monitor Command Prompt */
249	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
250	#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
251	#else
252	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
253	#endif
254	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
255	#define CFG_MAXARGS 16 /* max number of command args */
256	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
257
258	#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
259	#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
260
261	#define CFG_LOAD_ADDR 0x100000 /* default load address */
262	#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
263	#define CONFIG_LYNXKDI 1 /* support kdi files */
264
265	#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
266
267	/*-----------------------------------------------------------------------
268	* PCI stuff
269	*-----------------------------------------------------------------------
270	*/
271	/* General PCI */
272	#define CONFIG_PCI /* include pci support */
273	#undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */
274	#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
275	#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */
276
277	/* Board-specific PCI */
278	#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */
279	#define CFG_PCI_TARGET_INIT
280	#define CFG_PCI_MASTER_INIT
281
282	#define CFG_PCI_SUBSYS_VENDORID 0x1014 /* IBM */
283	#define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */
284
285	/*
286	* For booting Linux, the board info and command line data
287	* have to be in the first 8 MB of memory, since this is
288	* the maximum mapped by the Linux kernel during initialization.
289	*/
290	#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
291	/*-----------------------------------------------------------------------
292	* Cache Configuration
293	*/
294	#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */
295	#define CFG_CACHELINE_SIZE 32 /* ... */
296	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
297	#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
298	#endif
299
300	/*
301	* Internal Definitions
302	*
303	* Boot Flags
304	*/
305	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
306	#define BOOTFLAG_WARM 0x02 /* Software reboot */
307
308	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
309	#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
310	#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
311	#endif
312	#endif /* __CONFIG_H */