[people/ms/u-boot.git] / include / configs / zeus.h

/*
 * (C) Copyright 2007
 * Stefan Roese, DENX Software Engineering, sr@denx.de.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/************************************************************************
 * zeus.h - configuration for Zeus board
 ***********************************************************************/
#ifndef __CONFIG_H
#define __CONFIG_H

/*-----------------------------------------------------------------------
 * High Level Configuration Options
 *----------------------------------------------------------------------*/
#define CONFIG_ZEUS		1		/* Board is Zeus	*/
#define CONFIG_405EP		1		/* Specifc 405EP support*/

#define	CONFIG_SYS_TEXT_BASE	0xFFFC0000

#define CONFIG_SYS_CLK_FREQ     33000000 /* external frequency to pll   */

#define CONFIG_BOARD_EARLY_INIT_F 1		/* Call board_early_init_f */
#define CONFIG_MISC_INIT_R	1		/* Call misc_init_r	*/

#define PLLMR0_DEFAULT		PLLMR0_333_111_55_111
#define PLLMR1_DEFAULT		PLLMR1_333_111_55_111

#define CONFIG_ENV_IS_IN_FLASH     1	/* use FLASH for environment vars	*/

#define CONFIG_OVERWRITE_ETHADDR_ONCE	1

#define CONFIG_PPC4xx_EMAC
#define CONFIG_MII		1	/* MII PHY management		*/
#define CONFIG_PHY_ADDR		0x01	/* PHY address			*/
#define CONFIG_HAS_ETH1		1
#define CONFIG_PHY1_ADDR	0x11	/* EMAC1 PHY address		*/
#define CONFIG_SYS_RX_ETH_BUFFER	16	/* Number of ethernet rx buffers & descriptors */
#define CONFIG_PHY_RESET	1
#define CONFIG_PHY_RESET_DELAY	300	/* PHY RESET recovery delay	*/

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME

/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_DIAG
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_ELF
#define CONFIG_CMD_I2C
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_MII
#define CONFIG_CMD_NFS
#define CONFIG_CMD_PING
#define CONFIG_CMD_REGINFO

/* POST support */
#define CONFIG_POST		(CONFIG_SYS_POST_MEMORY   | \
				 CONFIG_SYS_POST_CPU	   | \
				 CONFIG_SYS_POST_CACHE	   | \
				 CONFIG_SYS_POST_UART	   | \
				 CONFIG_SYS_POST_ETHER)

#define CONFIG_SYS_POST_ETHER_EXT_LOOPBACK	/* eth POST using ext loopack connector	*/

/* Define here the base-addresses of the UARTs to test in POST */
#define CONFIG_SYS_POST_UART_TABLE	{ CONFIG_SYS_NS16550_COM1 }

#define CONFIG_LOGBUFFER
#define CONFIG_SYS_POST_CACHE_ADDR	0x00800000 /* free virtual address	*/

#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */

#undef CONFIG_WATCHDOG			/* watchdog disabled		*/

/*-----------------------------------------------------------------------
 * SDRAM
 *----------------------------------------------------------------------*/
/*
 * SDRAM configuration (please see cpu/ppc/sdram.[ch])
 */
#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0 */
#define CONFIG_SDRAM_BANK1	1	/* init onboard SDRAM bank 1 */

/* SDRAM timings used in datasheet */
#define CONFIG_SYS_SDRAM_CL            3	/* CAS latency */
#define CONFIG_SYS_SDRAM_tRP           20	/* PRECHARGE command period */
#define CONFIG_SYS_SDRAM_tRC           66	/* ACTIVE-to-ACTIVE command period */
#define CONFIG_SYS_SDRAM_tRCD          20	/* ACTIVE-to-READ delay */
#define CONFIG_SYS_SDRAM_tRFC		66	/* Auto refresh period */

/*-----------------------------------------------------------------------
 * Serial Port
 *----------------------------------------------------------------------*/
#define CONFIG_CONS_INDEX	1
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#define CONFIG_SYS_NS16550_CLK		get_serial_clock()
#undef	CONFIG_SYS_EXT_SERIAL_CLOCK			/* external serial clock */
#define CONFIG_SYS_BASE_BAUD	691200
#define CONFIG_BAUDRATE		115200

#define CONFIG_SYS_BAUDRATE_TABLE  \
    {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}

/*-----------------------------------------------------------------------
 * Miscellaneous configurable options
 *----------------------------------------------------------------------*/
#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE	        1024	/* Console I/O Buffer Size	*/
#else
#define CONFIG_SYS_CBSIZE	        256	/* Console I/O Buffer Size	*/
#endif
#define CONFIG_SYS_PBSIZE              (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS	        16	/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE	        CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size	*/

#define CONFIG_SYS_MEMTEST_START	0x0400000 /* memtest works on		*/
#define CONFIG_SYS_MEMTEST_END		0x0C00000 /* 4 ... 12 MB in DRAM	*/

#define CONFIG_SYS_LOAD_ADDR		0x100000  /* default load address	*/
#define CONFIG_SYS_EXTBDINFO		1	/* To use extended board_into (bd_t) */

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/

#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
#define CONFIG_LOOPW            1       /* enable loopw command         */
#define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */

/*-----------------------------------------------------------------------
 * I2C
 *----------------------------------------------------------------------*/
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_PPC4XX
#define CONFIG_SYS_I2C_PPC4XX_CH0
#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		400000
#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0		0x7F

/* these are for the ST M24C02 2kbit serial i2c eeprom */
#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50		/* base address */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1		/* bytes of address */
/* mask of address bits that overflow into the "EEPROM chip address"    */
#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07

#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3	/* 8 byte write page size */
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */

/*
 * The layout of the I2C EEPROM, used for bootstrap setup and for board-
 * specific values, like ethaddr... that can be restored via the sw-reset
 * button
 */
#define FACTORY_RESET_I2C_EEPROM	0x50
#define FACTORY_RESET_ENV_OFFS		0x80
#define FACTORY_RESET_ENV_SIZE		0x80

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_FLASH_BASE		0xFF000000
#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
#define CONFIG_SYS_MONITOR_BASE	(-CONFIG_SYS_MONITOR_LEN)

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */

/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CONFIG_SYS_FLASH_CFI				/* The flash is CFI compatible	*/
#define CONFIG_FLASH_CFI_DRIVER			/* Use common CFI driver	*/

#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }

#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max number of sectors on one chip	*/

#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/
#define CONFIG_SYS_FLASH_PROTECTION	1	/* use hardware flash protection	*/

#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
#define CONFIG_SYS_FLASH_QUIET_TEST	1	/* don't warn upon unknown flash	*/

#ifdef CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_SECT_SIZE	0x20000	/* size of one complete sector		*/
#define CONFIG_ENV_ADDR		((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
#define	CONFIG_ENV_SIZE		0x2000	/* Total Size of Environment Sector	*/

/* Address and size of Redundant Environment Sector	*/
#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
#endif

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in data cache)
 */
/* use on chip memory (OCM) for temperary stack until sdram is tested */
#define CONFIG_SYS_TEMP_STACK_OCM	1

/* On Chip Memory location */
#define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
#define CONFIG_SYS_OCM_DATA_SIZE	0x1000
#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* inside of OCM		*/
#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM	*/

#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
/* reserve some memory for POST and BOOT limit info */
#define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_GBL_DATA_OFFSET - 16)

/* extra data in OCM */
#define CONFIG_SYS_POST_MAGIC		\
		(CONFIG_SYS_OCM_DATA_ADDR + CONFIG_SYS_GBL_DATA_OFFSET - 8)
#define CONFIG_SYS_POST_VAL		\
		(CONFIG_SYS_OCM_DATA_ADDR + CONFIG_SYS_GBL_DATA_OFFSET - 12)

/*-----------------------------------------------------------------------
 * External Bus Controller (EBC) Setup
 */

/* Memory Bank 0 (Flash 16M) initialization					*/
#define CONFIG_SYS_EBC_PB0AP		0x05815600
#define CONFIG_SYS_EBC_PB0CR		0xFF09A000  /* BAS=0xFF0,BS=16MB,BU=R/W,BW=16bit  */

/*-----------------------------------------------------------------------
 * Definitions for GPIO setup (PPC405EP specific)
 *
 * GPIO0[0]     - External Bus Controller BLAST output
 * GPIO0[1-9]   - Instruction trace outputs
 * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
 * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs
 * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
 * GPIO0[24-27] - UART0 control signal inputs/outputs
 * GPIO0[28-29] - UART1 data signal input/output
 * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
 */
#define CONFIG_SYS_GPIO0_OSRL		0x15555550	/* Chip selects */
#define CONFIG_SYS_GPIO0_OSRH		0x00000110	/* UART_DTR-pin 27 alt out */
#define CONFIG_SYS_GPIO0_ISR1L		0x10000041	/* Pin 2, 12 is input */
#define CONFIG_SYS_GPIO0_ISR1H		0x15505440	/* OUT: LEDs 22/23; IN: pin12,2, NVALID# */
#define CONFIG_SYS_GPIO0_TSRL		0x00000000
#define CONFIG_SYS_GPIO0_TSRH		0x00000000
#define CONFIG_SYS_GPIO0_TCR		0xBFF68317	/* 3-state OUT: 22/23/29; 12,2 is not 3-state */
#define CONFIG_SYS_GPIO0_ODR		0x00000000

#define CONFIG_SYS_GPIO_SW_RESET	1
#define CONFIG_SYS_GPIO_ZEUS_PE	12
#define CONFIG_SYS_GPIO_LED_RED	22
#define CONFIG_SYS_GPIO_LED_GREEN	23

/* Time in milli-seconds */
#define CONFIG_SYS_TIME_POST		5000
#define CONFIG_SYS_TIME_FACTORY_RESET	10000

#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE	230400		/* speed to run kgdb serial port */
#endif

/*
 * Pass open firmware flat tree
 */
#define CONFIG_OF_LIBFDT
#define CONFIG_OF_BOARD_SETUP

/* ENVIRONMENT VARS */

#define CONFIG_PREBOOT		"echo;echo Welcome to Bulletendpoints board v1.1;echo"
#define CONFIG_IPADDR		192.168.1.10
#define CONFIG_SERVERIP		192.168.1.100
#define CONFIG_GATEWAYIP	192.168.1.100
#if 0
#define CONFIG_BOOTDELAY	-1	/* autoboot disabled        */
#else
#define CONFIG_BOOTDELAY	3	/* autoboot after 5 seconds */
#endif

#define CONFIG_EXTRA_ENV_SETTINGS					\
	"logversion=2\0"                                                \
	"hostname=zeus\0"						\
	"netdev=eth0\0"							\
	"ethact=ppc_4xx_eth0\0"						\
	"netmask=255.255.255.0\0"					\
	"ramdisk_size=50000\0"						\
	"nfsargs=setenv bootargs root=/dev/nfs rw"			\
		" nfsroot=${serverip}:${rootpath}\0"			\
	"ramargs=setenv bootargs root=/dev/ram rw"			\
		" ramdisk_size=${ramdisk_size}\0"			\
	"addip=setenv bootargs ${bootargs} "				\
		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
		":${hostname}:${netdev}:off panic=1\0"			\
	"addtty=setenv bootargs ${bootargs} console=ttyS0,"		\
		"${baudrate}\0"						\
	"net_nfs=tftp ${kernel_mem_addr} ${file_kernel};"		\
		"run nfsargs addip addtty;bootm\0"			\
	"net_ram=tftp ${kernel_mem_addr} ${file_kernel};"		\
		"tftp ${ramdisk_mem_addr} ${file_fs};"			\
		"run ramargs addip addtty;"				\
		"bootm ${kernel_mem_addr} ${ramdisk_mem_addr}\0"	\
	"rootpath=/target_fs/zeus\0"					\
	"kernel_fl_addr=ff000000\0"					\
	"kernel_mem_addr=200000\0"					\
	"ramdisk_fl_addr=ff300000\0"					\
	"ramdisk_mem_addr=4000000\0"					\
	"uboot_fl_addr=fffc0000\0"					\
	"uboot_mem_addr=100000\0"					\
	"file_uboot=/zeus/u-boot.bin\0"					\
	"tftp_uboot=tftp 100000 ${file_uboot}\0"			\
	"update_uboot=protect off fffc0000 ffffffff;"			\
		"era fffc0000 ffffffff;cp.b 100000 fffc0000 40000;"	\
		"protect on fffc0000 ffffffff\0"			\
	"upd_uboot=run tftp_uboot;run update_uboot\0"			\
	"file_kernel=/zeus/uImage_ba\0"					\
	"tftp_kernel=tftp 100000 ${file_kernel}\0"			\
	"update_kernel=protect off ff000000 ff17ffff;"			\
		"era ff000000 ff17ffff;cp.b 100000 ff000000 180000\0"	\
	"upd_kernel=run tftp_kernel;run update_kernel\0"		\
	"file_fs=/zeus/rootfs_ba.img\0"					\
	"tftp_fs=tftp 100000 ${file_fs}\0"				\
	"update_fs=protect off ff300000 ff87ffff;era ff300000 ff87ffff;"\
		"cp.b 100000 ff300000 580000\0"				\
	"upd_fs=run tftp_fs;run update_fs\0"				\
	"bootcmd=chkreset;run ramargs addip addtty addmisc;"		\
		"bootm ${kernel_fl_addr} ${ramdisk_fl_addr}\0"		\
	""

#endif	/* __CONFIG_H */
Commit	Line	Data
779e9751 SR	1	/*
	2	* (C) Copyright 2007
	3	* Stefan Roese, DENX Software Engineering, sr@denx.de.
	4	*
3765b3e7	5	* SPDX-License-Identifier: GPL-2.0+
779e9751 SR	6	*/
	7
	8	/************************************************************************
	9	* zeus.h - configuration for Zeus board
	10	***********************************************************************/
	11	#ifndef __CONFIG_H
	12	#define __CONFIG_H
	13
	14	/*-----------------------------------------------------------------------
	15	* High Level Configuration Options
	16	----------------------------------------------------------------------/
	17	#define CONFIG_ZEUS 1 /* Board is Zeus */
779e9751 SR	18	#define CONFIG_405EP 1 /* Specifc 405EP support*/
779e9751 SR	19
2ae18241 WD	20	#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
2ae18241 WD	21
779e9751 SR	22	#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
	23
	24	#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
	25	#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
	26
	27	#define PLLMR0_DEFAULT PLLMR0_333_111_55_111
	28	#define PLLMR1_DEFAULT PLLMR1_333_111_55_111
	29
5a1aceb0	30	#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
779e9751 SR	31
	32	#define CONFIG_OVERWRITE_ETHADDR_ONCE 1
	33
96e21f86	34	#define CONFIG_PPC4xx_EMAC
779e9751 SR	35	#define CONFIG_MII 1 /* MII PHY management */
	36	#define CONFIG_PHY_ADDR 0x01 /* PHY address */
	37	#define CONFIG_HAS_ETH1 1
	38	#define CONFIG_PHY1_ADDR 0x11 /* EMAC1 PHY address */
6d0f6bcf	39	#define CONFIG_SYS_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & descriptors */
779e9751 SR	40	#define CONFIG_PHY_RESET 1
	41	#define CONFIG_PHY_RESET_DELAY 300 /* PHY RESET recovery delay */
	42
3b3bff4c SR	43	/*
	44	* BOOTP options
	45	*/
	46	#define CONFIG_BOOTP_BOOTFILESIZE
	47	#define CONFIG_BOOTP_BOOTPATH
	48	#define CONFIG_BOOTP_GATEWAY
	49	#define CONFIG_BOOTP_HOSTNAME
	50
	51	/*
	52	* Command line configuration.
	53	*/
	54	#include <config_cmd_default.h>
	55
	56	#define CONFIG_CMD_ASKENV
	57	#define CONFIG_CMD_CACHE
	58	#define CONFIG_CMD_DHCP
	59	#define CONFIG_CMD_DIAG
	60	#define CONFIG_CMD_EEPROM
	61	#define CONFIG_CMD_ELF
	62	#define CONFIG_CMD_I2C
	63	#define CONFIG_CMD_IRQ
3b3bff4c	64	#define CONFIG_CMD_MII
3b3bff4c SR	65	#define CONFIG_CMD_NFS
	66	#define CONFIG_CMD_PING
	67	#define CONFIG_CMD_REGINFO
779e9751 SR	68
779e9751 SR	69	/* POST support */
6d0f6bcf JCPV	70	#define CONFIG_POST (CONFIG_SYS_POST_MEMORY \| \
	71	CONFIG_SYS_POST_CPU \| \
	72	CONFIG_SYS_POST_CACHE \| \
	73	CONFIG_SYS_POST_UART \| \
	74	CONFIG_SYS_POST_ETHER)
779e9751	75
6d0f6bcf	76	#define CONFIG_SYS_POST_ETHER_EXT_LOOPBACK /* eth POST using ext loopack connector */
779e9751 SR	77
779e9751 SR	78	/* Define here the base-addresses of the UARTs to test in POST */
5d7c73e6	79	#define CONFIG_SYS_POST_UART_TABLE { CONFIG_SYS_NS16550_COM1 }
779e9751 SR	80
779e9751 SR	81	#define CONFIG_LOGBUFFER
6d0f6bcf	82	#define CONFIG_SYS_POST_CACHE_ADDR 0x00800000 /* free virtual address */
779e9751	83
6d0f6bcf	84	#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
779e9751	85
779e9751 SR	86	#undef CONFIG_WATCHDOG /* watchdog disabled */
	87
	88	/*-----------------------------------------------------------------------
	89	* SDRAM
	90	----------------------------------------------------------------------/
	91	/*
	92	* SDRAM configuration (please see cpu/ppc/sdram.[ch])
	93	*/
	94	#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
	95	#define CONFIG_SDRAM_BANK1 1 /* init onboard SDRAM bank 1 */
	96
	97	/* SDRAM timings used in datasheet */
6d0f6bcf JCPV	98	#define CONFIG_SYS_SDRAM_CL 3 /* CAS latency */
	99	#define CONFIG_SYS_SDRAM_tRP 20 /* PRECHARGE command period */
	100	#define CONFIG_SYS_SDRAM_tRC 66 /* ACTIVE-to-ACTIVE command period */
	101	#define CONFIG_SYS_SDRAM_tRCD 20 /* ACTIVE-to-READ delay */
	102	#define CONFIG_SYS_SDRAM_tRFC 66 /* Auto refresh period */
779e9751 SR	103
	104	/*-----------------------------------------------------------------------
	105	* Serial Port
	106	----------------------------------------------------------------------/
550650dd SR	107	#define CONFIG_CONS_INDEX 1
	108	#define CONFIG_SYS_NS16550
	109	#define CONFIG_SYS_NS16550_SERIAL
	110	#define CONFIG_SYS_NS16550_REG_SIZE 1
	111	#define CONFIG_SYS_NS16550_CLK get_serial_clock()
6d0f6bcf	112	#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */
550650dd	113	#define CONFIG_SYS_BASE_BAUD 691200
779e9751	114	#define CONFIG_BAUDRATE 115200
779e9751	115
550650dd SR	116	#define CONFIG_SYS_BAUDRATE_TABLE \
550650dd SR	117	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
779e9751 SR	118
	119	/*-----------------------------------------------------------------------
	120	* Miscellaneous configurable options
	121	----------------------------------------------------------------------/
6d0f6bcf	122	#define CONFIG_SYS_LONGHELP /* undef to save memory */
3b3bff4c	123	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	124	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
779e9751	125	#else
6d0f6bcf	126	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
779e9751	127	#endif
6d0f6bcf JCPV	128	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	129	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	130	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
779e9751	131
6d0f6bcf JCPV	132	#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
6d0f6bcf JCPV	133	#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
779e9751	134
6d0f6bcf JCPV	135	#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
6d0f6bcf JCPV	136	#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
779e9751	137
779e9751	138	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
6d0f6bcf	139	#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
779e9751 SR	140
	141	#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
	142	#define CONFIG_LOOPW 1 /* enable loopw command */
	143	#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
	144	#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
	145	#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
	146
	147	/*-----------------------------------------------------------------------
	148	* I2C
	149	----------------------------------------------------------------------/
880540de DE	150	#define CONFIG_SYS_I2C
	151	#define CONFIG_SYS_I2C_PPC4XX
	152	#define CONFIG_SYS_I2C_PPC4XX_CH0
	153	#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
	154	#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
779e9751 SR	155
779e9751 SR	156	/* these are for the ST M24C02 2kbit serial i2c eeprom */
6d0f6bcf JCPV	157	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* base address */
6d0f6bcf JCPV	158	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */
779e9751	159	/* mask of address bits that overflow into the "EEPROM chip address" */
6d0f6bcf	160	#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
779e9751	161
6d0f6bcf JCPV	162	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 /* 8 byte write page size */
6d0f6bcf JCPV	163	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
779e9751 SR	164
	165	/*
	166	* The layout of the I2C EEPROM, used for bootstrap setup and for board-
	167	* specific values, like ethaddr... that can be restored via the sw-reset
	168	* button
	169	*/
	170	#define FACTORY_RESET_I2C_EEPROM 0x50
	171	#define FACTORY_RESET_ENV_OFFS 0x80
	172	#define FACTORY_RESET_ENV_SIZE 0x80
	173
	174	/*-----------------------------------------------------------------------
	175	* Start addresses for the final memory configuration
	176	* (Set up by the startup code)
6d0f6bcf	177	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
779e9751	178	*/
6d0f6bcf JCPV	179	#define CONFIG_SYS_SDRAM_BASE 0x00000000
	180	#define CONFIG_SYS_FLASH_BASE 0xFF000000
	181	#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
	182	#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
	183	#define CONFIG_SYS_MONITOR_BASE (-CONFIG_SYS_MONITOR_LEN)
779e9751 SR	184
	185	/*
	186	* For booting Linux, the board info and command line data
	187	* have to be in the first 8 MB of memory, since this is
	188	* the maximum mapped by the Linux kernel during initialization.
	189	*/
6d0f6bcf	190	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
779e9751 SR	191
	192	/*-----------------------------------------------------------------------
	193	* FLASH organization
	194	*/
6d0f6bcf	195	#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
00b1883a	196	#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
779e9751	197
6d0f6bcf	198	#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
779e9751	199
6d0f6bcf JCPV	200	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
6d0f6bcf JCPV	201	#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
779e9751	202
6d0f6bcf JCPV	203	#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
6d0f6bcf JCPV	204	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
779e9751	205
6d0f6bcf JCPV	206	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
6d0f6bcf JCPV	207	#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware flash protection */
779e9751	208
6d0f6bcf JCPV	209	#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
6d0f6bcf JCPV	210	#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
779e9751	211
5a1aceb0	212	#ifdef CONFIG_ENV_IS_IN_FLASH
0e8d1586	213	#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
6d0f6bcf	214	#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
0e8d1586	215	#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
779e9751 SR	216
779e9751 SR	217	/* Address and size of Redundant Environment Sector */
0e8d1586 JCPV	218	#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
0e8d1586 JCPV	219	#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
779e9751 SR	220	#endif
779e9751 SR	221
779e9751 SR	222	/*-----------------------------------------------------------------------
	223	* Definitions for initial stack pointer and data area (in data cache)
	224	*/
	225	/* use on chip memory (OCM) for temperary stack until sdram is tested */
6d0f6bcf	226	#define CONFIG_SYS_TEMP_STACK_OCM 1
779e9751 SR	227
779e9751 SR	228	/* On Chip Memory location */
6d0f6bcf JCPV	229	#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
	230	#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
	231	#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of OCM */
553f0982	232	#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
779e9751	233
25ddd1fb	234	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
779e9751	235	/* reserve some memory for POST and BOOT limit info */
6d0f6bcf	236	#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 16)
779e9751 SR	237
779e9751 SR	238	/* extra data in OCM */
800eb096 MZ	239	#define CONFIG_SYS_POST_MAGIC \
	240	(CONFIG_SYS_OCM_DATA_ADDR + CONFIG_SYS_GBL_DATA_OFFSET - 8)
	241	#define CONFIG_SYS_POST_VAL \
	242	(CONFIG_SYS_OCM_DATA_ADDR + CONFIG_SYS_GBL_DATA_OFFSET - 12)
779e9751 SR	243
	244	/*-----------------------------------------------------------------------
	245	* External Bus Controller (EBC) Setup
	246	*/
	247
	248	/* Memory Bank 0 (Flash 16M) initialization */
6d0f6bcf JCPV	249	#define CONFIG_SYS_EBC_PB0AP 0x05815600
6d0f6bcf JCPV	250	#define CONFIG_SYS_EBC_PB0CR 0xFF09A000 /* BAS=0xFF0,BS=16MB,BU=R/W,BW=16bit */
779e9751 SR	251
	252	/*-----------------------------------------------------------------------
	253	* Definitions for GPIO setup (PPC405EP specific)
	254	*
	255	* GPIO0[0] - External Bus Controller BLAST output
	256	* GPIO0[1-9] - Instruction trace outputs
	257	* GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
	258	* GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs
	259	* GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
	260	* GPIO0[24-27] - UART0 control signal inputs/outputs
	261	* GPIO0[28-29] - UART1 data signal input/output
	262	* GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
	263	*/
afabb498 SR	264	#define CONFIG_SYS_GPIO0_OSRL 0x15555550 /* Chip selects */
	265	#define CONFIG_SYS_GPIO0_OSRH 0x00000110 /* UART_DTR-pin 27 alt out */
	266	#define CONFIG_SYS_GPIO0_ISR1L 0x10000041 /* Pin 2, 12 is input */
	267	#define CONFIG_SYS_GPIO0_ISR1H 0x15505440 /* OUT: LEDs 22/23; IN: pin12,2, NVALID# */
6d0f6bcf	268	#define CONFIG_SYS_GPIO0_TSRL 0x00000000
afabb498	269	#define CONFIG_SYS_GPIO0_TSRH 0x00000000
6d0f6bcf JCPV	270	#define CONFIG_SYS_GPIO0_TCR 0xBFF68317 /* 3-state OUT: 22/23/29; 12,2 is not 3-state */
	271	#define CONFIG_SYS_GPIO0_ODR 0x00000000
	272
	273	#define CONFIG_SYS_GPIO_SW_RESET 1
	274	#define CONFIG_SYS_GPIO_ZEUS_PE 12
	275	#define CONFIG_SYS_GPIO_LED_RED 22
	276	#define CONFIG_SYS_GPIO_LED_GREEN 23
779e9751 SR	277
779e9751 SR	278	/* Time in milli-seconds */
6d0f6bcf JCPV	279	#define CONFIG_SYS_TIME_POST 5000
6d0f6bcf JCPV	280	#define CONFIG_SYS_TIME_FACTORY_RESET 10000
779e9751	281
3b3bff4c	282	#if defined(CONFIG_CMD_KGDB)
779e9751	283	#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
779e9751 SR	284	#endif
779e9751 SR	285
b18410e5 SR	286	/*
	287	* Pass open firmware flat tree
	288	*/
	289	#define CONFIG_OF_LIBFDT
	290	#define CONFIG_OF_BOARD_SETUP
	291
779e9751 SR	292	/* ENVIRONMENT VARS */
	293
	294	#define CONFIG_PREBOOT "echo;echo Welcome to Bulletendpoints board v1.1;echo"
	295	#define CONFIG_IPADDR 192.168.1.10
	296	#define CONFIG_SERVERIP 192.168.1.100
	297	#define CONFIG_GATEWAYIP 192.168.1.100
779e9751 SR	298	#if 0
	299	#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
	300	#else
	301	#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */
	302	#endif
	303
	304	#define CONFIG_EXTRA_ENV_SETTINGS \
	305	"logversion=2\0" \
	306	"hostname=zeus\0" \
	307	"netdev=eth0\0" \
	308	"ethact=ppc_4xx_eth0\0" \
	309	"netmask=255.255.255.0\0" \
	310	"ramdisk_size=50000\0" \
	311	"nfsargs=setenv bootargs root=/dev/nfs rw" \
	312	" nfsroot=${serverip}:${rootpath}\0" \
	313	"ramargs=setenv bootargs root=/dev/ram rw" \
e5084af8	314	" ramdisk_size=${ramdisk_size}\0" \
779e9751 SR	315	"addip=setenv bootargs ${bootargs} " \
779e9751 SR	316	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
93e14596	317	":${hostname}:${netdev}:off panic=1\0" \
779e9751 SR	318	"addtty=setenv bootargs ${bootargs} console=ttyS0," \
	319	"${baudrate}\0" \
	320	"net_nfs=tftp ${kernel_mem_addr} ${file_kernel};" \
	321	"run nfsargs addip addtty;bootm\0" \
	322	"net_ram=tftp ${kernel_mem_addr} ${file_kernel};" \
	323	"tftp ${ramdisk_mem_addr} ${file_fs};" \
	324	"run ramargs addip addtty;" \
	325	"bootm ${kernel_mem_addr} ${ramdisk_mem_addr}\0" \
	326	"rootpath=/target_fs/zeus\0" \
	327	"kernel_fl_addr=ff000000\0" \
	328	"kernel_mem_addr=200000\0" \
	329	"ramdisk_fl_addr=ff300000\0" \
	330	"ramdisk_mem_addr=4000000\0" \
	331	"uboot_fl_addr=fffc0000\0" \
	332	"uboot_mem_addr=100000\0" \
	333	"file_uboot=/zeus/u-boot.bin\0" \
	334	"tftp_uboot=tftp 100000 ${file_uboot}\0" \
	335	"update_uboot=protect off fffc0000 ffffffff;" \
	336	"era fffc0000 ffffffff;cp.b 100000 fffc0000 40000;" \
	337	"protect on fffc0000 ffffffff\0" \
	338	"upd_uboot=run tftp_uboot;run update_uboot\0" \
	339	"file_kernel=/zeus/uImage_ba\0" \
	340	"tftp_kernel=tftp 100000 ${file_kernel}\0" \
	341	"update_kernel=protect off ff000000 ff17ffff;" \
	342	"era ff000000 ff17ffff;cp.b 100000 ff000000 180000\0" \
	343	"upd_kernel=run tftp_kernel;run update_kernel\0" \
	344	"file_fs=/zeus/rootfs_ba.img\0" \
	345	"tftp_fs=tftp 100000 ${file_fs}\0" \
	346	"update_fs=protect off ff300000 ff87ffff;era ff300000 ff87ffff;"\
93e14596	347	"cp.b 100000 ff300000 580000\0" \
779e9751 SR	348	"upd_fs=run tftp_fs;run update_fs\0" \
	349	"bootcmd=chkreset;run ramargs addip addtty addmisc;" \
	350	"bootm ${kernel_fl_addr} ${ramdisk_fl_addr}\0" \
	351	""
	352
	353	#endif /* __CONFIG_H */