[people/ms/u-boot.git] / include / configs / zipitz2.h

/*
 * Aeronix Zipit Z2 configuration file
 *
 * Copyright (C) 2009-2010 Marek Vasut <marek.vasut@gmail.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Board Configuration Options
 */
#define	CONFIG_CPU_PXA27X		1	/* Marvell PXA270 CPU */
#define	CONFIG_SYS_TEXT_BASE		0x0

#undef	CONFIG_BOARD_LATE_INIT
#undef	CONFIG_SKIP_LOWLEVEL_INIT
#define	CONFIG_PREBOOT

/*
 * Environment settings
 */
#define	CONFIG_ENV_OVERWRITE
#define CONFIG_ENV_IS_IN_FLASH		1
#define CONFIG_ENV_ADDR			0x40000
#define CONFIG_ENV_SIZE			0x10000

#define	CONFIG_SYS_MALLOC_LEN		(128*1024)
#define	CONFIG_ARCH_CPU_INIT

#define	CONFIG_BOOTCOMMAND						\
	"if mmc rescan && ext2load mmc 0 0xa0000000 boot/uboot.script ;"\
	"then "								\
		"source 0xa0000000; "					\
	"else "								\
		"bootm 0x50000; "					\
	"fi; "
#define	CONFIG_BOOTARGS							\
	"console=tty0 console=ttyS2,115200 fbcon=rotate:3"
#define	CONFIG_TIMESTAMP
#define	CONFIG_BOOTDELAY		2	/* Autoboot delay */
#define	CONFIG_CMDLINE_TAG
#define	CONFIG_SETUP_MEMORY_TAGS
#define	CONFIG_SYS_TEXT_BASE		0x0
#define	CONFIG_LZMA			/* LZMA compression support */

/*
 * Serial Console Configuration
 * STUART - the lower serial port on Colibri board
 */
#define	CONFIG_PXA_SERIAL
#define	CONFIG_STUART			1
#define CONFIG_CONS_INDEX		2
#define	CONFIG_BAUDRATE			115200

/*
 * Bootloader Components Configuration
 */
#define	CONFIG_CMD_ENV
#define	CONFIG_CMD_MMC
#define	CONFIG_CMD_SPI
#define	CONFIG_CMD_USB
#define	CONFIG_CMD_CACHE

/*
 * MMC Card Configuration
 */
#ifdef	CONFIG_CMD_MMC
#define	CONFIG_MMC
#define	CONFIG_GENERIC_MMC
#define	CONFIG_PXA_MMC_GENERIC
#define	CONFIG_SYS_MMC_BASE		0xF0000000
#define	CONFIG_CMD_FAT
#define CONFIG_CMD_EXT2
#define	CONFIG_DOS_PARTITION
#endif

/*
 * SPI and LCD
 */
#ifdef	CONFIG_CMD_SPI
#define	CONFIG_SOFT_SPI
#define	CONFIG_LCD
#define	CONFIG_LCD_ROTATION
#define	CONFIG_PXA_LCD
#define	CONFIG_LMS283GF05

#define	SPI_DELAY	udelay(10)
#define	SPI_SDA(val)	zipitz2_spi_sda(val)
#define	SPI_SCL(val)	zipitz2_spi_scl(val)
#define	SPI_READ	zipitz2_spi_read()
#ifndef	__ASSEMBLY__
void zipitz2_spi_sda(int);
void zipitz2_spi_scl(int);
unsigned char zipitz2_spi_read(void);
#endif
#endif

#define	CONFIG_SYS_LONGHELP				/* undef to save memory	*/
#define	CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size */
#define	CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
#define	CONFIG_SYS_MAXARGS		16		/* max number of command args */
#define	CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
#define	CONFIG_SYS_DEVICE_NULLDEV	1

/*
 * Clock Configuration
 */
#define CONFIG_SYS_CPUSPEED		0x190		/* standard setting for 312MHz; L=16, N=1.5, A=0, SDCLK!=SystemBus */

/*
 * SRAM Map
 */
#define	PHYS_SRAM			0x5c000000	/* SRAM Bank #1 */
#define	PHYS_SRAM_SIZE			0x00040000	/* 256k */

/*
 * DRAM Map
 */
#define	CONFIG_NR_DRAM_BANKS		1		/* We have 1 bank of DRAM */
#define	PHYS_SDRAM_1			0xa0000000	/* SDRAM Bank #1 */
#define	PHYS_SDRAM_1_SIZE		0x02000000	/* 32 MB */

#define	CONFIG_SYS_DRAM_BASE		0xa0000000	/* CS0 */
#define	CONFIG_SYS_DRAM_SIZE		0x02000000	/* 32 MB DRAM */

#define CONFIG_SYS_MEMTEST_START	0xa0400000	/* memtest works on */
#define CONFIG_SYS_MEMTEST_END		0xa0800000	/* 4 ... 8 MB in DRAM */

#define	CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_DRAM_BASE

#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
#define	CONFIG_SYS_INIT_SP_ADDR		(GENERATED_GBL_DATA_SIZE + PHYS_SRAM + 2048)

/*
 * NOR FLASH
 */
#define PHYS_FLASH_1			0x00000000	/* Flash Bank #1 */
#define PHYS_FLASH_SIZE			0x00800000	/* 8 MB */
#define PHYS_FLASH_SECT_SIZE		0x00010000	/* 64 KB sectors */
#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1

#define CONFIG_SYS_FLASH_CFI
#define CONFIG_FLASH_CFI_DRIVER		1
#define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT

#define CONFIG_SYS_MONITOR_BASE		PHYS_FLASH_1
#define CONFIG_SYS_MONITOR_LEN		PHYS_FLASH_SECT_SIZE

#define CONFIG_SYS_MAX_FLASH_BANKS	1
#define CONFIG_SYS_MAX_FLASH_SECT	256

#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1

#define CONFIG_SYS_FLASH_ERASE_TOUT	240000
#define CONFIG_SYS_FLASH_WRITE_TOUT	240000
#define CONFIG_SYS_FLASH_LOCK_TOUT	240000
#define CONFIG_SYS_FLASH_UNLOCK_TOUT	240000
#define CONFIG_SYS_FLASH_PROTECTION

/*
 * GPIO settings
 */
#define CONFIG_SYS_GAFR0_L_VAL	0x02000140
#define CONFIG_SYS_GAFR0_U_VAL	0x59188000
#define CONFIG_SYS_GAFR1_L_VAL	0x63900002
#define CONFIG_SYS_GAFR1_U_VAL	0xaaa03950
#define CONFIG_SYS_GAFR2_L_VAL	0x0aaaaaaa
#define CONFIG_SYS_GAFR2_U_VAL	0x29000308
#define CONFIG_SYS_GAFR3_L_VAL	0x54000000
#define CONFIG_SYS_GAFR3_U_VAL	0x000000d5
#define CONFIG_SYS_GPCR0_VAL	0x00000000
#define CONFIG_SYS_GPCR1_VAL	0x00000020
#define CONFIG_SYS_GPCR2_VAL	0x00000000
#define CONFIG_SYS_GPCR3_VAL	0x00000000
#define CONFIG_SYS_GPDR0_VAL	0xdafcee00
#define CONFIG_SYS_GPDR1_VAL	0xffa3aaab
#define CONFIG_SYS_GPDR2_VAL	0x8fe9ffff
#define CONFIG_SYS_GPDR3_VAL	0x001b1f8a
#define CONFIG_SYS_GPSR0_VAL	0x06080400
#define CONFIG_SYS_GPSR1_VAL	0x007f0000
#define CONFIG_SYS_GPSR2_VAL	0x032a0000
#define CONFIG_SYS_GPSR3_VAL	0x00000180

#define CONFIG_SYS_PSSR_VAL	0x30

/*
 * Clock settings
 */
#define CONFIG_SYS_CKEN		0x00511220
#define CONFIG_SYS_CCCR		0x00000190

/*
 * Memory settings
 */
#define CONFIG_SYS_MSC0_VAL	0x2ffc38f8
#define CONFIG_SYS_MSC1_VAL	0x0000ccd1
#define CONFIG_SYS_MSC2_VAL	0x0000b884
#define CONFIG_SYS_MDCNFG_VAL	0x08000ba9
#define CONFIG_SYS_MDREFR_VAL	0x2011a01e
#define CONFIG_SYS_MDMRS_VAL	0x00000000
#define CONFIG_SYS_FLYCNFG_VAL	0x00010001
#define CONFIG_SYS_SXCNFG_VAL	0x40044004

/*
 * PCMCIA and CF Interfaces
 */
#define CONFIG_SYS_MECR_VAL	0x00000001
#define CONFIG_SYS_MCMEM0_VAL	0x00014307
#define CONFIG_SYS_MCMEM1_VAL	0x00014307
#define CONFIG_SYS_MCATT0_VAL	0x0001c787
#define CONFIG_SYS_MCATT1_VAL	0x0001c787
#define CONFIG_SYS_MCIO0_VAL	0x0001430f
#define CONFIG_SYS_MCIO1_VAL	0x0001430f

#include "pxa-common.h"

#endif	/* __CONFIG_H */
Commit	Line	Data
f19eb154 VK	1	/*
	2	* Aeronix Zipit Z2 configuration file
	3	*
	4	* Copyright (C) 2009-2010 Marek Vasut <marek.vasut@gmail.com>
	5	*
	6	* SPDX-License-Identifier: GPL-2.0+
	7	*/
	8
	9	#ifndef __CONFIG_H
	10	#define __CONFIG_H
	11
	12	/*
	13	* High Level Board Configuration Options
	14	*/
	15	#define CONFIG_CPU_PXA27X 1 /* Marvell PXA270 CPU */
	16	#define CONFIG_SYS_TEXT_BASE 0x0
	17
	18	#undef CONFIG_BOARD_LATE_INIT
	19	#undef CONFIG_SKIP_LOWLEVEL_INIT
	20	#define CONFIG_PREBOOT
	21
	22	/*
	23	* Environment settings
	24	*/
	25	#define CONFIG_ENV_OVERWRITE
	26	#define CONFIG_ENV_IS_IN_FLASH 1
	27	#define CONFIG_ENV_ADDR 0x40000
	28	#define CONFIG_ENV_SIZE 0x10000
	29
f19eb154 VK	30	#define CONFIG_SYS_MALLOC_LEN (128*1024)
	31	#define CONFIG_ARCH_CPU_INIT
	32
	33	#define CONFIG_BOOTCOMMAND \
	34	"if mmc rescan && ext2load mmc 0 0xa0000000 boot/uboot.script ;"\
	35	"then " \
	36	"source 0xa0000000; " \
	37	"else " \
	38	"bootm 0x50000; " \
	39	"fi; "
	40	#define CONFIG_BOOTARGS \
	41	"console=tty0 console=ttyS2,115200 fbcon=rotate:3"
	42	#define CONFIG_TIMESTAMP
	43	#define CONFIG_BOOTDELAY 2 /* Autoboot delay */
	44	#define CONFIG_CMDLINE_TAG
	45	#define CONFIG_SETUP_MEMORY_TAGS
	46	#define CONFIG_SYS_TEXT_BASE 0x0
	47	#define CONFIG_LZMA /* LZMA compression support */
	48
	49	/*
	50	* Serial Console Configuration
	51	* STUART - the lower serial port on Colibri board
	52	*/
	53	#define CONFIG_PXA_SERIAL
	54	#define CONFIG_STUART 1
	55	#define CONFIG_CONS_INDEX 2
	56	#define CONFIG_BAUDRATE 115200
	57
	58	/*
	59	* Bootloader Components Configuration
	60	*/
	61	#define CONFIG_CMD_ENV
	62	#define CONFIG_CMD_MMC
	63	#define CONFIG_CMD_SPI
afed7ebe	64	#define CONFIG_CMD_USB
f9e8a98f	65	#define CONFIG_CMD_CACHE
f19eb154 VK	66
	67	/*
	68	* MMC Card Configuration
	69	*/
	70	#ifdef CONFIG_CMD_MMC
	71	#define CONFIG_MMC
	72	#define CONFIG_GENERIC_MMC
	73	#define CONFIG_PXA_MMC_GENERIC
	74	#define CONFIG_SYS_MMC_BASE 0xF0000000
	75	#define CONFIG_CMD_FAT
	76	#define CONFIG_CMD_EXT2
	77	#define CONFIG_DOS_PARTITION
	78	#endif
	79
	80	/*
	81	* SPI and LCD
	82	*/
	83	#ifdef CONFIG_CMD_SPI
	84	#define CONFIG_SOFT_SPI
	85	#define CONFIG_LCD
59fa089b	86	#define CONFIG_LCD_ROTATION
f19eb154 VK	87	#define CONFIG_PXA_LCD
	88	#define CONFIG_LMS283GF05
	89
	90	#define SPI_DELAY udelay(10)
	91	#define SPI_SDA(val) zipitz2_spi_sda(val)
	92	#define SPI_SCL(val) zipitz2_spi_scl(val)
	93	#define SPI_READ zipitz2_spi_read()
	94	#ifndef __ASSEMBLY__
	95	void zipitz2_spi_sda(int);
	96	void zipitz2_spi_scl(int);
	97	unsigned char zipitz2_spi_read(void);
	98	#endif
	99	#endif
	100
f19eb154 VK	101	#define CONFIG_SYS_LONGHELP /* undef to save memory */
	102	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
	103	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	104	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	105	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
	106	#define CONFIG_SYS_DEVICE_NULLDEV 1
	107
	108	/*
	109	* Clock Configuration
	110	*/
	111	#define CONFIG_SYS_CPUSPEED 0x190 /* standard setting for 312MHz; L=16, N=1.5, A=0, SDCLK!=SystemBus */
	112
	113	/*
	114	* SRAM Map
	115	*/
	116	#define PHYS_SRAM 0x5c000000 /* SRAM Bank #1 */
	117	#define PHYS_SRAM_SIZE 0x00040000 /* 256k */
	118
	119	/*
	120	* DRAM Map
	121	*/
	122	#define CONFIG_NR_DRAM_BANKS 1 /* We have 1 bank of DRAM */
	123	#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
	124	#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */
	125
	126	#define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */
	127	#define CONFIG_SYS_DRAM_SIZE 0x02000000 /* 32 MB DRAM */
	128
	129	#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */
	130	#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
	131
	132	#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_DRAM_BASE
	133
	134	#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
	135	#define CONFIG_SYS_INIT_SP_ADDR (GENERATED_GBL_DATA_SIZE + PHYS_SRAM + 2048)
	136
	137	/*
	138	* NOR FLASH
	139	*/
	140	#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
	141	#define PHYS_FLASH_SIZE 0x00800000 /* 8 MB */
	142	#define PHYS_FLASH_SECT_SIZE 0x00010000 /* 64 KB sectors */
	143	#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
	144
	145	#define CONFIG_SYS_FLASH_CFI
	146	#define CONFIG_FLASH_CFI_DRIVER 1
	147	#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
	148
	149	#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
	150	#define CONFIG_SYS_MONITOR_LEN PHYS_FLASH_SECT_SIZE
	151
	152	#define CONFIG_SYS_MAX_FLASH_BANKS 1
	153	#define CONFIG_SYS_MAX_FLASH_SECT 256
	154
	155	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
	156
	157	#define CONFIG_SYS_FLASH_ERASE_TOUT 240000
	158	#define CONFIG_SYS_FLASH_WRITE_TOUT 240000
	159	#define CONFIG_SYS_FLASH_LOCK_TOUT 240000
	160	#define CONFIG_SYS_FLASH_UNLOCK_TOUT 240000
	161	#define CONFIG_SYS_FLASH_PROTECTION
	162
	163	/*
	164	* GPIO settings
165	*/
166	#define CONFIG_SYS_GAFR0_L_VAL 0x02000140
167	#define CONFIG_SYS_GAFR0_U_VAL 0x59188000
168	#define CONFIG_SYS_GAFR1_L_VAL 0x63900002
169	#define CONFIG_SYS_GAFR1_U_VAL 0xaaa03950
170	#define CONFIG_SYS_GAFR2_L_VAL 0x0aaaaaaa
171	#define CONFIG_SYS_GAFR2_U_VAL 0x29000308
172	#define CONFIG_SYS_GAFR3_L_VAL 0x54000000
173	#define CONFIG_SYS_GAFR3_U_VAL 0x000000d5
174	#define CONFIG_SYS_GPCR0_VAL 0x00000000
175	#define CONFIG_SYS_GPCR1_VAL 0x00000020
176	#define CONFIG_SYS_GPCR2_VAL 0x00000000
177	#define CONFIG_SYS_GPCR3_VAL 0x00000000
178	#define CONFIG_SYS_GPDR0_VAL 0xdafcee00
179	#define CONFIG_SYS_GPDR1_VAL 0xffa3aaab
180	#define CONFIG_SYS_GPDR2_VAL 0x8fe9ffff
181	#define CONFIG_SYS_GPDR3_VAL 0x001b1f8a
182	#define CONFIG_SYS_GPSR0_VAL 0x06080400
183	#define CONFIG_SYS_GPSR1_VAL 0x007f0000
184	#define CONFIG_SYS_GPSR2_VAL 0x032a0000
185	#define CONFIG_SYS_GPSR3_VAL 0x00000180
186
187	#define CONFIG_SYS_PSSR_VAL 0x30
188
189	/*
190	* Clock settings
191	*/
192	#define CONFIG_SYS_CKEN 0x00511220
193	#define CONFIG_SYS_CCCR 0x00000190
194
195	/*
196	* Memory settings
197	*/
198	#define CONFIG_SYS_MSC0_VAL 0x2ffc38f8
199	#define CONFIG_SYS_MSC1_VAL 0x0000ccd1
200	#define CONFIG_SYS_MSC2_VAL 0x0000b884
201	#define CONFIG_SYS_MDCNFG_VAL 0x08000ba9
202	#define CONFIG_SYS_MDREFR_VAL 0x2011a01e
203	#define CONFIG_SYS_MDMRS_VAL 0x00000000
204	#define CONFIG_SYS_FLYCNFG_VAL 0x00010001
205	#define CONFIG_SYS_SXCNFG_VAL 0x40044004
206
207	/*
208	* PCMCIA and CF Interfaces
209	*/
210	#define CONFIG_SYS_MECR_VAL 0x00000001
211	#define CONFIG_SYS_MCMEM0_VAL 0x00014307
212	#define CONFIG_SYS_MCMEM1_VAL 0x00014307
213	#define CONFIG_SYS_MCATT0_VAL 0x0001c787
214	#define CONFIG_SYS_MCATT1_VAL 0x0001c787
215	#define CONFIG_SYS_MCIO0_VAL 0x0001430f
216	#define CONFIG_SYS_MCIO1_VAL 0x0001430f
217
218	#include "pxa-common.h"
219
220	#endif /* __CONFIG_H */