projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 0f2cbe3f JY |
1 | /* |
| 2 | * Copyright 2008 Freescale Semiconductor, Inc. | |
| 3 | * | |
| 4 | * This program is free software; you can redistribute it and/or | |
| 5 | * modify it under the terms of the GNU General Public License | |
| 6 | * Version 2 as published by the Free Software Foundation. | |
| 7 | */ | |
| 8 | ||
| 9 | #ifndef _DDR_SPD_H_ | |
| 10 | #define _DDR_SPD_H_ | |
| 11 | ||
| 12 | /* | |
| 13 | * Format from "JEDEC Standard No. 21-C, | |
| 14 | * Appendix D: Rev 1.0: SPD's for DDR SDRAM | |
| 15 | */ | |
| 16 | typedef struct ddr1_spd_eeprom_s { | |
| 17 | unsigned char info_size; /* 0 # bytes written into serial memory */ | |
| 18 | unsigned char chip_size; /* 1 Total # bytes of SPD memory device */ | |
| 19 | unsigned char mem_type; /* 2 Fundamental memory type */ | |
| 20 | unsigned char nrow_addr; /* 3 # of Row Addresses on this assembly */ | |
| 21 | unsigned char ncol_addr; /* 4 # of Column Addrs on this assembly */ | |
| 22 | unsigned char nrows; /* 5 Number of DIMM Banks */ | |
| 23 | unsigned char dataw_lsb; /* 6 Data Width of this assembly */ | |
| 24 | unsigned char dataw_msb; /* 7 ... Data Width continuation */ | |
| 25 | unsigned char voltage; /* 8 Voltage intf std of this assembly */ | |
| 26 | unsigned char clk_cycle; /* 9 SDRAM Cycle time @ CL=X */ | |
| 27 | unsigned char clk_access; /* 10 SDRAM Access from Clk @ CL=X (tAC) */ | |
| 28 | unsigned char config; /* 11 DIMM Configuration type */ | |
| 29 | unsigned char refresh; /* 12 Refresh Rate/Type */ | |
| 30 | unsigned char primw; /* 13 Primary SDRAM Width */ | |
| 31 | unsigned char ecw; /* 14 Error Checking SDRAM width */ | |
| 32 | unsigned char min_delay; /* 15 for Back to Back Random Address */ | |
| 33 | unsigned char burstl; /* 16 Burst Lengths Supported */ | |
| 34 | unsigned char nbanks; /* 17 # of Banks on SDRAM Device */ | |
| 35 | unsigned char cas_lat; /* 18 CAS# Latencies Supported */ | |
| 36 | unsigned char cs_lat; /* 19 CS# Latency */ | |
| 37 | unsigned char write_lat; /* 20 Write Latency (aka Write Recovery) */ | |
| 38 | unsigned char mod_attr; /* 21 SDRAM Module Attributes */ | |
| 39 | unsigned char dev_attr; /* 22 SDRAM Device Attributes */ | |
| 40 | unsigned char clk_cycle2; /* 23 Min SDRAM Cycle time @ CL=X-0.5 */ | |
| 41 | unsigned char clk_access2; /* 24 SDRAM Access from | |
| 42 | Clk @ CL=X-0.5 (tAC) */ | |
| 43 | unsigned char clk_cycle3; /* 25 Min SDRAM Cycle time @ CL=X-1 */ | |
| 44 | unsigned char clk_access3; /* 26 Max Access from Clk @ CL=X-1 (tAC) */ | |
| 45 | unsigned char trp; /* 27 Min Row Precharge Time (tRP)*/ | |
| 46 | unsigned char trrd; /* 28 Min Row Active to Row Active (tRRD) */ | |
| 47 | unsigned char trcd; /* 29 Min RAS to CAS Delay (tRCD) */ | |
| 48 | unsigned char tras; /* 30 Minimum RAS Pulse Width (tRAS) */ | |
| 49 | unsigned char bank_dens; /* 31 Density of each bank on module */ | |
| 50 | unsigned char ca_setup; /* 32 Addr + Cmd Setup Time Before Clk */ | |
| 51 | unsigned char ca_hold; /* 33 Addr + Cmd Hold Time After Clk */ | |
| 52 | unsigned char data_setup; /* 34 Data Input Setup Time Before Strobe */ | |
| 53 | unsigned char data_hold; /* 35 Data Input Hold Time After Strobe */ | |
| 54 | unsigned char res_36_40[5];/* 36-40 reserved for VCSDRAM */ | |
| 55 | unsigned char trc; /* 41 Min Active to Auto refresh time tRC */ | |
| 56 | unsigned char trfc; /* 42 Min Auto to Active period tRFC */ | |
| 57 | unsigned char tckmax; /* 43 Max device cycle time tCKmax */ | |
| 58 | unsigned char tdqsq; /* 44 Max DQS to DQ skew (tDQSQ max) */ | |
| 59 | unsigned char tqhs; /* 45 Max Read DataHold skew (tQHS) */ | |
| 60 | unsigned char res_46; /* 46 Reserved */ | |
| 61 | unsigned char dimm_height; /* 47 DDR SDRAM DIMM Height */ | |
| 62 | unsigned char res_48_61[14]; /* 48-61 Reserved */ | |
| 63 | unsigned char spd_rev; /* 62 SPD Data Revision Code */ | |
| 64 | unsigned char cksum; /* 63 Checksum for bytes 0-62 */ | |
| 65 | unsigned char mid[8]; /* 64-71 Mfr's JEDEC ID code per JEP-106 */ | |
| 66 | unsigned char mloc; /* 72 Manufacturing Location */ | |
| 67 | unsigned char mpart[18]; /* 73 Manufacturer's Part Number */ | |
| 68 | unsigned char rev[2]; /* 91 Revision Code */ | |
| 69 | unsigned char mdate[2]; /* 93 Manufacturing Date */ | |
| 70 | unsigned char sernum[4]; /* 95 Assembly Serial Number */ | |
| 71 | unsigned char mspec[27]; /* 99-127 Manufacturer Specific Data */ | |
| 72 | ||
| 73 | } ddr1_spd_eeprom_t; | |
| 74 | ||
| 75 | /* | |
| 76 | * Format from "JEDEC Appendix X: Serial Presence Detects for DDR2 SDRAM", | |
| 77 | * SPD Revision 1.2 | |
| 78 | */ | |
| 79 | typedef struct ddr2_spd_eeprom_s { | |
| 80 | unsigned char info_size; /* 0 # bytes written into serial memory */ | |
| 81 | unsigned char chip_size; /* 1 Total # bytes of SPD memory device */ | |
| 82 | unsigned char mem_type; /* 2 Fundamental memory type */ | |
| 83 | unsigned char nrow_addr; /* 3 # of Row Addresses on this assembly */ | |
| 84 | unsigned char ncol_addr; /* 4 # of Column Addrs on this assembly */ | |
| 85 | unsigned char mod_ranks; /* 5 Number of DIMM Ranks */ | |
| 86 | unsigned char dataw; /* 6 Module Data Width */ | |
| 87 | unsigned char res_7; /* 7 Reserved */ | |
| 88 | unsigned char voltage; /* 8 Voltage intf std of this assembly */ | |
| 89 | unsigned char clk_cycle; /* 9 SDRAM Cycle time @ CL=X */ | |
| 90 | unsigned char clk_access; /* 10 SDRAM Access from Clk @ CL=X (tAC) */ | |
| 91 | unsigned char config; /* 11 DIMM Configuration type */ | |
| 92 | unsigned char refresh; /* 12 Refresh Rate/Type */ | |
| 93 | unsigned char primw; /* 13 Primary SDRAM Width */ | |
| 94 | unsigned char ecw; /* 14 Error Checking SDRAM width */ | |
| 95 | unsigned char res_15; /* 15 Reserved */ | |
| 96 | unsigned char burstl; /* 16 Burst Lengths Supported */ | |
| 97 | unsigned char nbanks; /* 17 # of Banks on Each SDRAM Device */ | |
| 98 | unsigned char cas_lat; /* 18 CAS# Latencies Supported */ | |
| 99 | unsigned char mech_char; /* 19 DIMM Mechanical Characteristics */ | |
| 100 | unsigned char dimm_type; /* 20 DIMM type information */ | |
| 101 | unsigned char mod_attr; /* 21 SDRAM Module Attributes */ | |
| 102 | unsigned char dev_attr; /* 22 SDRAM Device Attributes */ | |
| 103 | unsigned char clk_cycle2; /* 23 Min SDRAM Cycle time @ CL=X-1 */ | |
| 104 | unsigned char clk_access2; /* 24 SDRAM Access from Clk @ CL=X-1 (tAC) */ | |
| 105 | unsigned char clk_cycle3; /* 25 Min SDRAM Cycle time @ CL=X-2 */ | |
| 106 | unsigned char clk_access3; /* 26 Max Access from Clk @ CL=X-2 (tAC) */ | |
| 107 | unsigned char trp; /* 27 Min Row Precharge Time (tRP)*/ | |
| 108 | unsigned char trrd; /* 28 Min Row Active to Row Active (tRRD) */ | |
| 109 | unsigned char trcd; /* 29 Min RAS to CAS Delay (tRCD) */ | |
| 110 | unsigned char tras; /* 30 Minimum RAS Pulse Width (tRAS) */ | |
| 111 | unsigned char rank_dens; /* 31 Density of each rank on module */ | |
| 112 | unsigned char ca_setup; /* 32 Addr+Cmd Setup Time Before Clk (tIS) */ | |
| 113 | unsigned char ca_hold; /* 33 Addr+Cmd Hold Time After Clk (tIH) */ | |
| 114 | unsigned char data_setup; /* 34 Data Input Setup Time | |
| 115 | Before Strobe (tDS) */ | |
| 116 | unsigned char data_hold; /* 35 Data Input Hold Time | |
| 117 | After Strobe (tDH) */ | |
| 118 | unsigned char twr; /* 36 Write Recovery time tWR */ | |
| 119 | unsigned char twtr; /* 37 Int write to read delay tWTR */ | |
| 120 | unsigned char trtp; /* 38 Int read to precharge delay tRTP */ | |
| 121 | unsigned char mem_probe; /* 39 Mem analysis probe characteristics */ | |
| 122 | unsigned char trctrfc_ext; /* 40 Extensions to trc and trfc */ | |
| 123 | unsigned char trc; /* 41 Min Active to Auto refresh time tRC */ | |
| 124 | unsigned char trfc; /* 42 Min Auto to Active period tRFC */ | |
| 125 | unsigned char tckmax; /* 43 Max device cycle time tCKmax */ | |
| 126 | unsigned char tdqsq; /* 44 Max DQS to DQ skew (tDQSQ max) */ | |
| 127 | unsigned char tqhs; /* 45 Max Read DataHold skew (tQHS) */ | |
| 128 | unsigned char pll_relock; /* 46 PLL Relock time */ | |
| 129 | unsigned char Tcasemax; /* 47 Tcasemax */ | |
| 130 | unsigned char psiTAdram; /* 48 Thermal Resistance of DRAM Package from | |
| 131 | Top (Case) to Ambient (Psi T-A DRAM) */ | |
| 132 | unsigned char dt0_mode; /* 49 DRAM Case Temperature Rise from Ambient | |
| 133 | due to Activate-Precharge/Mode Bits | |
| 134 | (DT0/Mode Bits) */ | |
| 135 | unsigned char dt2n_dt2q; /* 50 DRAM Case Temperature Rise from Ambient | |
| 136 | due to Precharge/Quiet Standby | |
| 137 | (DT2N/DT2Q) */ | |
| 138 | unsigned char dt2p; /* 51 DRAM Case Temperature Rise from Ambient | |
| 139 | due to Precharge Power-Down (DT2P) */ | |
| 140 | unsigned char dt3n; /* 52 DRAM Case Temperature Rise from Ambient | |
| 141 | due to Active Standby (DT3N) */ | |
| 142 | unsigned char dt3pfast; /* 53 DRAM Case Temperature Rise from Ambient | |
| 143 | due to Active Power-Down with | |
| 144 | Fast PDN Exit (DT3Pfast) */ | |
| 145 | unsigned char dt3pslow; /* 54 DRAM Case Temperature Rise from Ambient | |
| 146 | due to Active Power-Down with Slow | |
| 147 | PDN Exit (DT3Pslow) */ | |
| 148 | unsigned char dt4r_dt4r4w; /* 55 DRAM Case Temperature Rise from Ambient | |
| 149 | due to Page Open Burst Read/DT4R4W | |
| 150 | Mode Bit (DT4R/DT4R4W Mode Bit) */ | |
| 151 | unsigned char dt5b; /* 56 DRAM Case Temperature Rise from Ambient | |
| 152 | due to Burst Refresh (DT5B) */ | |
| 153 | unsigned char dt7; /* 57 DRAM Case Temperature Rise from Ambient | |
| 154 | due to Bank Interleave Reads with | |
| 155 | Auto-Precharge (DT7) */ | |
| 156 | unsigned char psiTApll; /* 58 Thermal Resistance of PLL Package form | |
| 157 | Top (Case) to Ambient (Psi T-A PLL) */ | |
| 158 | unsigned char psiTAreg; /* 59 Thermal Reisitance of Register Package | |
| 159 | from Top (Case) to Ambient | |
| 160 | (Psi T-A Register) */ | |
| 161 | unsigned char dtpllactive; /* 60 PLL Case Temperature Rise from Ambient | |
| 162 | due to PLL Active (DT PLL Active) */ | |
| 163 | unsigned char dtregact; /* 61 Register Case Temperature Rise from | |
| 164 | Ambient due to Register Active/Mode Bit | |
| 165 | (DT Register Active/Mode Bit) */ | |
| 166 | unsigned char spd_rev; /* 62 SPD Data Revision Code */ | |
| 167 | unsigned char cksum; /* 63 Checksum for bytes 0-62 */ | |
| 168 | unsigned char mid[8]; /* 64 Mfr's JEDEC ID code per JEP-106 */ | |
| 169 | unsigned char mloc; /* 72 Manufacturing Location */ | |
| 170 | unsigned char mpart[18]; /* 73 Manufacturer's Part Number */ | |
| 171 | unsigned char rev[2]; /* 91 Revision Code */ | |
| 172 | unsigned char mdate[2]; /* 93 Manufacturing Date */ | |
| 173 | unsigned char sernum[4]; /* 95 Assembly Serial Number */ | |
| 174 | unsigned char mspec[27]; /* 99-127 Manufacturer Specific Data */ | |
| 175 | ||
| 176 | } ddr2_spd_eeprom_t; | |
| 177 | ||
| 178 | typedef struct ddr3_spd_eeprom_s { | |
| 179 | /* General Section: Bytes 0-59 */ | |
| 180 | unsigned char info_size_crc; /* 0 # bytes written into serial memory, | |
| 181 | CRC coverage */ | |
| 182 | unsigned char spd_rev; /* 1 Total # bytes of SPD mem device */ | |
| 183 | unsigned char mem_type; /* 2 Key Byte / Fundamental mem type */ | |
| 184 | unsigned char module_type; /* 3 Key Byte / Module Type */ | |
| 185 | unsigned char density_banks; /* 4 SDRAM Density and Banks */ | |
| 186 | unsigned char addressing; /* 5 SDRAM Addressing */ | |
| c360ceac | 187 | unsigned char module_vdd; /* 6 Module nominal voltage, VDD */ |
| 0f2cbe3f JY |
188 | unsigned char organization; /* 7 Module Organization */ |
| 189 | unsigned char bus_width; /* 8 Module Memory Bus Width */ | |
| 190 | unsigned char ftb_div; /* 9 Fine Timebase (FTB) | |
| 191 | Dividend / Divisor */ | |
| 192 | unsigned char mtb_dividend; /* 10 Medium Timebase (MTB) Dividend */ | |
| 193 | unsigned char mtb_divisor; /* 11 Medium Timebase (MTB) Divisor */ | |
| 194 | unsigned char tCK_min; /* 12 SDRAM Minimum Cycle Time */ | |
| 195 | unsigned char res_13; /* 13 Reserved */ | |
| 196 | unsigned char caslat_lsb; /* 14 CAS Latencies Supported, | |
| 197 | Least Significant Byte */ | |
| 198 | unsigned char caslat_msb; /* 15 CAS Latencies Supported, | |
| 199 | Most Significant Byte */ | |
| 200 | unsigned char tAA_min; /* 16 Min CAS Latency Time */ | |
| 201 | unsigned char tWR_min; /* 17 Min Write REcovery Time */ | |
| 202 | unsigned char tRCD_min; /* 18 Min RAS# to CAS# Delay Time */ | |
| 203 | unsigned char tRRD_min; /* 19 Min Row Active to | |
| 204 | Row Active Delay Time */ | |
| 205 | unsigned char tRP_min; /* 20 Min Row Precharge Delay Time */ | |
| 206 | unsigned char tRAS_tRC_ext; /* 21 Upper Nibbles for tRAS and tRC */ | |
| 207 | unsigned char tRAS_min_lsb; /* 22 Min Active to Precharge | |
| 208 | Delay Time */ | |
| 209 | unsigned char tRC_min_lsb; /* 23 Min Active to Active/Refresh | |
| 210 | Delay Time, LSB */ | |
| 211 | unsigned char tRFC_min_lsb; /* 24 Min Refresh Recovery Delay Time */ | |
| 212 | unsigned char tRFC_min_msb; /* 25 Min Refresh Recovery Delay Time */ | |
| 213 | unsigned char tWTR_min; /* 26 Min Internal Write to | |
| 214 | Read Command Delay Time */ | |
| 215 | unsigned char tRTP_min; /* 27 Min Internal Read to Precharge | |
| 216 | Command Delay Time */ | |
| 217 | unsigned char tFAW_msb; /* 28 Upper Nibble for tFAW */ | |
| 218 | unsigned char tFAW_min; /* 29 Min Four Activate Window | |
| 219 | Delay Time*/ | |
| 220 | unsigned char opt_features; /* 30 SDRAM Optional Features */ | |
| 221 | unsigned char therm_ref_opt; /* 31 SDRAM Thermal and Refresh Opts */ | |
| 222 | unsigned char res_32_59[28]; /* 32-59 Reserved, General Section */ | |
| 223 | ||
| 224 | /* Module-Specific Section: Bytes 60-116 */ | |
| 225 | union { | |
| 226 | struct { | |
| 227 | /* 60 (Unbuffered) Module Nominal Height */ | |
| 228 | unsigned char mod_height; | |
| 229 | /* 61 (Unbuffered) Module Maximum Thickness */ | |
| 230 | unsigned char mod_thickness; | |
| 231 | /* 62 (Unbuffered) Reference Raw Card Used */ | |
| 232 | unsigned char ref_raw_card; | |
| 233 | /* 63 (Unbuffered) Address Mapping from | |
| 234 | Edge Connector to DRAM */ | |
| 235 | unsigned char addr_mapping; | |
| 236 | /* 64-116 (Unbuffered) Reserved */ | |
| 237 | unsigned char res_64_116[53]; | |
| 238 | } unbuffered; | |
| 239 | struct { | |
| 240 | /* 60 (Registered) Module Nominal Height */ | |
| 241 | unsigned char mod_height; | |
| 242 | /* 61 (Registered) Module Maximum Thickness */ | |
| 243 | unsigned char mod_thickness; | |
| 244 | /* 62 (Registered) Reference Raw Card Used */ | |
| 245 | unsigned char ref_raw_card; | |
| 9490ff48 YS |
246 | /* 63 DIMM Module Attributes */ |
| 247 | unsigned char modu_attr; | |
| 248 | /* 64 RDIMM Thermal Heat Spreader Solution */ | |
| 249 | unsigned char thermal; | |
| 250 | /* 65 Register Manufacturer ID Code, Least Significant Byte */ | |
| 251 | unsigned char reg_id_lo; | |
| 252 | /* 66 Register Manufacturer ID Code, Most Significant Byte */ | |
| 253 | unsigned char reg_id_hi; | |
| 254 | /* 67 Register Revision Number */ | |
| 255 | unsigned char reg_rev; | |
| 256 | /* 68 Register Type */ | |
| 257 | unsigned char reg_type; | |
| 258 | /* 69-76 RC1,3,5...15 (MS Nibble) / RC0,2,4...14 (LS Nibble) */ | |
| 259 | unsigned char rcw[8]; | |
| 0f2cbe3f JY |
260 | } registered; |
| 261 | unsigned char uc[57]; /* 60-116 Module-Specific Section */ | |
| 262 | } mod_section; | |
| 263 | ||
| 264 | /* Unique Module ID: Bytes 117-125 */ | |
| 265 | unsigned char mmid_lsb; /* 117 Module MfgID Code LSB - JEP-106 */ | |
| 266 | unsigned char mmid_msb; /* 118 Module MfgID Code MSB - JEP-106 */ | |
| 267 | unsigned char mloc; /* 119 Mfg Location */ | |
| 268 | unsigned char mdate[2]; /* 120-121 Mfg Date */ | |
| 269 | unsigned char sernum[4]; /* 122-125 Module Serial Number */ | |
| 270 | ||
| 271 | /* CRC: Bytes 126-127 */ | |
| 272 | unsigned char crc[2]; /* 126-127 SPD CRC */ | |
| 273 | ||
| 274 | /* Other Manufacturer Fields and User Space: Bytes 128-255 */ | |
| 275 | unsigned char mpart[18]; /* 128-145 Mfg's Module Part Number */ | |
| 276 | unsigned char mrev[2]; /* 146-147 Module Revision Code */ | |
| 277 | ||
| 278 | unsigned char dmid_lsb; /* 148 DRAM MfgID Code LSB - JEP-106 */ | |
| 279 | unsigned char dmid_msb; /* 149 DRAM MfgID Code MSB - JEP-106 */ | |
| 280 | ||
| 281 | unsigned char msd[26]; /* 150-175 Mfg's Specific Data */ | |
| 282 | unsigned char cust[80]; /* 176-255 Open for Customer Use */ | |
| 283 | ||
| 284 | } ddr3_spd_eeprom_t; | |
| 285 | ||
| 286 | extern unsigned int ddr1_spd_check(const ddr1_spd_eeprom_t *spd); | |
| 287 | extern void ddr1_spd_dump(const ddr1_spd_eeprom_t *spd); | |
| 288 | extern unsigned int ddr2_spd_check(const ddr2_spd_eeprom_t *spd); | |
| 289 | extern void ddr2_spd_dump(const ddr2_spd_eeprom_t *spd); | |
| c360ceac | 290 | extern unsigned int ddr3_spd_check(const ddr3_spd_eeprom_t *spd); |
| 0f2cbe3f JY |
291 | |
| 292 | /* | |
| 293 | * Byte 2 Fundamental Memory Types. | |
| 294 | */ | |
| 295 | #define SPD_MEMTYPE_FPM (0x01) | |
| 296 | #define SPD_MEMTYPE_EDO (0x02) | |
| 297 | #define SPD_MEMTYPE_PIPE_NIBBLE (0x03) | |
| 298 | #define SPD_MEMTYPE_SDRAM (0x04) | |
| 299 | #define SPD_MEMTYPE_ROM (0x05) | |
| 300 | #define SPD_MEMTYPE_SGRAM (0x06) | |
| 301 | #define SPD_MEMTYPE_DDR (0x07) | |
| 302 | #define SPD_MEMTYPE_DDR2 (0x08) | |
| 303 | #define SPD_MEMTYPE_DDR2_FBDIMM (0x09) | |
| 304 | #define SPD_MEMTYPE_DDR2_FBDIMM_PROBE (0x0A) | |
| 305 | #define SPD_MEMTYPE_DDR3 (0x0B) | |
| 306 | ||
| c360ceac DL |
307 | /* |
| 308 | * Byte 3 Key Byte / Module Type for DDR3 SPD | |
| 309 | */ | |
| 310 | #define SPD_MODULETYPE_RDIMM (0x01) | |
| 311 | #define SPD_MODULETYPE_UDIMM (0x02) | |
| 312 | #define SPD_MODULETYPE_SODIMM (0x03) | |
| 313 | #define SPD_MODULETYPE_MICRODIMM (0x04) | |
| 314 | #define SPD_MODULETYPE_MINIRDIMM (0x05) | |
| 315 | #define SPD_MODULETYPE_MINIUDIMM (0x06) | |
| 316 | ||
| 0f2cbe3f | 317 | #endif /* _DDR_SPD_H_ */ |