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58e5e9af | 1 | /* |
34e026f9 | 2 | * Copyright 2008-2014 Freescale Semiconductor, Inc. |
58e5e9af KG |
3 | * |
4 | * This program is free software; you can redistribute it and/or | |
5 | * modify it under the terms of the GNU General Public License | |
6 | * Version 2 as published by the Free Software Foundation. | |
7 | */ | |
8 | ||
9 | #ifndef FSL_DDR_MAIN_H | |
10 | #define FSL_DDR_MAIN_H | |
11 | ||
34e026f9 | 12 | #include <fsl_ddrc_version.h> |
5614e71b YS |
13 | #include <fsl_ddr_sdram.h> |
14 | #include <fsl_ddr_dimm_params.h> | |
58e5e9af | 15 | |
5614e71b | 16 | #include <common_timing_params.h> |
58e5e9af | 17 | |
1d71efbb YS |
18 | #ifndef CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS |
19 | /* All controllers are for main memory */ | |
20 | #define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS CONFIG_NUM_DDR_CONTROLLERS | |
21 | #endif | |
22 | ||
4e5b1bd0 YS |
23 | #ifdef CONFIG_SYS_FSL_DDR_LE |
24 | #define ddr_in32(a) in_le32(a) | |
25 | #define ddr_out32(a, v) out_le32(a, v) | |
dda3b610 YS |
26 | #define ddr_setbits32(a, v) setbits_le32(a, v) |
27 | #define ddr_clrbits32(a, v) clrbits_le32(a, v) | |
28 | #define ddr_clrsetbits32(a, clear, set) clrsetbits_le32(a, clear, set) | |
4e5b1bd0 YS |
29 | #else |
30 | #define ddr_in32(a) in_be32(a) | |
31 | #define ddr_out32(a, v) out_be32(a, v) | |
dda3b610 YS |
32 | #define ddr_setbits32(a, v) setbits_be32(a, v) |
33 | #define ddr_clrbits32(a, v) clrbits_be32(a, v) | |
34 | #define ddr_clrsetbits32(a, clear, set) clrsetbits_be32(a, clear, set) | |
4e5b1bd0 YS |
35 | #endif |
36 | ||
34e026f9 YS |
37 | #define _DDR_ADDR CONFIG_SYS_FSL_DDR_ADDR |
38 | ||
39 | u32 fsl_ddr_get_version(void); | |
40 | ||
1b3e3c4f | 41 | #if defined(CONFIG_DDR_SPD) || defined(CONFIG_SPD_EEPROM) |
58e5e9af KG |
42 | /* |
43 | * Bind the main DDR setup driver's generic names | |
44 | * to this specific DDR technology. | |
45 | */ | |
46 | static __inline__ int | |
47 | compute_dimm_parameters(const generic_spd_eeprom_t *spd, | |
48 | dimm_params_t *pdimm, | |
49 | unsigned int dimm_number) | |
50 | { | |
51 | return ddr_compute_dimm_parameters(spd, pdimm, dimm_number); | |
52 | } | |
1b3e3c4f | 53 | #endif |
58e5e9af KG |
54 | |
55 | /* | |
56 | * Data Structures | |
57 | * | |
58 | * All data structures have to be on the stack | |
59 | */ | |
6d0f6bcf JCPV |
60 | #define CONFIG_SYS_NUM_DDR_CTLRS CONFIG_NUM_DDR_CONTROLLERS |
61 | #define CONFIG_SYS_DIMM_SLOTS_PER_CTLR CONFIG_DIMM_SLOTS_PER_CTLR | |
58e5e9af KG |
62 | |
63 | typedef struct { | |
64 | generic_spd_eeprom_t | |
6d0f6bcf | 65 | spd_installed_dimms[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_SYS_DIMM_SLOTS_PER_CTLR]; |
58e5e9af | 66 | struct dimm_params_s |
6d0f6bcf JCPV |
67 | dimm_params[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_SYS_DIMM_SLOTS_PER_CTLR]; |
68 | memctl_options_t memctl_opts[CONFIG_SYS_NUM_DDR_CTLRS]; | |
69 | common_timing_params_t common_timing_params[CONFIG_SYS_NUM_DDR_CTLRS]; | |
70 | fsl_ddr_cfg_regs_t fsl_ddr_config_reg[CONFIG_SYS_NUM_DDR_CTLRS]; | |
1d71efbb YS |
71 | unsigned int first_ctrl; |
72 | unsigned int num_ctrls; | |
73 | unsigned long long mem_base; | |
74 | unsigned int dimm_slots_per_ctrl; | |
75 | int (*board_need_mem_reset)(void); | |
76 | void (*board_mem_reset)(void); | |
77 | void (*board_mem_de_reset)(void); | |
58e5e9af KG |
78 | } fsl_ddr_info_t; |
79 | ||
80 | /* Compute steps */ | |
81 | #define STEP_GET_SPD (1 << 0) | |
82 | #define STEP_COMPUTE_DIMM_PARMS (1 << 1) | |
83 | #define STEP_COMPUTE_COMMON_PARMS (1 << 2) | |
84 | #define STEP_GATHER_OPTS (1 << 3) | |
85 | #define STEP_ASSIGN_ADDRESSES (1 << 4) | |
86 | #define STEP_COMPUTE_REGS (1 << 5) | |
87 | #define STEP_PROGRAM_REGS (1 << 6) | |
88 | #define STEP_ALL 0xFFF | |
89 | ||
6f5e1dc5 | 90 | unsigned long long |
fc0c2b6f HW |
91 | fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step, |
92 | unsigned int size_only); | |
6f5e1dc5 | 93 | const char *step_to_string(unsigned int step); |
58e5e9af | 94 | |
6f5e1dc5 | 95 | unsigned int compute_fsl_memctl_config_regs(const memctl_options_t *popts, |
58e5e9af KG |
96 | fsl_ddr_cfg_regs_t *ddr, |
97 | const common_timing_params_t *common_dimm, | |
98 | const dimm_params_t *dimm_parameters, | |
fc0c2b6f HW |
99 | unsigned int dbw_capacity_adjust, |
100 | unsigned int size_only); | |
6f5e1dc5 YS |
101 | unsigned int compute_lowest_common_dimm_parameters( |
102 | const dimm_params_t *dimm_params, | |
103 | common_timing_params_t *outpdimm, | |
104 | unsigned int number_of_dimms); | |
0dd38a35 | 105 | unsigned int populate_memctl_options(int all_dimms_registered, |
58e5e9af | 106 | memctl_options_t *popts, |
dfb49108 | 107 | dimm_params_t *pdimm, |
58e5e9af | 108 | unsigned int ctrl_num); |
6f5e1dc5 | 109 | void check_interleaving_options(fsl_ddr_info_t *pinfo); |
58e5e9af | 110 | |
6f5e1dc5 YS |
111 | unsigned int mclk_to_picos(unsigned int mclk); |
112 | unsigned int get_memory_clk_period_ps(void); | |
113 | unsigned int picos_to_mclk(unsigned int picos); | |
114 | void fsl_ddr_set_lawbar( | |
115 | const common_timing_params_t *memctl_common_params, | |
116 | unsigned int memctl_interleaved, | |
117 | unsigned int ctrl_num); | |
118 | ||
e8ba6c50 JY |
119 | int fsl_ddr_interactive_env_var_exists(void); |
120 | unsigned long long fsl_ddr_interactive(fsl_ddr_info_t *pinfo, int var_is_set); | |
6f5e1dc5 | 121 | void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd, |
1d71efbb | 122 | unsigned int ctrl_num, unsigned int dimm_slots_per_ctrl); |
6f5e1dc5 YS |
123 | |
124 | int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); | |
125 | unsigned int check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr); | |
4e5b1bd0 | 126 | void board_add_ram_info(int use_default); |
6f5e1dc5 YS |
127 | |
128 | /* processor specific function */ | |
129 | void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, | |
c63e1370 | 130 | unsigned int ctrl_num, int step); |
1b3e3c4f YS |
131 | |
132 | /* board specific function */ | |
133 | int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, | |
134 | unsigned int controller_number, | |
135 | unsigned int dimm_number); | |
58e5e9af | 136 | #endif |