[people/ms/u-boot.git] / include / fsl_ddr_sdram.h

/*
 * Copyright 2008-2014 Freescale Semiconductor, Inc.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * Version 2 as published by the Free Software Foundation.
 */

#ifndef FSL_DDR_MEMCTL_H
#define FSL_DDR_MEMCTL_H

/*
 * Pick a basic DDR Technology.
 */
#include <ddr_spd.h>
#include <fsl_ddrc_version.h>

#define SDRAM_TYPE_DDR1		2
#define SDRAM_TYPE_DDR2		3
#define SDRAM_TYPE_LPDDR1	6
#define SDRAM_TYPE_DDR3		7
#define SDRAM_TYPE_DDR4		5

#define DDR_BL4		4	/* burst length 4 */
#define DDR_BC4		DDR_BL4	/* burst chop for ddr3 */
#define DDR_OTF		6	/* on-the-fly BC4 and BL8 */
#define DDR_BL8		8	/* burst length 8 */

#define DDR3_RTT_OFF		0
#define DDR3_RTT_60_OHM		1 /* RTT_Nom = RZQ/4 */
#define DDR3_RTT_120_OHM	2 /* RTT_Nom = RZQ/2 */
#define DDR3_RTT_40_OHM		3 /* RTT_Nom = RZQ/6 */
#define DDR3_RTT_20_OHM		4 /* RTT_Nom = RZQ/12 */
#define DDR3_RTT_30_OHM		5 /* RTT_Nom = RZQ/8 */

#define DDR2_RTT_OFF		0
#define DDR2_RTT_75_OHM		1
#define DDR2_RTT_150_OHM	2
#define DDR2_RTT_50_OHM		3

#if defined(CONFIG_SYS_FSL_DDR1)
#define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR	(1)
typedef ddr1_spd_eeprom_t generic_spd_eeprom_t;
#ifndef CONFIG_FSL_SDRAM_TYPE
#define CONFIG_FSL_SDRAM_TYPE	SDRAM_TYPE_DDR1
#endif
#elif defined(CONFIG_SYS_FSL_DDR2)
#define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR	(3)
typedef ddr2_spd_eeprom_t generic_spd_eeprom_t;
#ifndef CONFIG_FSL_SDRAM_TYPE
#define CONFIG_FSL_SDRAM_TYPE	SDRAM_TYPE_DDR2
#endif
#elif defined(CONFIG_SYS_FSL_DDR3)
typedef ddr3_spd_eeprom_t generic_spd_eeprom_t;
#ifndef CONFIG_FSL_SDRAM_TYPE
#define CONFIG_FSL_SDRAM_TYPE	SDRAM_TYPE_DDR3
#endif
#elif defined(CONFIG_SYS_FSL_DDR4)
#define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR	(3)	/* FIXME */
typedef struct ddr4_spd_eeprom_s generic_spd_eeprom_t;
#ifndef CONFIG_FSL_SDRAM_TYPE
#define CONFIG_FSL_SDRAM_TYPE	SDRAM_TYPE_DDR4
#endif
#endif	/* #if defined(CONFIG_SYS_FSL_DDR1) */

#define FSL_DDR_ODT_NEVER		0x0
#define FSL_DDR_ODT_CS			0x1
#define FSL_DDR_ODT_ALL_OTHER_CS	0x2
#define FSL_DDR_ODT_OTHER_DIMM		0x3
#define FSL_DDR_ODT_ALL			0x4
#define FSL_DDR_ODT_SAME_DIMM		0x5
#define FSL_DDR_ODT_CS_AND_OTHER_DIMM	0x6
#define FSL_DDR_ODT_OTHER_CS_ONSAMEDIMM	0x7

/* define bank(chip select) interleaving mode */
#define FSL_DDR_CS0_CS1			0x40
#define FSL_DDR_CS2_CS3			0x20
#define FSL_DDR_CS0_CS1_AND_CS2_CS3	(FSL_DDR_CS0_CS1 | FSL_DDR_CS2_CS3)
#define FSL_DDR_CS0_CS1_CS2_CS3		(FSL_DDR_CS0_CS1_AND_CS2_CS3 | 0x04)

/* define memory controller interleaving mode */
#define FSL_DDR_CACHE_LINE_INTERLEAVING	0x0
#define FSL_DDR_PAGE_INTERLEAVING	0x1
#define FSL_DDR_BANK_INTERLEAVING	0x2
#define FSL_DDR_SUPERBANK_INTERLEAVING	0x3
#define FSL_DDR_256B_INTERLEAVING	0x8
#define FSL_DDR_3WAY_1KB_INTERLEAVING	0xA
#define FSL_DDR_3WAY_4KB_INTERLEAVING	0xC
#define FSL_DDR_3WAY_8KB_INTERLEAVING	0xD
/* placeholder for 4-way interleaving */
#define FSL_DDR_4WAY_1KB_INTERLEAVING	0x1A
#define FSL_DDR_4WAY_4KB_INTERLEAVING	0x1C
#define FSL_DDR_4WAY_8KB_INTERLEAVING	0x1D

#define SDRAM_CS_CONFIG_EN		0x80000000

/* DDR_SDRAM_CFG - DDR SDRAM Control Configuration
 */
#define SDRAM_CFG_MEM_EN		0x80000000
#define SDRAM_CFG_SREN			0x40000000
#define SDRAM_CFG_ECC_EN		0x20000000
#define SDRAM_CFG_RD_EN			0x10000000
#define SDRAM_CFG_SDRAM_TYPE_DDR1	0x02000000
#define SDRAM_CFG_SDRAM_TYPE_DDR2	0x03000000
#define SDRAM_CFG_SDRAM_TYPE_MASK	0x07000000
#define SDRAM_CFG_SDRAM_TYPE_SHIFT	24
#define SDRAM_CFG_DYN_PWR		0x00200000
#define SDRAM_CFG_DBW_MASK		0x00180000
#define SDRAM_CFG_DBW_SHIFT		19
#define SDRAM_CFG_32_BE			0x00080000
#define SDRAM_CFG_16_BE			0x00100000
#define SDRAM_CFG_8_BE			0x00040000
#define SDRAM_CFG_NCAP			0x00020000
#define SDRAM_CFG_2T_EN			0x00008000
#define SDRAM_CFG_BI			0x00000001

#define SDRAM_CFG2_FRC_SR		0x80000000
#define SDRAM_CFG2_D_INIT		0x00000010
#define SDRAM_CFG2_ODT_CFG_MASK		0x00600000
#define SDRAM_CFG2_ODT_NEVER		0
#define SDRAM_CFG2_ODT_ONLY_WRITE	1
#define SDRAM_CFG2_ODT_ONLY_READ	2
#define SDRAM_CFG2_ODT_ALWAYS		3

#define TIMING_CFG_2_CPO_MASK	0x0F800000

#if defined(CONFIG_SYS_FSL_DDR_VER) && \
	(CONFIG_SYS_FSL_DDR_VER > FSL_DDR_VER_4_4)
#define RD_TO_PRE_MASK		0xf
#define RD_TO_PRE_SHIFT		13
#define WR_DATA_DELAY_MASK	0xf
#define WR_DATA_DELAY_SHIFT	9
#else
#define RD_TO_PRE_MASK		0x7
#define RD_TO_PRE_SHIFT		13
#define WR_DATA_DELAY_MASK	0x7
#define WR_DATA_DELAY_SHIFT	10
#endif

/* DDR_MD_CNTL */
#define MD_CNTL_MD_EN		0x80000000
#define MD_CNTL_CS_SEL_CS0	0x00000000
#define MD_CNTL_CS_SEL_CS1	0x10000000
#define MD_CNTL_CS_SEL_CS2	0x20000000
#define MD_CNTL_CS_SEL_CS3	0x30000000
#define MD_CNTL_CS_SEL_CS0_CS1	0x40000000
#define MD_CNTL_CS_SEL_CS2_CS3	0x50000000
#define MD_CNTL_MD_SEL_MR	0x00000000
#define MD_CNTL_MD_SEL_EMR	0x01000000
#define MD_CNTL_MD_SEL_EMR2	0x02000000
#define MD_CNTL_MD_SEL_EMR3	0x03000000
#define MD_CNTL_SET_REF		0x00800000
#define MD_CNTL_SET_PRE		0x00400000
#define MD_CNTL_CKE_CNTL_LOW	0x00100000
#define MD_CNTL_CKE_CNTL_HIGH	0x00200000
#define MD_CNTL_WRCW		0x00080000
#define MD_CNTL_MD_VALUE(x)	(x & 0x0000FFFF)

/* DDR_CDR1 */
#define DDR_CDR1_DHC_EN	0x80000000
#define DDR_CDR1_ODT_SHIFT	17
#define DDR_CDR1_ODT_MASK	0x6
#define DDR_CDR2_ODT_MASK	0x1
#define DDR_CDR1_ODT(x) ((x & DDR_CDR1_ODT_MASK) << DDR_CDR1_ODT_SHIFT)
#define DDR_CDR2_ODT(x) (x & DDR_CDR2_ODT_MASK)
#define DDR_CDR2_VREF_OVRD(x)	(0x00008080 | ((((x) - 37) & 0x3F) << 8))
#define DDR_CDR2_VREF_TRAIN_EN	0x00000080

#if (defined(CONFIG_SYS_FSL_DDR_VER) && \
	(CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7))
#ifdef CONFIG_SYS_FSL_DDR3L
#define DDR_CDR_ODT_OFF		0x0
#define DDR_CDR_ODT_120ohm	0x1
#define DDR_CDR_ODT_200ohm	0x2
#define DDR_CDR_ODT_75ohm	0x3
#define DDR_CDR_ODT_60ohm	0x5
#define DDR_CDR_ODT_46ohm	0x7
#elif defined(CONFIG_SYS_FSL_DDR4)
#define DDR_CDR_ODT_OFF		0x0
#define DDR_CDR_ODT_100ohm	0x1
#define DDR_CDR_ODT_120OHM	0x2
#define DDR_CDR_ODT_80ohm	0x3
#define DDR_CDR_ODT_60ohm	0x4
#define DDR_CDR_ODT_40ohm	0x5
#define DDR_CDR_ODT_50ohm	0x6
#define DDR_CDR_ODT_30ohm	0x7
#else
#define DDR_CDR_ODT_OFF		0x0
#define DDR_CDR_ODT_120ohm	0x1
#define DDR_CDR_ODT_180ohm	0x2
#define DDR_CDR_ODT_75ohm	0x3
#define DDR_CDR_ODT_110ohm	0x4
#define DDR_CDR_ODT_60hm	0x5
#define DDR_CDR_ODT_70ohm	0x6
#define DDR_CDR_ODT_47ohm	0x7
#endif /* DDR3L */
#else
#define DDR_CDR_ODT_75ohm	0x0
#define DDR_CDR_ODT_55ohm	0x1
#define DDR_CDR_ODT_60ohm	0x2
#define DDR_CDR_ODT_50ohm	0x3
#define DDR_CDR_ODT_150ohm	0x4
#define DDR_CDR_ODT_43ohm	0x5
#define DDR_CDR_ODT_120ohm	0x6
#endif

#define DDR_INIT_ADDR_EXT_UIA	(1 << 31)

/* Record of register values computed */
typedef struct fsl_ddr_cfg_regs_s {
	struct {
		unsigned int bnds;
		unsigned int config;
		unsigned int config_2;
	} cs[CONFIG_CHIP_SELECTS_PER_CTRL];
	unsigned int timing_cfg_3;
	unsigned int timing_cfg_0;
	unsigned int timing_cfg_1;
	unsigned int timing_cfg_2;
	unsigned int ddr_sdram_cfg;
	unsigned int ddr_sdram_cfg_2;
	unsigned int ddr_sdram_cfg_3;
	unsigned int ddr_sdram_mode;
	unsigned int ddr_sdram_mode_2;
	unsigned int ddr_sdram_mode_3;
	unsigned int ddr_sdram_mode_4;
	unsigned int ddr_sdram_mode_5;
	unsigned int ddr_sdram_mode_6;
	unsigned int ddr_sdram_mode_7;
	unsigned int ddr_sdram_mode_8;
	unsigned int ddr_sdram_mode_9;
	unsigned int ddr_sdram_mode_10;
	unsigned int ddr_sdram_mode_11;
	unsigned int ddr_sdram_mode_12;
	unsigned int ddr_sdram_mode_13;
	unsigned int ddr_sdram_mode_14;
	unsigned int ddr_sdram_mode_15;
	unsigned int ddr_sdram_mode_16;
	unsigned int ddr_sdram_md_cntl;
	unsigned int ddr_sdram_interval;
	unsigned int ddr_data_init;
	unsigned int ddr_sdram_clk_cntl;
	unsigned int ddr_init_addr;
	unsigned int ddr_init_ext_addr;
	unsigned int timing_cfg_4;
	unsigned int timing_cfg_5;
	unsigned int timing_cfg_6;
	unsigned int timing_cfg_7;
	unsigned int timing_cfg_8;
	unsigned int timing_cfg_9;
	unsigned int ddr_zq_cntl;
	unsigned int ddr_wrlvl_cntl;
	unsigned int ddr_wrlvl_cntl_2;
	unsigned int ddr_wrlvl_cntl_3;
	unsigned int ddr_sr_cntr;
	unsigned int ddr_sdram_rcw_1;
	unsigned int ddr_sdram_rcw_2;
	unsigned int ddr_sdram_rcw_3;
	unsigned int ddr_sdram_rcw_4;
	unsigned int ddr_sdram_rcw_5;
	unsigned int ddr_sdram_rcw_6;
	unsigned int dq_map_0;
	unsigned int dq_map_1;
	unsigned int dq_map_2;
	unsigned int dq_map_3;
	unsigned int ddr_eor;
	unsigned int ddr_cdr1;
	unsigned int ddr_cdr2;
	unsigned int err_disable;
	unsigned int err_int_en;
	unsigned int debug[32];
} fsl_ddr_cfg_regs_t;

typedef struct memctl_options_partial_s {
	unsigned int all_dimms_ecc_capable;
	unsigned int all_dimms_tckmax_ps;
	unsigned int all_dimms_burst_lengths_bitmask;
	unsigned int all_dimms_registered;
	unsigned int all_dimms_unbuffered;
	/*	unsigned int lowest_common_spd_caslat; */
	unsigned int all_dimms_minimum_trcd_ps;
} memctl_options_partial_t;

#define DDR_DATA_BUS_WIDTH_64 0
#define DDR_DATA_BUS_WIDTH_32 1
#define DDR_DATA_BUS_WIDTH_16 2
#define DDR_CSWL_CS0	0x04000001
/*
 * Generalized parameters for memory controller configuration,
 * might be a little specific to the FSL memory controller
 */
typedef struct memctl_options_s {
	/*
	 * Memory organization parameters
	 *
	 * if DIMM is present in the system
	 * where DIMMs are with respect to chip select
	 * where chip selects are with respect to memory boundaries
	 */
	unsigned int registered_dimm_en;    /* use registered DIMM support */

	/* Options local to a Chip Select */
	struct cs_local_opts_s {
		unsigned int auto_precharge;
		unsigned int odt_rd_cfg;
		unsigned int odt_wr_cfg;
		unsigned int odt_rtt_norm;
		unsigned int odt_rtt_wr;
	} cs_local_opts[CONFIG_CHIP_SELECTS_PER_CTRL];

	/* Special configurations for chip select */
	unsigned int memctl_interleaving;
	unsigned int memctl_interleaving_mode;
	unsigned int ba_intlv_ctl;
	unsigned int addr_hash;

	/* Operational mode parameters */
	unsigned int ecc_mode;	 /* Use ECC? */
	/* Initialize ECC using memory controller? */
	unsigned int ecc_init_using_memctl;
	unsigned int dqs_config;	/* Use DQS? maybe only with DDR2? */
	/* SREN - self-refresh during sleep */
	unsigned int self_refresh_in_sleep;
	unsigned int dynamic_power;	/* DYN_PWR */
	/* memory data width to use (16-bit, 32-bit, 64-bit) */
	unsigned int data_bus_width;
	unsigned int burst_length;	/* BL4, OTF and BL8 */
	/* On-The-Fly Burst Chop enable */
	unsigned int otf_burst_chop_en;
	/* mirrior DIMMs for DDR3 */
	unsigned int mirrored_dimm;
	unsigned int quad_rank_present;
	unsigned int ap_en;	/* address parity enable for RDIMM */
	unsigned int x4_en;	/* enable x4 devices */

	/* Global Timing Parameters */
	unsigned int cas_latency_override;
	unsigned int cas_latency_override_value;
	unsigned int use_derated_caslat;
	unsigned int additive_latency_override;
	unsigned int additive_latency_override_value;

	unsigned int clk_adjust;		/* */
	unsigned int cpo_override;
	unsigned int write_data_delay;		/* DQS adjust */

	unsigned int cswl_override;
	unsigned int wrlvl_override;
	unsigned int wrlvl_sample;		/* Write leveling */
	unsigned int wrlvl_start;
	unsigned int wrlvl_ctl_2;
	unsigned int wrlvl_ctl_3;

	unsigned int half_strength_driver_enable;
	unsigned int twot_en;
	unsigned int threet_en;
	unsigned int bstopre;
	unsigned int tfaw_window_four_activates_ps;	/* tFAW --  FOUR_ACT */

	/* Rtt impedance */
	unsigned int rtt_override;		/* rtt_override enable */
	unsigned int rtt_override_value;	/* that is Rtt_Nom for DDR3 */
	unsigned int rtt_wr_override_value;	/* this is Rtt_WR for DDR3 */

	/* Automatic self refresh */
	unsigned int auto_self_refresh_en;
	unsigned int sr_it;
	/* ZQ calibration */
	unsigned int zq_en;
	/* Write leveling */
	unsigned int wrlvl_en;
	/* RCW override for RDIMM */
	unsigned int rcw_override;
	unsigned int rcw_1;
	unsigned int rcw_2;
	/* control register 1 */
	unsigned int ddr_cdr1;
	unsigned int ddr_cdr2;

	unsigned int trwt_override;
	unsigned int trwt;			/* read-to-write turnaround */
} memctl_options_t;

phys_size_t fsl_ddr_sdram(void);
phys_size_t fsl_ddr_sdram_size(void);
phys_size_t fsl_other_ddr_sdram(unsigned long long base,
				unsigned int first_ctrl,
				unsigned int num_ctrls,
				unsigned int dimm_slots_per_ctrl,
				int (*board_need_reset)(void),
				void (*board_reset)(void),
				void (*board_de_reset)(void));
extern int fsl_use_spd(void);
void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
			     unsigned int ctrl_num, int step);
u32 fsl_ddr_get_intl3r(void);
void print_ddr_info(unsigned int start_ctrl);

static void __board_assert_mem_reset(void)
{
}

static void __board_deassert_mem_reset(void)
{
}

void board_assert_mem_reset(void)
	__attribute__((weak, alias("__board_assert_mem_reset")));

void board_deassert_mem_reset(void)
	__attribute__((weak, alias("__board_deassert_mem_reset")));

static int __board_need_mem_reset(void)
{
	return 0;
}

int board_need_mem_reset(void)
	__attribute__((weak, alias("__board_need_mem_reset")));

#if defined(CONFIG_DEEP_SLEEP)
void board_mem_sleep_setup(void);
bool is_warm_boot(void);
int fsl_dp_resume(void);
#endif

/*
 * The 85xx boards have a common prototype for fixed_sdram so put the
 * declaration here.
 */
#ifdef CONFIG_MPC85xx
extern phys_size_t fixed_sdram(void);
#endif

#if defined(CONFIG_DDR_ECC)
extern void ddr_enable_ecc(unsigned int dram_size);
#endif


typedef struct fixed_ddr_parm{
	int min_freq;
	int max_freq;
	fsl_ddr_cfg_regs_t *ddr_settings;
} fixed_ddr_parm_t;
#endif
Commit	Line	Data
58e5e9af	1	/*
34e026f9	2	* Copyright 2008-2014 Freescale Semiconductor, Inc.
58e5e9af KG	3	*
	4	* This program is free software; you can redistribute it and/or
	5	* modify it under the terms of the GNU General Public License
	6	* Version 2 as published by the Free Software Foundation.
	7	*/
	8
	9	#ifndef FSL_DDR_MEMCTL_H
	10	#define FSL_DDR_MEMCTL_H
	11
	12	/*
	13	* Pick a basic DDR Technology.
	14	*/
	15	#include <ddr_spd.h>
34e026f9	16	#include <fsl_ddrc_version.h>
58e5e9af	17
34e026f9 YS	18	#define SDRAM_TYPE_DDR1 2
	19	#define SDRAM_TYPE_DDR2 3
	20	#define SDRAM_TYPE_LPDDR1 6
	21	#define SDRAM_TYPE_DDR3 7
	22	#define SDRAM_TYPE_DDR4 5
58e5e9af	23
c360ceac DL	24	#define DDR_BL4 4 /* burst length 4 */
	25	#define DDR_BC4 DDR_BL4 /* burst chop for ddr3 */
	26	#define DDR_OTF 6 /* on-the-fly BC4 and BL8 */
	27	#define DDR_BL8 8 /* burst length 8 */
	28
e1fd16b6	29	#define DDR3_RTT_OFF 0
f8d05e5e DL	30	#define DDR3_RTT_60_OHM 1 /* RTT_Nom = RZQ/4 */
	31	#define DDR3_RTT_120_OHM 2 /* RTT_Nom = RZQ/2 */
	32	#define DDR3_RTT_40_OHM 3 /* RTT_Nom = RZQ/6 */
	33	#define DDR3_RTT_20_OHM 4 /* RTT_Nom = RZQ/12 */
	34	#define DDR3_RTT_30_OHM 5 /* RTT_Nom = RZQ/8 */
	35
4e57382f YS	36	#define DDR2_RTT_OFF 0
	37	#define DDR2_RTT_75_OHM 1
	38	#define DDR2_RTT_150_OHM 2
	39	#define DDR2_RTT_50_OHM 3
	40
5614e71b	41	#if defined(CONFIG_SYS_FSL_DDR1)
58e5e9af KG	42	#define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (1)
	43	typedef ddr1_spd_eeprom_t generic_spd_eeprom_t;
	44	#ifndef CONFIG_FSL_SDRAM_TYPE
	45	#define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR1
	46	#endif
5614e71b	47	#elif defined(CONFIG_SYS_FSL_DDR2)
58e5e9af KG	48	#define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (3)
	49	typedef ddr2_spd_eeprom_t generic_spd_eeprom_t;
	50	#ifndef CONFIG_FSL_SDRAM_TYPE
	51	#define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR2
	52	#endif
5614e71b	53	#elif defined(CONFIG_SYS_FSL_DDR3)
58e5e9af	54	typedef ddr3_spd_eeprom_t generic_spd_eeprom_t;
22ff3d01 DL	55	#ifndef CONFIG_FSL_SDRAM_TYPE
22ff3d01 DL	56	#define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR3
58e5e9af	57	#endif
34e026f9 YS	58	#elif defined(CONFIG_SYS_FSL_DDR4)
	59	#define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (3) /* FIXME */
	60	typedef struct ddr4_spd_eeprom_s generic_spd_eeprom_t;
	61	#ifndef CONFIG_FSL_SDRAM_TYPE
	62	#define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR4
	63	#endif
5614e71b	64	#endif /* #if defined(CONFIG_SYS_FSL_DDR1) */
58e5e9af	65
e1fd16b6 YS	66	#define FSL_DDR_ODT_NEVER 0x0
	67	#define FSL_DDR_ODT_CS 0x1
	68	#define FSL_DDR_ODT_ALL_OTHER_CS 0x2
	69	#define FSL_DDR_ODT_OTHER_DIMM 0x3
	70	#define FSL_DDR_ODT_ALL 0x4
	71	#define FSL_DDR_ODT_SAME_DIMM 0x5
	72	#define FSL_DDR_ODT_CS_AND_OTHER_DIMM 0x6
	73	#define FSL_DDR_ODT_OTHER_CS_ONSAMEDIMM 0x7
	74
dbbbb3ab HW	75	/* define bank(chip select) interleaving mode */
	76	#define FSL_DDR_CS0_CS1 0x40
	77	#define FSL_DDR_CS2_CS3 0x20
	78	#define FSL_DDR_CS0_CS1_AND_CS2_CS3 (FSL_DDR_CS0_CS1 \| FSL_DDR_CS2_CS3)
	79	#define FSL_DDR_CS0_CS1_CS2_CS3 (FSL_DDR_CS0_CS1_AND_CS2_CS3 \| 0x04)
	80
	81	/* define memory controller interleaving mode */
	82	#define FSL_DDR_CACHE_LINE_INTERLEAVING 0x0
	83	#define FSL_DDR_PAGE_INTERLEAVING 0x1
	84	#define FSL_DDR_BANK_INTERLEAVING 0x2
	85	#define FSL_DDR_SUPERBANK_INTERLEAVING 0x3
6b1e1254	86	#define FSL_DDR_256B_INTERLEAVING 0x8
a4c66509 YS	87	#define FSL_DDR_3WAY_1KB_INTERLEAVING 0xA
	88	#define FSL_DDR_3WAY_4KB_INTERLEAVING 0xC
	89	#define FSL_DDR_3WAY_8KB_INTERLEAVING 0xD
	90	/* placeholder for 4-way interleaving */
	91	#define FSL_DDR_4WAY_1KB_INTERLEAVING 0x1A
	92	#define FSL_DDR_4WAY_4KB_INTERLEAVING 0x1C
	93	#define FSL_DDR_4WAY_8KB_INTERLEAVING 0x1D
dbbbb3ab	94
123922b1 YS	95	#define SDRAM_CS_CONFIG_EN 0x80000000
123922b1 YS	96
e1be0d25 P	97	/* DDR_SDRAM_CFG - DDR SDRAM Control Configuration
	98	*/
	99	#define SDRAM_CFG_MEM_EN 0x80000000
	100	#define SDRAM_CFG_SREN 0x40000000
	101	#define SDRAM_CFG_ECC_EN 0x20000000
	102	#define SDRAM_CFG_RD_EN 0x10000000
	103	#define SDRAM_CFG_SDRAM_TYPE_DDR1 0x02000000
	104	#define SDRAM_CFG_SDRAM_TYPE_DDR2 0x03000000
	105	#define SDRAM_CFG_SDRAM_TYPE_MASK 0x07000000
	106	#define SDRAM_CFG_SDRAM_TYPE_SHIFT 24
	107	#define SDRAM_CFG_DYN_PWR 0x00200000
9c6b47d5	108	#define SDRAM_CFG_DBW_MASK 0x00180000
f31cfd19	109	#define SDRAM_CFG_DBW_SHIFT 19
e1be0d25	110	#define SDRAM_CFG_32_BE 0x00080000
0b3b1766	111	#define SDRAM_CFG_16_BE 0x00100000
e1be0d25 P	112	#define SDRAM_CFG_8_BE 0x00040000
	113	#define SDRAM_CFG_NCAP 0x00020000
	114	#define SDRAM_CFG_2T_EN 0x00008000
	115	#define SDRAM_CFG_BI 0x00000001
	116
a7787b78	117	#define SDRAM_CFG2_FRC_SR 0x80000000
91671913 YS	118	#define SDRAM_CFG2_D_INIT 0x00000010
91671913 YS	119	#define SDRAM_CFG2_ODT_CFG_MASK 0x00600000
cae7c1b5 YS	120	#define SDRAM_CFG2_ODT_NEVER 0
	121	#define SDRAM_CFG2_ODT_ONLY_WRITE 1
	122	#define SDRAM_CFG2_ODT_ONLY_READ 2
	123	#define SDRAM_CFG2_ODT_ALWAYS 3
91671913 YS	124
	125	#define TIMING_CFG_2_CPO_MASK 0x0F800000
	126
34e026f9 YS	127	#if defined(CONFIG_SYS_FSL_DDR_VER) && \
34e026f9 YS	128	(CONFIG_SYS_FSL_DDR_VER > FSL_DDR_VER_4_4)
c360ceac DL	129	#define RD_TO_PRE_MASK 0xf
	130	#define RD_TO_PRE_SHIFT 13
	131	#define WR_DATA_DELAY_MASK 0xf
	132	#define WR_DATA_DELAY_SHIFT 9
	133	#else
	134	#define RD_TO_PRE_MASK 0x7
	135	#define RD_TO_PRE_SHIFT 13
	136	#define WR_DATA_DELAY_MASK 0x7
	137	#define WR_DATA_DELAY_SHIFT 10
	138	#endif
	139
fa8d23c0 YS	140	/* DDR_MD_CNTL */
	141	#define MD_CNTL_MD_EN 0x80000000
	142	#define MD_CNTL_CS_SEL_CS0 0x00000000
	143	#define MD_CNTL_CS_SEL_CS1 0x10000000
	144	#define MD_CNTL_CS_SEL_CS2 0x20000000
	145	#define MD_CNTL_CS_SEL_CS3 0x30000000
	146	#define MD_CNTL_CS_SEL_CS0_CS1 0x40000000
	147	#define MD_CNTL_CS_SEL_CS2_CS3 0x50000000
	148	#define MD_CNTL_MD_SEL_MR 0x00000000
	149	#define MD_CNTL_MD_SEL_EMR 0x01000000
	150	#define MD_CNTL_MD_SEL_EMR2 0x02000000
	151	#define MD_CNTL_MD_SEL_EMR3 0x03000000
	152	#define MD_CNTL_SET_REF 0x00800000
	153	#define MD_CNTL_SET_PRE 0x00400000
	154	#define MD_CNTL_CKE_CNTL_LOW 0x00100000
	155	#define MD_CNTL_CKE_CNTL_HIGH 0x00200000
	156	#define MD_CNTL_WRCW 0x00080000
	157	#define MD_CNTL_MD_VALUE(x) (x & 0x0000FFFF)
	158
6b06d7dc YS	159	/* DDR_CDR1 */
6b06d7dc YS	160	#define DDR_CDR1_DHC_EN 0x80000000
57495e4e YS	161	#define DDR_CDR1_ODT_SHIFT 17
	162	#define DDR_CDR1_ODT_MASK 0x6
	163	#define DDR_CDR2_ODT_MASK 0x1
	164	#define DDR_CDR1_ODT(x) ((x & DDR_CDR1_ODT_MASK) << DDR_CDR1_ODT_SHIFT)
	165	#define DDR_CDR2_ODT(x) (x & DDR_CDR2_ODT_MASK)
34e026f9	166	#define DDR_CDR2_VREF_OVRD(x) (0x00008080 \| ((((x) - 37) & 0x3F) << 8))
a7787b78	167	#define DDR_CDR2_VREF_TRAIN_EN 0x00000080
57495e4e YS	168
	169	#if (defined(CONFIG_SYS_FSL_DDR_VER) && \
	170	(CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7))
34e026f9 YS	171	#ifdef CONFIG_SYS_FSL_DDR3L
	172	#define DDR_CDR_ODT_OFF 0x0
	173	#define DDR_CDR_ODT_120ohm 0x1
	174	#define DDR_CDR_ODT_200ohm 0x2
	175	#define DDR_CDR_ODT_75ohm 0x3
	176	#define DDR_CDR_ODT_60ohm 0x5
	177	#define DDR_CDR_ODT_46ohm 0x7
	178	#elif defined(CONFIG_SYS_FSL_DDR4)
	179	#define DDR_CDR_ODT_OFF 0x0
	180	#define DDR_CDR_ODT_100ohm 0x1
	181	#define DDR_CDR_ODT_120OHM 0x2
	182	#define DDR_CDR_ODT_80ohm 0x3
	183	#define DDR_CDR_ODT_60ohm 0x4
	184	#define DDR_CDR_ODT_40ohm 0x5
	185	#define DDR_CDR_ODT_50ohm 0x6
	186	#define DDR_CDR_ODT_30ohm 0x7
	187	#else
57495e4e YS	188	#define DDR_CDR_ODT_OFF 0x0
	189	#define DDR_CDR_ODT_120ohm 0x1
	190	#define DDR_CDR_ODT_180ohm 0x2
	191	#define DDR_CDR_ODT_75ohm 0x3
	192	#define DDR_CDR_ODT_110ohm 0x4
	193	#define DDR_CDR_ODT_60hm 0x5
	194	#define DDR_CDR_ODT_70ohm 0x6
	195	#define DDR_CDR_ODT_47ohm 0x7
34e026f9	196	#endif /* DDR3L */
57495e4e YS	197	#else
	198	#define DDR_CDR_ODT_75ohm 0x0
	199	#define DDR_CDR_ODT_55ohm 0x1
	200	#define DDR_CDR_ODT_60ohm 0x2
	201	#define DDR_CDR_ODT_50ohm 0x3
	202	#define DDR_CDR_ODT_150ohm 0x4
	203	#define DDR_CDR_ODT_43ohm 0x5
	204	#define DDR_CDR_ODT_120ohm 0x6
	205	#endif
6b06d7dc	206
a7787b78 TY	207	#define DDR_INIT_ADDR_EXT_UIA (1 << 31)
a7787b78 TY	208
58e5e9af KG	209	/* Record of register values computed */
	210	typedef struct fsl_ddr_cfg_regs_s {
	211	struct {
	212	unsigned int bnds;
	213	unsigned int config;
	214	unsigned int config_2;
	215	} cs[CONFIG_CHIP_SELECTS_PER_CTRL];
	216	unsigned int timing_cfg_3;
	217	unsigned int timing_cfg_0;
	218	unsigned int timing_cfg_1;
	219	unsigned int timing_cfg_2;
	220	unsigned int ddr_sdram_cfg;
	221	unsigned int ddr_sdram_cfg_2;
34e026f9	222	unsigned int ddr_sdram_cfg_3;
58e5e9af KG	223	unsigned int ddr_sdram_mode;
58e5e9af KG	224	unsigned int ddr_sdram_mode_2;
e1fd16b6 YS	225	unsigned int ddr_sdram_mode_3;
	226	unsigned int ddr_sdram_mode_4;
	227	unsigned int ddr_sdram_mode_5;
	228	unsigned int ddr_sdram_mode_6;
	229	unsigned int ddr_sdram_mode_7;
	230	unsigned int ddr_sdram_mode_8;
34e026f9 YS	231	unsigned int ddr_sdram_mode_9;
	232	unsigned int ddr_sdram_mode_10;
	233	unsigned int ddr_sdram_mode_11;
	234	unsigned int ddr_sdram_mode_12;
	235	unsigned int ddr_sdram_mode_13;
	236	unsigned int ddr_sdram_mode_14;
	237	unsigned int ddr_sdram_mode_15;
	238	unsigned int ddr_sdram_mode_16;
58e5e9af KG	239	unsigned int ddr_sdram_md_cntl;
	240	unsigned int ddr_sdram_interval;
	241	unsigned int ddr_data_init;
	242	unsigned int ddr_sdram_clk_cntl;
	243	unsigned int ddr_init_addr;
	244	unsigned int ddr_init_ext_addr;
	245	unsigned int timing_cfg_4;
	246	unsigned int timing_cfg_5;
34e026f9 YS	247	unsigned int timing_cfg_6;
	248	unsigned int timing_cfg_7;
	249	unsigned int timing_cfg_8;
	250	unsigned int timing_cfg_9;
58e5e9af KG	251	unsigned int ddr_zq_cntl;
58e5e9af KG	252	unsigned int ddr_wrlvl_cntl;
57495e4e YS	253	unsigned int ddr_wrlvl_cntl_2;
57495e4e YS	254	unsigned int ddr_wrlvl_cntl_3;
58e5e9af KG	255	unsigned int ddr_sr_cntr;
	256	unsigned int ddr_sdram_rcw_1;
	257	unsigned int ddr_sdram_rcw_2;
34e026f9 YS	258	unsigned int ddr_sdram_rcw_3;
	259	unsigned int ddr_sdram_rcw_4;
	260	unsigned int ddr_sdram_rcw_5;
	261	unsigned int ddr_sdram_rcw_6;
	262	unsigned int dq_map_0;
	263	unsigned int dq_map_1;
	264	unsigned int dq_map_2;
	265	unsigned int dq_map_3;
7fd101c9	266	unsigned int ddr_eor;
d2a9568c YS	267	unsigned int ddr_cdr1;
	268	unsigned int ddr_cdr2;
	269	unsigned int err_disable;
	270	unsigned int err_int_en;
	271	unsigned int debug[32];
58e5e9af KG	272	} fsl_ddr_cfg_regs_t;
	273
	274	typedef struct memctl_options_partial_s {
0dd38a35 PJ	275	unsigned int all_dimms_ecc_capable;
	276	unsigned int all_dimms_tckmax_ps;
	277	unsigned int all_dimms_burst_lengths_bitmask;
	278	unsigned int all_dimms_registered;
	279	unsigned int all_dimms_unbuffered;
34e026f9	280	/* unsigned int lowest_common_spd_caslat; */
0dd38a35	281	unsigned int all_dimms_minimum_trcd_ps;
58e5e9af KG	282	} memctl_options_partial_t;
58e5e9af KG	283
51d498f1 YS	284	#define DDR_DATA_BUS_WIDTH_64 0
	285	#define DDR_DATA_BUS_WIDTH_32 1
	286	#define DDR_DATA_BUS_WIDTH_16 2
ef87cab6	287	#define DDR_CSWL_CS0 0x04000001
58e5e9af KG	288	/*
	289	* Generalized parameters for memory controller configuration,
	290	* might be a little specific to the FSL memory controller
	291	*/
	292	typedef struct memctl_options_s {
	293	/*
	294	* Memory organization parameters
	295	*
	296	* if DIMM is present in the system
	297	* where DIMMs are with respect to chip select
	298	* where chip selects are with respect to memory boundaries
	299	*/
	300	unsigned int registered_dimm_en; /* use registered DIMM support */
	301
	302	/* Options local to a Chip Select */
	303	struct cs_local_opts_s {
	304	unsigned int auto_precharge;
	305	unsigned int odt_rd_cfg;
	306	unsigned int odt_wr_cfg;
e1fd16b6 YS	307	unsigned int odt_rtt_norm;
e1fd16b6 YS	308	unsigned int odt_rtt_wr;
58e5e9af KG	309	} cs_local_opts[CONFIG_CHIP_SELECTS_PER_CTRL];
	310
	311	/* Special configurations for chip select */
	312	unsigned int memctl_interleaving;
	313	unsigned int memctl_interleaving_mode;
	314	unsigned int ba_intlv_ctl;
7fd101c9	315	unsigned int addr_hash;
58e5e9af KG	316
58e5e9af KG	317	/* Operational mode parameters */
0dd38a35	318	unsigned int ecc_mode; /* Use ECC? */
58e5e9af	319	/* Initialize ECC using memory controller? */
0dd38a35 PJ	320	unsigned int ecc_init_using_memctl;
0dd38a35 PJ	321	unsigned int dqs_config; /* Use DQS? maybe only with DDR2? */
58e5e9af KG	322	/* SREN - self-refresh during sleep */
	323	unsigned int self_refresh_in_sleep;
	324	unsigned int dynamic_power; /* DYN_PWR */
	325	/* memory data width to use (16-bit, 32-bit, 64-bit) */
	326	unsigned int data_bus_width;
c360ceac DL	327	unsigned int burst_length; /* BL4, OTF and BL8 */
c360ceac DL	328	/* On-The-Fly Burst Chop enable */
0dd38a35	329	unsigned int otf_burst_chop_en;
c360ceac DL	330	/* mirrior DIMMs for DDR3 */
c360ceac DL	331	unsigned int mirrored_dimm;
5800e7ab	332	unsigned int quad_rank_present;
d2a9568c	333	unsigned int ap_en; /* address parity enable for RDIMM */
b61e0615	334	unsigned int x4_en; /* enable x4 devices */
58e5e9af KG	335
	336	/* Global Timing Parameters */
	337	unsigned int cas_latency_override;
	338	unsigned int cas_latency_override_value;
	339	unsigned int use_derated_caslat;
	340	unsigned int additive_latency_override;
	341	unsigned int additive_latency_override_value;
	342
	343	unsigned int clk_adjust; /* */
	344	unsigned int cpo_override;
	345	unsigned int write_data_delay; /* DQS adjust */
bdc9f7b5	346
ef87cab6	347	unsigned int cswl_override;
bdc9f7b5 DL	348	unsigned int wrlvl_override;
	349	unsigned int wrlvl_sample; /* Write leveling */
	350	unsigned int wrlvl_start;
57495e4e YS	351	unsigned int wrlvl_ctl_2;
57495e4e YS	352	unsigned int wrlvl_ctl_3;
bdc9f7b5	353
58e5e9af	354	unsigned int half_strength_driver_enable;
0dd38a35 PJ	355	unsigned int twot_en;
0dd38a35 PJ	356	unsigned int threet_en;
58e5e9af	357	unsigned int bstopre;
0dd38a35	358	unsigned int tfaw_window_four_activates_ps; /* tFAW -- FOUR_ACT */
22cca7e1	359
c360ceac DL	360	/* Rtt impedance */
	361	unsigned int rtt_override; /* rtt_override enable */
	362	unsigned int rtt_override_value; /* that is Rtt_Nom for DDR3 */
1aa3d08a	363	unsigned int rtt_wr_override_value; /* this is Rtt_WR for DDR3 */
c360ceac	364
22cca7e1 DL	365	/* Automatic self refresh */
	366	unsigned int auto_self_refresh_en;
	367	unsigned int sr_it;
c360ceac DL	368	/* ZQ calibration */
	369	unsigned int zq_en;
	370	/* Write leveling */
	371	unsigned int wrlvl_en;
d2a9568c YS	372	/* RCW override for RDIMM */
	373	unsigned int rcw_override;
	374	unsigned int rcw_1;
	375	unsigned int rcw_2;
	376	/* control register 1 */
	377	unsigned int ddr_cdr1;
57495e4e	378	unsigned int ddr_cdr2;
23f9670f YS	379
	380	unsigned int trwt_override;
	381	unsigned int trwt; /* read-to-write turnaround */
58e5e9af KG	382	} memctl_options_t;
58e5e9af KG	383
1d71efbb YS	384	phys_size_t fsl_ddr_sdram(void);
	385	phys_size_t fsl_ddr_sdram_size(void);
	386	phys_size_t fsl_other_ddr_sdram(unsigned long long base,
	387	unsigned int first_ctrl,
	388	unsigned int num_ctrls,
	389	unsigned int dimm_slots_per_ctrl,
	390	int (*board_need_reset)(void),
	391	void (*board_reset)(void),
	392	void (*board_de_reset)(void));
3dbd5d7d	393	extern int fsl_use_spd(void);
1d71efbb YS	394	void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
1d71efbb YS	395	unsigned int ctrl_num, int step);
f31cfd19	396	u32 fsl_ddr_get_intl3r(void);
1d71efbb	397	void print_ddr_info(unsigned int start_ctrl);
28a96671	398
c63e1370 YS	399	static void __board_assert_mem_reset(void)
	400	{
	401	}
	402
	403	static void __board_deassert_mem_reset(void)
	404	{
	405	}
	406
	407	void board_assert_mem_reset(void)
	408	__attribute__((weak, alias("__board_assert_mem_reset")));
	409
	410	void board_deassert_mem_reset(void)
	411	__attribute__((weak, alias("__board_deassert_mem_reset")));
	412
	413	static int __board_need_mem_reset(void)
	414	{
	415	return 0;
	416	}
	417
	418	int board_need_mem_reset(void)
	419	__attribute__((weak, alias("__board_need_mem_reset")));
	420
a7787b78 TY	421	#if defined(CONFIG_DEEP_SLEEP)
	422	void board_mem_sleep_setup(void);
	423	bool is_warm_boot(void);
	424	int fsl_dp_resume(void);
	425	#endif
aade2004	426
38dba0c2 BB	427	/*
	428	* The 85xx boards have a common prototype for fixed_sdram so put the
	429	* declaration here.
	430	*/
	431	#ifdef CONFIG_MPC85xx
	432	extern phys_size_t fixed_sdram(void);
	433	#endif
	434
	435	#if defined(CONFIG_DDR_ECC)
	436	extern void ddr_enable_ecc(unsigned int dram_size);
	437	#endif
	438
	439
28a96671 YS	440	typedef struct fixed_ddr_parm{
	441	int min_freq;
	442	int max_freq;
	443	fsl_ddr_cfg_regs_t *ddr_settings;
	444	} fixed_ddr_parm_t;
58e5e9af	445	#endif