[people/ms/u-boot.git] / include / fsl_esdhc.h

/*
 * FSL SD/MMC Defines
 *-------------------------------------------------------------------
 *
 * Copyright 2007-2008,2010-2011 Freescale Semiconductor, Inc
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef  __FSL_ESDHC_H__
#define	__FSL_ESDHC_H__

#include <linux/bitops.h>
#include <linux/errno.h>
#include <asm/byteorder.h>

/* needed for the mmc_cfg definition */
#include <mmc.h>

#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
#include "../board/freescale/common/qixis.h"
#endif

/* FSL eSDHC-specific constants */
#define SYSCTL			0x0002e02c
#define SYSCTL_INITA		0x08000000
#define SYSCTL_TIMEOUT_MASK	0x000f0000
#define SYSCTL_CLOCK_MASK	0x0000fff0
#if !defined(CONFIG_FSL_USDHC)
#define SYSCTL_CKEN		0x00000008
#define SYSCTL_PEREN		0x00000004
#define SYSCTL_HCKEN		0x00000002
#define SYSCTL_IPGEN		0x00000001
#endif
#define SYSCTL_RSTA		0x01000000
#define SYSCTL_RSTC		0x02000000
#define SYSCTL_RSTD		0x04000000

#define VENDORSPEC_CKEN		0x00004000
#define VENDORSPEC_PEREN	0x00002000
#define VENDORSPEC_HCKEN	0x00001000
#define VENDORSPEC_IPGEN	0x00000800
#define VENDORSPEC_INIT		0x20007809

#define IRQSTAT			0x0002e030
#define IRQSTAT_DMAE		(0x10000000)
#define IRQSTAT_AC12E		(0x01000000)
#define IRQSTAT_DEBE		(0x00400000)
#define IRQSTAT_DCE		(0x00200000)
#define IRQSTAT_DTOE		(0x00100000)
#define IRQSTAT_CIE		(0x00080000)
#define IRQSTAT_CEBE		(0x00040000)
#define IRQSTAT_CCE		(0x00020000)
#define IRQSTAT_CTOE		(0x00010000)
#define IRQSTAT_CINT		(0x00000100)
#define IRQSTAT_CRM		(0x00000080)
#define IRQSTAT_CINS		(0x00000040)
#define IRQSTAT_BRR		(0x00000020)
#define IRQSTAT_BWR		(0x00000010)
#define IRQSTAT_DINT		(0x00000008)
#define IRQSTAT_BGE		(0x00000004)
#define IRQSTAT_TC		(0x00000002)
#define IRQSTAT_CC		(0x00000001)

#define CMD_ERR		(IRQSTAT_CIE | IRQSTAT_CEBE | IRQSTAT_CCE)
#define DATA_ERR	(IRQSTAT_DEBE | IRQSTAT_DCE | IRQSTAT_DTOE | \
				IRQSTAT_DMAE)
#define DATA_COMPLETE	(IRQSTAT_TC | IRQSTAT_DINT)

#define IRQSTATEN		0x0002e034
#define IRQSTATEN_DMAE		(0x10000000)
#define IRQSTATEN_AC12E		(0x01000000)
#define IRQSTATEN_DEBE		(0x00400000)
#define IRQSTATEN_DCE		(0x00200000)
#define IRQSTATEN_DTOE		(0x00100000)
#define IRQSTATEN_CIE		(0x00080000)
#define IRQSTATEN_CEBE		(0x00040000)
#define IRQSTATEN_CCE		(0x00020000)
#define IRQSTATEN_CTOE		(0x00010000)
#define IRQSTATEN_CINT		(0x00000100)
#define IRQSTATEN_CRM		(0x00000080)
#define IRQSTATEN_CINS		(0x00000040)
#define IRQSTATEN_BRR		(0x00000020)
#define IRQSTATEN_BWR		(0x00000010)
#define IRQSTATEN_DINT		(0x00000008)
#define IRQSTATEN_BGE		(0x00000004)
#define IRQSTATEN_TC		(0x00000002)
#define IRQSTATEN_CC		(0x00000001)

#define ESDHCCTL		0x0002e40c
#define ESDHCCTL_PCS		(0x00080000)

#define PRSSTAT			0x0002e024
#define PRSSTAT_DAT0		(0x01000000)
#define PRSSTAT_CLSL		(0x00800000)
#define PRSSTAT_WPSPL		(0x00080000)
#define PRSSTAT_CDPL		(0x00040000)
#define PRSSTAT_CINS		(0x00010000)
#define PRSSTAT_BREN		(0x00000800)
#define PRSSTAT_BWEN		(0x00000400)
#define PRSSTAT_SDSTB		(0X00000008)
#define PRSSTAT_DLA		(0x00000004)
#define PRSSTAT_CICHB		(0x00000002)
#define PRSSTAT_CIDHB		(0x00000001)

#define PROCTL			0x0002e028
#define PROCTL_INIT		0x00000020
#define PROCTL_DTW_4		0x00000002
#define PROCTL_DTW_8		0x00000004

#define CMDARG			0x0002e008

#define XFERTYP			0x0002e00c
#define XFERTYP_CMD(x)		((x & 0x3f) << 24)
#define XFERTYP_CMDTYP_NORMAL	0x0
#define XFERTYP_CMDTYP_SUSPEND	0x00400000
#define XFERTYP_CMDTYP_RESUME	0x00800000
#define XFERTYP_CMDTYP_ABORT	0x00c00000
#define XFERTYP_DPSEL		0x00200000
#define XFERTYP_CICEN		0x00100000
#define XFERTYP_CCCEN		0x00080000
#define XFERTYP_RSPTYP_NONE	0
#define XFERTYP_RSPTYP_136	0x00010000
#define XFERTYP_RSPTYP_48	0x00020000
#define XFERTYP_RSPTYP_48_BUSY	0x00030000
#define XFERTYP_MSBSEL		0x00000020
#define XFERTYP_DTDSEL		0x00000010
#define XFERTYP_DDREN		0x00000008
#define XFERTYP_AC12EN		0x00000004
#define XFERTYP_BCEN		0x00000002
#define XFERTYP_DMAEN		0x00000001

#define CINS_TIMEOUT		1000
#define PIO_TIMEOUT		500

#define DSADDR		0x2e004

#define CMDRSP0		0x2e010
#define CMDRSP1		0x2e014
#define CMDRSP2		0x2e018
#define CMDRSP3		0x2e01c

#define DATPORT		0x2e020

#define WML		0x2e044
#define WML_WRITE	0x00010000
#ifdef CONFIG_FSL_SDHC_V2_3
#define WML_RD_WML_MAX		0x80
#define WML_WR_WML_MAX		0x80
#define WML_RD_WML_MAX_VAL	0x0
#define WML_WR_WML_MAX_VAL	0x0
#define WML_RD_WML_MASK		0x7f
#define WML_WR_WML_MASK		0x7f0000
#else
#define WML_RD_WML_MAX		0x10
#define WML_WR_WML_MAX		0x80
#define WML_RD_WML_MAX_VAL	0x10
#define WML_WR_WML_MAX_VAL	0x80
#define WML_RD_WML_MASK	0xff
#define WML_WR_WML_MASK	0xff0000
#endif

#define BLKATTR		0x2e004
#define BLKATTR_CNT(x)	((x & 0xffff) << 16)
#define BLKATTR_SIZE(x)	(x & 0x1fff)
#define MAX_BLK_CNT	0x7fff	/* so malloc will have enough room with 32M */

#define ESDHC_HOSTCAPBLT_VS18	0x04000000
#define ESDHC_HOSTCAPBLT_VS30	0x02000000
#define ESDHC_HOSTCAPBLT_VS33	0x01000000
#define ESDHC_HOSTCAPBLT_SRS	0x00800000
#define ESDHC_HOSTCAPBLT_DMAS	0x00400000
#define ESDHC_HOSTCAPBLT_HSS	0x00200000

#define ESDHC_VENDORSPEC_VSELECT 0x00000002 /* Use 1.8V */

/* Imported from Linux Kernel drivers/mmc/host/sdhci-esdhc-imx.c */
#define	MIX_CTRL_DDREN		BIT(3)
#define MIX_CTRL_DTDSEL_READ	BIT(4)
#define	MIX_CTRL_AC23EN		BIT(7)
#define	MIX_CTRL_EXE_TUNE	BIT(22)
#define	MIX_CTRL_SMPCLK_SEL	BIT(23)
#define	MIX_CTRL_AUTO_TUNE_EN	BIT(24)
#define	MIX_CTRL_FBCLK_SEL	BIT(25)
#define	MIX_CTRL_HS400_EN	BIT(26)
#define	MIX_CTRL_HS400_ES	BIT(27)
/* Bits 3 and 6 are not SDHCI standard definitions */
#define	MIX_CTRL_SDHCI_MASK	0xb7
/* Tuning bits */
#define	MIX_CTRL_TUNING_MASK	0x03c00000

/* strobe dll register */
#define ESDHC_STROBE_DLL_CTRL		0x70
#define ESDHC_STROBE_DLL_CTRL_ENABLE	BIT(0)
#define ESDHC_STROBE_DLL_CTRL_RESET	BIT(1)
#define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT	0x7
#define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT	3

#define ESDHC_STROBE_DLL_STATUS		0x74
#define ESDHC_STROBE_DLL_STS_REF_LOCK	BIT(1)
#define ESDHC_STROBE_DLL_STS_SLV_LOCK	0x1
#define ESDHC_STROBE_DLL_CLK_FREQ	100000000

#define ESDHC_STD_TUNING_EN             BIT(24)
/* NOTE: the minimum valid tuning start tap for mx6sl is 1 */
#define ESDHC_TUNING_START_TAP_DEFAULT	0x1
#define ESDHC_TUNING_START_TAP_MASK	0xff
#define ESDHC_TUNING_STEP_MASK		0x00070000
#define ESDHC_TUNING_STEP_SHIFT		16

#define	ESDHC_FLAG_MULTIBLK_NO_INT	BIT(1)
#define	ESDHC_FLAG_ENGCM07207		BIT(2)
#define	ESDHC_FLAG_USDHC		BIT(3)
#define	ESDHC_FLAG_MAN_TUNING		BIT(4)
#define	ESDHC_FLAG_STD_TUNING		BIT(5)
#define	ESDHC_FLAG_HAVE_CAP1		BIT(6)
#define	ESDHC_FLAG_ERR004536		BIT(7)
#define	ESDHC_FLAG_HS200		BIT(8)
#define	ESDHC_FLAG_HS400		BIT(9)
#define	ESDHC_FLAG_ERR010450		BIT(10)
#define	ESDHC_FLAG_HS400_ES		BIT(11)

struct fsl_esdhc_cfg {
	phys_addr_t esdhc_base;
	u32	sdhc_clk;
	u8	max_bus_width;
	int	wp_enable;
	int	vs18_enable; /* Use 1.8V if set to 1 */
	struct mmc_config cfg;
};

/* Select the correct accessors depending on endianess */
#if defined CONFIG_SYS_FSL_ESDHC_LE
#define esdhc_read32		in_le32
#define esdhc_write32		out_le32
#define esdhc_clrsetbits32	clrsetbits_le32
#define esdhc_clrbits32		clrbits_le32
#define esdhc_setbits32		setbits_le32
#elif defined(CONFIG_SYS_FSL_ESDHC_BE)
#define esdhc_read32            in_be32
#define esdhc_write32           out_be32
#define esdhc_clrsetbits32      clrsetbits_be32
#define esdhc_clrbits32         clrbits_be32
#define esdhc_setbits32         setbits_be32
#elif __BYTE_ORDER == __LITTLE_ENDIAN
#define esdhc_read32		in_le32
#define esdhc_write32		out_le32
#define esdhc_clrsetbits32	clrsetbits_le32
#define esdhc_clrbits32		clrbits_le32
#define esdhc_setbits32		setbits_le32
#elif __BYTE_ORDER == __BIG_ENDIAN
#define esdhc_read32		in_be32
#define esdhc_write32		out_be32
#define esdhc_clrsetbits32	clrsetbits_be32
#define esdhc_clrbits32		clrbits_be32
#define esdhc_setbits32		setbits_be32
#else
#error "Endianess is not defined: please fix to continue"
#endif

#ifdef CONFIG_FSL_ESDHC
int fsl_esdhc_mmc_init(bd_t *bis);
int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg);
void fdt_fixup_esdhc(void *blob, bd_t *bd);
#else
static inline int fsl_esdhc_mmc_init(bd_t *bis) { return -ENOSYS; }
static inline void fdt_fixup_esdhc(void *blob, bd_t *bd) {}
#endif /* CONFIG_FSL_ESDHC */
void __noreturn mmc_boot(void);
void mmc_spl_load_image(uint32_t offs, unsigned int size, void *vdst);

#endif  /* __FSL_ESDHC_H__ */
Commit	Line	Data
50586ef2 AF	1	/*
	2	* FSL SD/MMC Defines
	3	*-------------------------------------------------------------------
	4	*
32c8cfb2	5	* Copyright 2007-2008,2010-2011 Freescale Semiconductor, Inc
50586ef2	6	*
1a459660	7	* SPDX-License-Identifier: GPL-2.0+
50586ef2 AF	8	*/
	9
	10	#ifndef __FSL_ESDHC_H__
	11	#define __FSL_ESDHC_H__
	12
51313b49	13	#include <linux/bitops.h>
1221ce45	14	#include <linux/errno.h>
c67bee14	15	#include <asm/byteorder.h>
b33433a6	16
93bfd616 PA	17	/* needed for the mmc_cfg definition */
	18	#include <mmc.h>
	19
5a8dbdc6 YL	20	#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
	21	#include "../board/freescale/common/qixis.h"
	22	#endif
	23
50586ef2 AF	24	/* FSL eSDHC-specific constants */
	25	#define SYSCTL 0x0002e02c
	26	#define SYSCTL_INITA 0x08000000
	27	#define SYSCTL_TIMEOUT_MASK 0x000f0000
1118cdbf	28	#define SYSCTL_CLOCK_MASK 0x0000fff0
f0b5f23f	29	#if !defined(CONFIG_FSL_USDHC)
c67bee14	30	#define SYSCTL_CKEN 0x00000008
50586ef2 AF	31	#define SYSCTL_PEREN 0x00000004
	32	#define SYSCTL_HCKEN 0x00000002
	33	#define SYSCTL_IPGEN 0x00000001
f0b5f23f	34	#endif
48bb3bb5	35	#define SYSCTL_RSTA 0x01000000
7a5b8029 DB	36	#define SYSCTL_RSTC 0x02000000
7a5b8029 DB	37	#define SYSCTL_RSTD 0x04000000
50586ef2	38
f53225cc PF	39	#define VENDORSPEC_CKEN 0x00004000
	40	#define VENDORSPEC_PEREN 0x00002000
	41	#define VENDORSPEC_HCKEN 0x00001000
	42	#define VENDORSPEC_IPGEN 0x00000800
	43	#define VENDORSPEC_INIT 0x20007809
	44
50586ef2 AF	45	#define IRQSTAT 0x0002e030
	46	#define IRQSTAT_DMAE (0x10000000)
	47	#define IRQSTAT_AC12E (0x01000000)
	48	#define IRQSTAT_DEBE (0x00400000)
	49	#define IRQSTAT_DCE (0x00200000)
	50	#define IRQSTAT_DTOE (0x00100000)
	51	#define IRQSTAT_CIE (0x00080000)
	52	#define IRQSTAT_CEBE (0x00040000)
	53	#define IRQSTAT_CCE (0x00020000)
	54	#define IRQSTAT_CTOE (0x00010000)
	55	#define IRQSTAT_CINT (0x00000100)
	56	#define IRQSTAT_CRM (0x00000080)
	57	#define IRQSTAT_CINS (0x00000040)
	58	#define IRQSTAT_BRR (0x00000020)
	59	#define IRQSTAT_BWR (0x00000010)
	60	#define IRQSTAT_DINT (0x00000008)
	61	#define IRQSTAT_BGE (0x00000004)
	62	#define IRQSTAT_TC (0x00000002)
	63	#define IRQSTAT_CC (0x00000001)
	64
	65	#define CMD_ERR (IRQSTAT_CIE \| IRQSTAT_CEBE \| IRQSTAT_CCE)
9b74dc56 AG	66	#define DATA_ERR (IRQSTAT_DEBE \| IRQSTAT_DCE \| IRQSTAT_DTOE \| \
	67	IRQSTAT_DMAE)
	68	#define DATA_COMPLETE (IRQSTAT_TC \| IRQSTAT_DINT)
50586ef2 AF	69
	70	#define IRQSTATEN 0x0002e034
	71	#define IRQSTATEN_DMAE (0x10000000)
	72	#define IRQSTATEN_AC12E (0x01000000)
	73	#define IRQSTATEN_DEBE (0x00400000)
	74	#define IRQSTATEN_DCE (0x00200000)
	75	#define IRQSTATEN_DTOE (0x00100000)
	76	#define IRQSTATEN_CIE (0x00080000)
	77	#define IRQSTATEN_CEBE (0x00040000)
	78	#define IRQSTATEN_CCE (0x00020000)
	79	#define IRQSTATEN_CTOE (0x00010000)
	80	#define IRQSTATEN_CINT (0x00000100)
	81	#define IRQSTATEN_CRM (0x00000080)
	82	#define IRQSTATEN_CINS (0x00000040)
	83	#define IRQSTATEN_BRR (0x00000020)
	84	#define IRQSTATEN_BWR (0x00000010)
	85	#define IRQSTATEN_DINT (0x00000008)
	86	#define IRQSTATEN_BGE (0x00000004)
	87	#define IRQSTATEN_TC (0x00000002)
	88	#define IRQSTATEN_CC (0x00000001)
	89
2d9ca2c7 YL	90	#define ESDHCCTL 0x0002e40c
	91	#define ESDHCCTL_PCS (0x00080000)
	92
50586ef2	93	#define PRSSTAT 0x0002e024
7a5b8029	94	#define PRSSTAT_DAT0 (0x01000000)
50586ef2 AF	95	#define PRSSTAT_CLSL (0x00800000)
	96	#define PRSSTAT_WPSPL (0x00080000)
	97	#define PRSSTAT_CDPL (0x00040000)
	98	#define PRSSTAT_CINS (0x00010000)
	99	#define PRSSTAT_BREN (0x00000800)
77c1458d	100	#define PRSSTAT_BWEN (0x00000400)
2d9ca2c7	101	#define PRSSTAT_SDSTB (0X00000008)
50586ef2 AF	102	#define PRSSTAT_DLA (0x00000004)
	103	#define PRSSTAT_CICHB (0x00000002)
	104	#define PRSSTAT_CIDHB (0x00000001)
	105
	106	#define PROCTL 0x0002e028
	107	#define PROCTL_INIT 0x00000020
	108	#define PROCTL_DTW_4 0x00000002
	109	#define PROCTL_DTW_8 0x00000004
	110
	111	#define CMDARG 0x0002e008
	112
	113	#define XFERTYP 0x0002e00c
	114	#define XFERTYP_CMD(x) ((x & 0x3f) << 24)
	115	#define XFERTYP_CMDTYP_NORMAL 0x0
	116	#define XFERTYP_CMDTYP_SUSPEND 0x00400000
	117	#define XFERTYP_CMDTYP_RESUME 0x00800000
	118	#define XFERTYP_CMDTYP_ABORT 0x00c00000
	119	#define XFERTYP_DPSEL 0x00200000
	120	#define XFERTYP_CICEN 0x00100000
	121	#define XFERTYP_CCCEN 0x00080000
	122	#define XFERTYP_RSPTYP_NONE 0
	123	#define XFERTYP_RSPTYP_136 0x00010000
	124	#define XFERTYP_RSPTYP_48 0x00020000
	125	#define XFERTYP_RSPTYP_48_BUSY 0x00030000
	126	#define XFERTYP_MSBSEL 0x00000020
	127	#define XFERTYP_DTDSEL 0x00000010
0e1bf614	128	#define XFERTYP_DDREN 0x00000008
50586ef2 AF	129	#define XFERTYP_AC12EN 0x00000004
	130	#define XFERTYP_BCEN 0x00000002
	131	#define XFERTYP_DMAEN 0x00000001
	132
	133	#define CINS_TIMEOUT 1000
bcfb3653	134	#define PIO_TIMEOUT 500
50586ef2 AF	135
	136	#define DSADDR 0x2e004
	137
	138	#define CMDRSP0 0x2e010
	139	#define CMDRSP1 0x2e014
	140	#define CMDRSP2 0x2e018
	141	#define CMDRSP3 0x2e01c
	142
	143	#define DATPORT 0x2e020
	144
	145	#define WML 0x2e044
	146	#define WML_WRITE 0x00010000
32c8cfb2 PJ	147	#ifdef CONFIG_FSL_SDHC_V2_3
	148	#define WML_RD_WML_MAX 0x80
	149	#define WML_WR_WML_MAX 0x80
	150	#define WML_RD_WML_MAX_VAL 0x0
	151	#define WML_WR_WML_MAX_VAL 0x0
	152	#define WML_RD_WML_MASK 0x7f
	153	#define WML_WR_WML_MASK 0x7f0000
	154	#else
	155	#define WML_RD_WML_MAX 0x10
	156	#define WML_WR_WML_MAX 0x80
	157	#define WML_RD_WML_MAX_VAL 0x10
	158	#define WML_WR_WML_MAX_VAL 0x80
ab467c51 RZ	159	#define WML_RD_WML_MASK 0xff
ab467c51 RZ	160	#define WML_WR_WML_MASK 0xff0000
32c8cfb2	161	#endif
50586ef2 AF	162
	163	#define BLKATTR 0x2e004
	164	#define BLKATTR_CNT(x) ((x & 0xffff) << 16)
	165	#define BLKATTR_SIZE(x) (x & 0x1fff)
	166	#define MAX_BLK_CNT 0x7fff /* so malloc will have enough room with 32M */
	167
	168	#define ESDHC_HOSTCAPBLT_VS18 0x04000000
	169	#define ESDHC_HOSTCAPBLT_VS30 0x02000000
	170	#define ESDHC_HOSTCAPBLT_VS33 0x01000000
	171	#define ESDHC_HOSTCAPBLT_SRS 0x00800000
	172	#define ESDHC_HOSTCAPBLT_DMAS 0x00400000
	173	#define ESDHC_HOSTCAPBLT_HSS 0x00200000
	174
f022d36e OS	175	#define ESDHC_VENDORSPEC_VSELECT 0x00000002 /* Use 1.8V */
f022d36e OS	176
51313b49 PF	177	/* Imported from Linux Kernel drivers/mmc/host/sdhci-esdhc-imx.c */
	178	#define MIX_CTRL_DDREN BIT(3)
	179	#define MIX_CTRL_DTDSEL_READ BIT(4)
	180	#define MIX_CTRL_AC23EN BIT(7)
	181	#define MIX_CTRL_EXE_TUNE BIT(22)
	182	#define MIX_CTRL_SMPCLK_SEL BIT(23)
	183	#define MIX_CTRL_AUTO_TUNE_EN BIT(24)
	184	#define MIX_CTRL_FBCLK_SEL BIT(25)
	185	#define MIX_CTRL_HS400_EN BIT(26)
	186	#define MIX_CTRL_HS400_ES BIT(27)
	187	/* Bits 3 and 6 are not SDHCI standard definitions */
	188	#define MIX_CTRL_SDHCI_MASK 0xb7
	189	/* Tuning bits */
	190	#define MIX_CTRL_TUNING_MASK 0x03c00000
	191
	192	/* strobe dll register */
	193	#define ESDHC_STROBE_DLL_CTRL 0x70
	194	#define ESDHC_STROBE_DLL_CTRL_ENABLE BIT(0)
	195	#define ESDHC_STROBE_DLL_CTRL_RESET BIT(1)
	196	#define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT 0x7
	197	#define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT 3
	198
	199	#define ESDHC_STROBE_DLL_STATUS 0x74
	200	#define ESDHC_STROBE_DLL_STS_REF_LOCK BIT(1)
	201	#define ESDHC_STROBE_DLL_STS_SLV_LOCK 0x1
	202	#define ESDHC_STROBE_DLL_CLK_FREQ 100000000
	203
	204	#define ESDHC_STD_TUNING_EN BIT(24)
	205	/* NOTE: the minimum valid tuning start tap for mx6sl is 1 */
	206	#define ESDHC_TUNING_START_TAP_DEFAULT 0x1
	207	#define ESDHC_TUNING_START_TAP_MASK 0xff
	208	#define ESDHC_TUNING_STEP_MASK 0x00070000
	209	#define ESDHC_TUNING_STEP_SHIFT 16
	210
	211	#define ESDHC_FLAG_MULTIBLK_NO_INT BIT(1)
	212	#define ESDHC_FLAG_ENGCM07207 BIT(2)
	213	#define ESDHC_FLAG_USDHC BIT(3)
	214	#define ESDHC_FLAG_MAN_TUNING BIT(4)
	215	#define ESDHC_FLAG_STD_TUNING BIT(5)
	216	#define ESDHC_FLAG_HAVE_CAP1 BIT(6)
	217	#define ESDHC_FLAG_ERR004536 BIT(7)
	218	#define ESDHC_FLAG_HS200 BIT(8)
	219	#define ESDHC_FLAG_HS400 BIT(9)
	220	#define ESDHC_FLAG_ERR010450 BIT(10)
	221	#define ESDHC_FLAG_HS400_ES BIT(11)
	222
c67bee14	223	struct fsl_esdhc_cfg {
5330c7d7	224	phys_addr_t esdhc_base;
a2ac1b3a	225	u32 sdhc_clk;
aad4659a	226	u8 max_bus_width;
15a91651	227	int wp_enable;
32a9179f	228	int vs18_enable; /* Use 1.8V if set to 1 */
93bfd616	229	struct mmc_config cfg;
c67bee14 SB	230	};
	231
	232	/* Select the correct accessors depending on endianess */
c82e9de4 WH	233	#if defined CONFIG_SYS_FSL_ESDHC_LE
	234	#define esdhc_read32 in_le32
	235	#define esdhc_write32 out_le32
	236	#define esdhc_clrsetbits32 clrsetbits_le32
	237	#define esdhc_clrbits32 clrbits_le32
	238	#define esdhc_setbits32 setbits_le32
	239	#elif defined(CONFIG_SYS_FSL_ESDHC_BE)
	240	#define esdhc_read32 in_be32
	241	#define esdhc_write32 out_be32
	242	#define esdhc_clrsetbits32 clrsetbits_be32
	243	#define esdhc_clrbits32 clrbits_be32
	244	#define esdhc_setbits32 setbits_be32
	245	#elif __BYTE_ORDER == __LITTLE_ENDIAN
c67bee14 SB	246	#define esdhc_read32 in_le32
	247	#define esdhc_write32 out_le32
	248	#define esdhc_clrsetbits32 clrsetbits_le32
	249	#define esdhc_clrbits32 clrbits_le32
	250	#define esdhc_setbits32 setbits_le32
	251	#elif __BYTE_ORDER == __BIG_ENDIAN
	252	#define esdhc_read32 in_be32
	253	#define esdhc_write32 out_be32
	254	#define esdhc_clrsetbits32 clrsetbits_be32
	255	#define esdhc_clrbits32 clrbits_be32
	256	#define esdhc_setbits32 setbits_be32
	257	#else
	258	#error "Endianess is not defined: please fix to continue"
	259	#endif
	260
b33433a6	261	#ifdef CONFIG_FSL_ESDHC
50586ef2	262	int fsl_esdhc_mmc_init(bd_t *bis);
c67bee14	263	int fsl_esdhc_initialize(bd_t bis, struct fsl_esdhc_cfg cfg);
b33433a6 AV	264	void fdt_fixup_esdhc(void blob, bd_t bd);
	265	#else
	266	static inline int fsl_esdhc_mmc_init(bd_t *bis) { return -ENOSYS; }
	267	static inline void fdt_fixup_esdhc(void blob, bd_t bd) {}
	268	#endif /* CONFIG_FSL_ESDHC */
bb0dc108	269	void __noreturn mmc_boot(void);
1eaa742d	270	void mmc_spl_load_image(uint32_t offs, unsigned int size, void *vdst);
50586ef2 AF	271
50586ef2 AF	272	#endif /* __FSL_ESDHC_H__ */