[people/ms/u-boot.git] / include / fsl_sec.h

/*
 * Common internal memory map for some Freescale SoCs
 *
 * Copyright 2014 Freescale Semiconductor, Inc.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __FSL_SEC_H
#define __FSL_SEC_H

#include <common.h>
#include <asm/io.h>

#ifdef CONFIG_SYS_FSL_SEC_LE
#define sec_in32(a)       in_le32(a)
#define sec_out32(a, v)   out_le32(a, v)
#define sec_in16(a)       in_le16(a)
#define sec_clrbits32     clrbits_le32
#define sec_setbits32     setbits_le32
#elif defined(CONFIG_SYS_FSL_SEC_BE)
#define sec_in32(a)       in_be32(a)
#define sec_out32(a, v)   out_be32(a, v)
#define sec_in16(a)       in_be16(a)
#define sec_clrbits32     clrbits_be32
#define sec_setbits32     setbits_be32
#elif defined(CONFIG_SYS_FSL_HAS_SEC)
#error Neither CONFIG_SYS_FSL_SEC_LE nor CONFIG_SYS_FSL_SEC_BE is defined
#endif

/* Security Engine Block (MS = Most Sig., LS = Least Sig.) */
#if CONFIG_SYS_FSL_SEC_COMPAT >= 4
/* RNG4 TRNG test registers */
struct rng4tst {
#define RTMCTL_PRGM 0x00010000	/* 1 -> program mode, 0 -> run mode */
#define RTMCTL_SAMP_MODE_VON_NEUMANN_ES_SC     0 /* use von Neumann data in
						    both entropy shifter and
						    statistical checker */
#define RTMCTL_SAMP_MODE_RAW_ES_SC             1 /* use raw data in both
						    entropy shifter and
						    statistical checker */
#define RTMCTL_SAMP_MODE_VON_NEUMANN_ES_RAW_SC 2 /* use von Neumann data in
						    entropy shifter, raw data
						    in statistical checker */
#define RTMCTL_SAMP_MODE_INVALID               3 /* invalid combination */
	u32 rtmctl;		/* misc. control register */
	u32 rtscmisc;		/* statistical check misc. register */
	u32 rtpkrrng;		/* poker range register */
#define RTSDCTL_ENT_DLY_MIN	3200
#define RTSDCTL_ENT_DLY_MAX	12800
	union {
		u32 rtpkrmax;	/* PRGM=1: poker max. limit register */
		u32 rtpkrsq;	/* PRGM=0: poker square calc. result register */
	};
#define RTSDCTL_ENT_DLY_SHIFT 16
#define RTSDCTL_ENT_DLY_MASK (0xffff << RTSDCTL_ENT_DLY_SHIFT)
	u32 rtsdctl;		/* seed control register */
	union {
		u32 rtsblim;	/* PRGM=1: sparse bit limit register */
		u32 rttotsam;	/* PRGM=0: total samples register */
	};
	u32 rtfreqmin;		/* frequency count min. limit register */
#define RTFRQMAX_DISABLE       (1 << 20)
	union {
		u32 rtfreqmax;	/* PRGM=1: freq. count max. limit register */
		u32 rtfreqcnt;	/* PRGM=0: freq. count register */
	};
	u32 rsvd1[40];
#define RNG_STATE0_HANDLE_INSTANTIATED	0x00000001
#define RNG_STATE1_HANDLE_INSTANTIATED	0x00000002
#define RNG_STATE_HANDLE_MASK	\
	(RNG_STATE0_HANDLE_INSTANTIATED | RNG_STATE1_HANDLE_INSTANTIATED)
	u32 rdsta;		/*RNG DRNG Status Register*/
	u32 rsvd2[15];
};

typedef struct ccsr_sec {
	u32	res0;
	u32	mcfgr;		/* Master CFG Register */
	u8	res1[0x4];
	u32	scfgr;
	struct {
		u32	ms;	/* Job Ring LIODN Register, MS */
		u32	ls;	/* Job Ring LIODN Register, LS */
	} jrliodnr[4];
	u8	res2[0x2c];
	u32	jrstartr;	/* Job Ring Start Register */
	struct {
		u32	ms;	/* RTIC LIODN Register, MS */
		u32	ls;	/* RTIC LIODN Register, LS */
	} rticliodnr[4];
	u8	res3[0x1c];
	u32	decorr;		/* DECO Request Register */
	struct {
		u32	ms;	/* DECO LIODN Register, MS */
		u32	ls;	/* DECO LIODN Register, LS */
	} decoliodnr[8];
	u8	res4[0x40];
	u32	dar;		/* DECO Avail Register */
	u32	drr;		/* DECO Reset Register */
	u8	res5[0x4d8];
	struct rng4tst rng;	/* RNG Registers */
	u8	res6[0x8a0];
	u32	crnr_ms;	/* CHA Revision Number Register, MS */
	u32	crnr_ls;	/* CHA Revision Number Register, LS */
	u32	ctpr_ms;	/* Compile Time Parameters Register, MS */
	u32	ctpr_ls;	/* Compile Time Parameters Register, LS */
	u8	res7[0x10];
	u32	far_ms;		/* Fault Address Register, MS */
	u32	far_ls;		/* Fault Address Register, LS */
	u32	falr;		/* Fault Address LIODN Register */
	u32	fadr;		/* Fault Address Detail Register */
	u8	res8[0x4];
	u32	csta;		/* CAAM Status Register */
	u32	smpart;		/* Secure Memory Partition Parameters */
	u32	smvid;		/* Secure Memory Version ID */
	u32	rvid;		/* Run Time Integrity Checking Version ID Reg.*/
	u32	ccbvid;		/* CHA Cluster Block Version ID Register */
	u32	chavid_ms;	/* CHA Version ID Register, MS */
	u32	chavid_ls;	/* CHA Version ID Register, LS */
	u32	chanum_ms;	/* CHA Number Register, MS */
	u32	chanum_ls;	/* CHA Number Register, LS */
	u32	secvid_ms;	/* SEC Version ID Register, MS */
	u32	secvid_ls;	/* SEC Version ID Register, LS */
	u8	res9[0x6020];
	u32	qilcr_ms;	/* Queue Interface LIODN CFG Register, MS */
	u32	qilcr_ls;	/* Queue Interface LIODN CFG Register, LS */
	u8	res10[0x8fd8];
} ccsr_sec_t;

#define SEC_CTPR_MS_AXI_LIODN		0x08000000
#define SEC_CTPR_MS_QI			0x02000000
#define SEC_CTPR_MS_VIRT_EN_INCL	0x00000001
#define SEC_CTPR_MS_VIRT_EN_POR		0x00000002
#define SEC_RVID_MA			0x0f000000
#define SEC_CHANUM_MS_JRNUM_MASK	0xf0000000
#define SEC_CHANUM_MS_JRNUM_SHIFT	28
#define SEC_CHANUM_MS_DECONUM_MASK	0x0f000000
#define SEC_CHANUM_MS_DECONUM_SHIFT	24
#define SEC_SECVID_MS_IPID_MASK	0xffff0000
#define SEC_SECVID_MS_IPID_SHIFT	16
#define SEC_SECVID_MS_MAJ_REV_MASK	0x0000ff00
#define SEC_SECVID_MS_MAJ_REV_SHIFT	8
#define SEC_CCBVID_ERA_MASK		0xff000000
#define SEC_CCBVID_ERA_SHIFT		24
#define SEC_SCFGR_RDBENABLE		0x00000400
#define SEC_SCFGR_VIRT_EN		0x00008000
#define SEC_CHAVID_LS_RNG_SHIFT		16
#define SEC_CHAVID_RNG_LS_MASK		0x000f0000

#define CONFIG_JRSTARTR_JR0		0x00000001

struct jr_regs {
#if defined(CONFIG_SYS_FSL_SEC_LE) && \
	!(defined(CONFIG_MX6) || defined(CONFIG_MX7))
	u32 irba_l;
	u32 irba_h;
#else
	u32 irba_h;
	u32 irba_l;
#endif
	u32 rsvd1;
	u32 irs;
	u32 rsvd2;
	u32 irsa;
	u32 rsvd3;
	u32 irja;
#if defined(CONFIG_SYS_FSL_SEC_LE) && \
	!(defined(CONFIG_MX6) || defined(CONFIG_MX7))
	u32 orba_l;
	u32 orba_h;
#else
	u32 orba_h;
	u32 orba_l;
#endif
	u32 rsvd4;
	u32 ors;
	u32 rsvd5;
	u32 orjr;
	u32 rsvd6;
	u32 orsf;
	u32 rsvd7;
	u32 jrsta;
	u32 rsvd8;
	u32 jrint;
	u32 jrcfg0;
	u32 jrcfg1;
	u32 rsvd9;
	u32 irri;
	u32 rsvd10;
	u32 orwi;
	u32 rsvd11;
	u32 jrcr;
};

/*
 * Scatter Gather Entry - Specifies the the Scatter Gather Format
 * related information
 */
struct sg_entry {
#if defined(CONFIG_SYS_FSL_SEC_LE) && \
	!(defined(CONFIG_MX6) || defined(CONFIG_MX7))
	uint32_t addr_lo;	/* Memory Address - lo */
	uint32_t addr_hi;	/* Memory Address of start of buffer - hi */
#else
	uint32_t addr_hi;	/* Memory Address of start of buffer - hi */
	uint32_t addr_lo;	/* Memory Address - lo */
#endif

	uint32_t len_flag;	/* Length of the data in the frame */
#define SG_ENTRY_LENGTH_MASK	0x3FFFFFFF
#define SG_ENTRY_EXTENSION_BIT	0x80000000
#define SG_ENTRY_FINAL_BIT	0x40000000
	uint32_t bpid_offset;
#define SG_ENTRY_BPID_MASK	0x00FF0000
#define SG_ENTRY_BPID_SHIFT	16
#define SG_ENTRY_OFFSET_MASK	0x00001FFF
#define SG_ENTRY_OFFSET_SHIFT	0
};

#define BLOB_SIZE(x)		((x) + 32 + 16) /* Blob buffer size */

#if defined(CONFIG_MX6) || defined(CONFIG_MX7)
/* Job Ring Base Address */
#define JR_BASE_ADDR(x) (CONFIG_SYS_FSL_SEC_ADDR + 0x1000 * (x + 1))
/* Secure Memory Offset varies accross versions */
#define SM_V1_OFFSET 0x0f4
#define SM_V2_OFFSET 0xa00
/*Secure Memory Versioning */
#define SMVID_V2 0x20105
#define SM_VERSION(x)  (x < SMVID_V2 ? 1 : 2)
#define SM_OFFSET(x)  (x == 1 ? SM_V1_OFFSET : SM_V2_OFFSET)
/* CAAM Job Ring 0 Registers */
/* Secure Memory Partition Owner register */
#define SMCSJR_PO		(3 << 6)
/* JR Allocation Error */
#define SMCSJR_AERR		(3 << 12)
/* Secure memory partition 0 page 0 owner register */
#define CAAM_SMPO_0	    (CONFIG_SYS_FSL_SEC_ADDR + 0x1FBC)
/* Secure memory command register */
#define CAAM_SMCJR(v, jr)   (JR_BASE_ADDR(jr) + SM_OFFSET(v) + SM_CMD(v))
/* Secure memory command status register */
#define CAAM_SMCSJR(v, jr)  (JR_BASE_ADDR(jr) + SM_OFFSET(v) + SM_STATUS(v))
/* Secure memory access permissions register */
#define CAAM_SMAPJR(v, jr, y) \
	(JR_BASE_ADDR(jr) + SM_OFFSET(v) + SM_PERM(v) + y * 16)
/* Secure memory access group 2 register */
#define CAAM_SMAG2JR(v, jr, y) \
	(JR_BASE_ADDR(jr) + SM_OFFSET(v) + SM_GROUP2(v) + y * 16)
/* Secure memory access group 1 register */
#define CAAM_SMAG1JR(v, jr, y)  \
	(JR_BASE_ADDR(jr) + SM_OFFSET(v) + SM_GROUP1(v) + y * 16)

/* Commands and macros for secure memory */
#define SM_CMD(v)		(v == 1 ? 0x0 : 0x1E4)
#define SM_STATUS(v)		(v == 1 ? 0x8 : 0x1EC)
#define SM_PERM(v)		(v == 1 ?  0x10 : 0x4)
#define SM_GROUP2(v)		(v == 1 ? 0x14 : 0x8)
#define SM_GROUP1(v)		(v == 1 ? 0x18 : 0xC)
#define CMD_PAGE_ALLOC		0x1
#define CMD_PAGE_DEALLOC	0x2
#define CMD_PART_DEALLOC	0x3
#define CMD_INQUIRY		0x5
#define CMD_COMPLETE		(3 << 14)
#define PAGE_AVAILABLE		0
#define PAGE_OWNED		(3 << 6)
#define PAGE(x)			(x << 16)
#define PARTITION(x)		(x << 8)
#define PARTITION_OWNER(x)	(0x3 << (x*2))

/* Address of secure 4kbyte pages */
#define SEC_MEM_PAGE0		CAAM_ARB_BASE_ADDR
#define SEC_MEM_PAGE1		(CAAM_ARB_BASE_ADDR + 0x1000)
#define SEC_MEM_PAGE2		(CAAM_ARB_BASE_ADDR + 0x2000)
#define SEC_MEM_PAGE3		(CAAM_ARB_BASE_ADDR + 0x3000)

#define JR_MID			2               /* Matches ROM configuration */
#define KS_G1			(1 << JR_MID)   /* CAAM only */
#define PERM			0x0000B008      /* Clear on release, lock SMAP
						 * lock SMAG group 1 Blob */

/* HAB WRAPPED KEY header */
#define WRP_HDR_SIZE		0x08
#define HDR_TAG			0x81
#define HDR_PAR			0x41
/* HAB WRAPPED KEY Data */
#define HAB_MOD			0x66
#define HAB_ALG			0x55
#define HAB_FLG			0x00

/* Partition and Page IDs */
#define PARTITION_1	1
#define PAGE_1			1

#define ERROR_IN_PAGE_ALLOC	1
#define ECONSTRJDESC   -1

#endif

/* blob_dek:
 * Encapsulates the src in a secure blob and stores it dst
 * @src: reference to the plaintext
 * @dst: reference to the output adrress
 * @len: size in bytes of src
 * @return: 0 on success, error otherwise
 */
int blob_dek(const u8 *src, u8 *dst, u8 len);

#if defined(CONFIG_ARCH_C29X)
int sec_init_idx(uint8_t);
#endif
int sec_init(void);
#endif

#endif /* __FSL_SEC_H */
Commit	Line	Data
48ef0d2a RG	1	/*
	2	* Common internal memory map for some Freescale SoCs
	3	*
	4	* Copyright 2014 Freescale Semiconductor, Inc.
	5	*
057c2200	6	* SPDX-License-Identifier: GPL-2.0+
48ef0d2a RG	7	*/
	8
	9	#ifndef __FSL_SEC_H
	10	#define __FSL_SEC_H
	11
	12	#include <common.h>
	13	#include <asm/io.h>
	14
028dbb8d RG	15	#ifdef CONFIG_SYS_FSL_SEC_LE
	16	#define sec_in32(a) in_le32(a)
	17	#define sec_out32(a, v) out_le32(a, v)
	18	#define sec_in16(a) in_le16(a)
	19	#define sec_clrbits32 clrbits_le32
	20	#define sec_setbits32 setbits_le32
	21	#elif defined(CONFIG_SYS_FSL_SEC_BE)
	22	#define sec_in32(a) in_be32(a)
	23	#define sec_out32(a, v) out_be32(a, v)
	24	#define sec_in16(a) in_be16(a)
	25	#define sec_clrbits32 clrbits_be32
	26	#define sec_setbits32 setbits_be32
90b80386	27	#elif defined(CONFIG_SYS_FSL_HAS_SEC)
028dbb8d RG	28	#error Neither CONFIG_SYS_FSL_SEC_LE nor CONFIG_SYS_FSL_SEC_BE is defined
	29	#endif
	30
48ef0d2a RG	31	/* Security Engine Block (MS = Most Sig., LS = Least Sig.) */
48ef0d2a RG	32	#if CONFIG_SYS_FSL_SEC_COMPAT >= 4
c5de15cb RG	33	/* RNG4 TRNG test registers */
	34	struct rng4tst {
	35	#define RTMCTL_PRGM 0x00010000 /* 1 -> program mode, 0 -> run mode */
c4065517 AP	36	#define RTMCTL_SAMP_MODE_VON_NEUMANN_ES_SC 0 /* use von Neumann data in
	37	both entropy shifter and
	38	statistical checker */
	39	#define RTMCTL_SAMP_MODE_RAW_ES_SC 1 /* use raw data in both
	40	entropy shifter and
	41	statistical checker */
	42	#define RTMCTL_SAMP_MODE_VON_NEUMANN_ES_RAW_SC 2 /* use von Neumann data in
	43	entropy shifter, raw data
	44	in statistical checker */
	45	#define RTMCTL_SAMP_MODE_INVALID 3 /* invalid combination */
c5de15cb RG	46	u32 rtmctl; /* misc. control register */
	47	u32 rtscmisc; /* statistical check misc. register */
	48	u32 rtpkrrng; /* poker range register */
17649e1b	49	#define RTSDCTL_ENT_DLY_MIN 3200
c5de15cb RG	50	#define RTSDCTL_ENT_DLY_MAX 12800
	51	union {
	52	u32 rtpkrmax; /* PRGM=1: poker max. limit register */
	53	u32 rtpkrsq; /* PRGM=0: poker square calc. result register */
	54	};
	55	#define RTSDCTL_ENT_DLY_SHIFT 16
	56	#define RTSDCTL_ENT_DLY_MASK (0xffff << RTSDCTL_ENT_DLY_SHIFT)
	57	u32 rtsdctl; /* seed control register */
	58	union {
	59	u32 rtsblim; /* PRGM=1: sparse bit limit register */
	60	u32 rttotsam; /* PRGM=0: total samples register */
	61	};
	62	u32 rtfreqmin; /* frequency count min. limit register */
026a3f1b	63	#define RTFRQMAX_DISABLE (1 << 20)
c5de15cb RG	64	union {
	65	u32 rtfreqmax; /* PRGM=1: freq. count max. limit register */
	66	u32 rtfreqcnt; /* PRGM=0: freq. count register */
	67	};
	68	u32 rsvd1[40];
	69	#define RNG_STATE0_HANDLE_INSTANTIATED 0x00000001
dfaec760 LA	70	#define RNG_STATE1_HANDLE_INSTANTIATED 0x00000002
	71	#define RNG_STATE_HANDLE_MASK \
	72	(RNG_STATE0_HANDLE_INSTANTIATED \| RNG_STATE1_HANDLE_INSTANTIATED)
c5de15cb RG	73	u32 rdsta; /RNG DRNG Status Register/
	74	u32 rsvd2[15];
	75	};
	76
48ef0d2a RG	77	typedef struct ccsr_sec {
	78	u32 res0;
	79	u32 mcfgr; /* Master CFG Register */
	80	u8 res1[0x4];
	81	u32 scfgr;
	82	struct {
	83	u32 ms; /* Job Ring LIODN Register, MS */
	84	u32 ls; /* Job Ring LIODN Register, LS */
	85	} jrliodnr[4];
	86	u8 res2[0x2c];
	87	u32 jrstartr; /* Job Ring Start Register */
	88	struct {
	89	u32 ms; /* RTIC LIODN Register, MS */
	90	u32 ls; /* RTIC LIODN Register, LS */
	91	} rticliodnr[4];
	92	u8 res3[0x1c];
	93	u32 decorr; /* DECO Request Register */
	94	struct {
	95	u32 ms; /* DECO LIODN Register, MS */
	96	u32 ls; /* DECO LIODN Register, LS */
	97	} decoliodnr[8];
	98	u8 res4[0x40];
	99	u32 dar; /* DECO Avail Register */
	100	u32 drr; /* DECO Reset Register */
c5de15cb RG	101	u8 res5[0x4d8];
c5de15cb RG	102	struct rng4tst rng; /* RNG Registers */
f91e65a7	103	u8 res6[0x8a0];
48ef0d2a RG	104	u32 crnr_ms; /* CHA Revision Number Register, MS */
	105	u32 crnr_ls; /* CHA Revision Number Register, LS */
	106	u32 ctpr_ms; /* Compile Time Parameters Register, MS */
	107	u32 ctpr_ls; /* Compile Time Parameters Register, LS */
f91e65a7	108	u8 res7[0x10];
48ef0d2a RG	109	u32 far_ms; /* Fault Address Register, MS */
	110	u32 far_ls; /* Fault Address Register, LS */
	111	u32 falr; /* Fault Address LIODN Register */
	112	u32 fadr; /* Fault Address Detail Register */
f91e65a7	113	u8 res8[0x4];
48ef0d2a	114	u32 csta; /* CAAM Status Register */
f91e65a7 UC	115	u32 smpart; /* Secure Memory Partition Parameters */
f91e65a7 UC	116	u32 smvid; /* Secure Memory Version ID */
48ef0d2a RG	117	u32 rvid; /* Run Time Integrity Checking Version ID Reg.*/
	118	u32 ccbvid; /* CHA Cluster Block Version ID Register */
	119	u32 chavid_ms; /* CHA Version ID Register, MS */
	120	u32 chavid_ls; /* CHA Version ID Register, LS */
	121	u32 chanum_ms; /* CHA Number Register, MS */
	122	u32 chanum_ls; /* CHA Number Register, LS */
	123	u32 secvid_ms; /* SEC Version ID Register, MS */
	124	u32 secvid_ls; /* SEC Version ID Register, LS */
	125	u8 res9[0x6020];
	126	u32 qilcr_ms; /* Queue Interface LIODN CFG Register, MS */
	127	u32 qilcr_ls; /* Queue Interface LIODN CFG Register, LS */
	128	u8 res10[0x8fd8];
	129	} ccsr_sec_t;
	130
	131	#define SEC_CTPR_MS_AXI_LIODN 0x08000000
	132	#define SEC_CTPR_MS_QI 0x02000000
	133	#define SEC_CTPR_MS_VIRT_EN_INCL 0x00000001
	134	#define SEC_CTPR_MS_VIRT_EN_POR 0x00000002
	135	#define SEC_RVID_MA 0x0f000000
	136	#define SEC_CHANUM_MS_JRNUM_MASK 0xf0000000
	137	#define SEC_CHANUM_MS_JRNUM_SHIFT 28
	138	#define SEC_CHANUM_MS_DECONUM_MASK 0x0f000000
	139	#define SEC_CHANUM_MS_DECONUM_SHIFT 24
	140	#define SEC_SECVID_MS_IPID_MASK 0xffff0000
	141	#define SEC_SECVID_MS_IPID_SHIFT 16
	142	#define SEC_SECVID_MS_MAJ_REV_MASK 0x0000ff00
	143	#define SEC_SECVID_MS_MAJ_REV_SHIFT 8
	144	#define SEC_CCBVID_ERA_MASK 0xff000000
	145	#define SEC_CCBVID_ERA_SHIFT 24
	146	#define SEC_SCFGR_RDBENABLE 0x00000400
	147	#define SEC_SCFGR_VIRT_EN 0x00008000
	148	#define SEC_CHAVID_LS_RNG_SHIFT 16
	149	#define SEC_CHAVID_RNG_LS_MASK 0x000f0000
b9eebfad RG	150
	151	#define CONFIG_JRSTARTR_JR0 0x00000001
	152
	153	struct jr_regs {
f91e65a7 UC	154	#if defined(CONFIG_SYS_FSL_SEC_LE) && \
f91e65a7 UC	155	!(defined(CONFIG_MX6) \|\| defined(CONFIG_MX7))
b9eebfad RG	156	u32 irba_l;
	157	u32 irba_h;
	158	#else
	159	u32 irba_h;
	160	u32 irba_l;
	161	#endif
	162	u32 rsvd1;
	163	u32 irs;
	164	u32 rsvd2;
	165	u32 irsa;
	166	u32 rsvd3;
	167	u32 irja;
f91e65a7 UC	168	#if defined(CONFIG_SYS_FSL_SEC_LE) && \
f91e65a7 UC	169	!(defined(CONFIG_MX6) \|\| defined(CONFIG_MX7))
b9eebfad RG	170	u32 orba_l;
	171	u32 orba_h;
	172	#else
	173	u32 orba_h;
	174	u32 orba_l;
	175	#endif
	176	u32 rsvd4;
	177	u32 ors;
	178	u32 rsvd5;
	179	u32 orjr;
	180	u32 rsvd6;
	181	u32 orsf;
	182	u32 rsvd7;
	183	u32 jrsta;
	184	u32 rsvd8;
	185	u32 jrint;
	186	u32 jrcfg0;
	187	u32 jrcfg1;
	188	u32 rsvd9;
	189	u32 irri;
	190	u32 rsvd10;
	191	u32 orwi;
	192	u32 rsvd11;
	193	u32 jrcr;
	194	};
	195
94e3c8c4	196	/*
	197	* Scatter Gather Entry - Specifies the the Scatter Gather Format
	198	* related information
	199	*/
	200	struct sg_entry {
f91e65a7 UC	201	#if defined(CONFIG_SYS_FSL_SEC_LE) && \
f91e65a7 UC	202	!(defined(CONFIG_MX6) \|\| defined(CONFIG_MX7))
94e3c8c4	203	uint32_t addr_lo; /* Memory Address - lo */
f59e69cb	204	uint32_t addr_hi; /* Memory Address of start of buffer - hi */
94e3c8c4	205	#else
f59e69cb	206	uint32_t addr_hi; /* Memory Address of start of buffer - hi */
94e3c8c4	207	uint32_t addr_lo; /* Memory Address - lo */
	208	#endif
	209
	210	uint32_t len_flag; /* Length of the data in the frame */
	211	#define SG_ENTRY_LENGTH_MASK 0x3FFFFFFF
	212	#define SG_ENTRY_EXTENSION_BIT 0x80000000
	213	#define SG_ENTRY_FINAL_BIT 0x40000000
	214	uint32_t bpid_offset;
	215	#define SG_ENTRY_BPID_MASK 0x00FF0000
	216	#define SG_ENTRY_BPID_SHIFT 16
	217	#define SG_ENTRY_OFFSET_MASK 0x00001FFF
	218	#define SG_ENTRY_OFFSET_SHIFT 0
	219	};
	220
598e9dcc CG	221	#define BLOB_SIZE(x) ((x) + 32 + 16) /* Blob buffer size */
598e9dcc CG	222
f91e65a7 UC	223	#if defined(CONFIG_MX6) \|\| defined(CONFIG_MX7)
	224	/* Job Ring Base Address */
	225	#define JR_BASE_ADDR(x) (CONFIG_SYS_FSL_SEC_ADDR + 0x1000 * (x + 1))
	226	/* Secure Memory Offset varies accross versions */
	227	#define SM_V1_OFFSET 0x0f4
	228	#define SM_V2_OFFSET 0xa00
	229	/Secure Memory Versioning /
	230	#define SMVID_V2 0x20105
	231	#define SM_VERSION(x) (x < SMVID_V2 ? 1 : 2)
	232	#define SM_OFFSET(x) (x == 1 ? SM_V1_OFFSET : SM_V2_OFFSET)
0200020b RC	233	/* CAAM Job Ring 0 Registers */
	234	/* Secure Memory Partition Owner register */
	235	#define SMCSJR_PO (3 << 6)
	236	/* JR Allocation Error */
	237	#define SMCSJR_AERR (3 << 12)
	238	/* Secure memory partition 0 page 0 owner register */
f91e65a7	239	#define CAAM_SMPO_0 (CONFIG_SYS_FSL_SEC_ADDR + 0x1FBC)
0200020b	240	/* Secure memory command register */
f91e65a7	241	#define CAAM_SMCJR(v, jr) (JR_BASE_ADDR(jr) + SM_OFFSET(v) + SM_CMD(v))
0200020b	242	/* Secure memory command status register */
f91e65a7	243	#define CAAM_SMCSJR(v, jr) (JR_BASE_ADDR(jr) + SM_OFFSET(v) + SM_STATUS(v))
0200020b	244	/* Secure memory access permissions register */
f91e65a7 UC	245	#define CAAM_SMAPJR(v, jr, y) \
f91e65a7 UC	246	(JR_BASE_ADDR(jr) + SM_OFFSET(v) + SM_PERM(v) + y * 16)
0200020b	247	/* Secure memory access group 2 register */
f91e65a7 UC	248	#define CAAM_SMAG2JR(v, jr, y) \
f91e65a7 UC	249	(JR_BASE_ADDR(jr) + SM_OFFSET(v) + SM_GROUP2(v) + y * 16)
0200020b	250	/* Secure memory access group 1 register */
f91e65a7 UC	251	#define CAAM_SMAG1JR(v, jr, y) \
f91e65a7 UC	252	(JR_BASE_ADDR(jr) + SM_OFFSET(v) + SM_GROUP1(v) + y * 16)
0200020b RC	253
0200020b RC	254	/* Commands and macros for secure memory */
f91e65a7 UC	255	#define SM_CMD(v) (v == 1 ? 0x0 : 0x1E4)
	256	#define SM_STATUS(v) (v == 1 ? 0x8 : 0x1EC)
	257	#define SM_PERM(v) (v == 1 ? 0x10 : 0x4)
	258	#define SM_GROUP2(v) (v == 1 ? 0x14 : 0x8)
	259	#define SM_GROUP1(v) (v == 1 ? 0x18 : 0xC)
0200020b RC	260	#define CMD_PAGE_ALLOC 0x1
	261	#define CMD_PAGE_DEALLOC 0x2
	262	#define CMD_PART_DEALLOC 0x3
	263	#define CMD_INQUIRY 0x5
	264	#define CMD_COMPLETE (3 << 14)
	265	#define PAGE_AVAILABLE 0
	266	#define PAGE_OWNED (3 << 6)
	267	#define PAGE(x) (x << 16)
	268	#define PARTITION(x) (x << 8)
	269	#define PARTITION_OWNER(x) (0x3 << (x*2))
	270
	271	/* Address of secure 4kbyte pages */
	272	#define SEC_MEM_PAGE0 CAAM_ARB_BASE_ADDR
	273	#define SEC_MEM_PAGE1 (CAAM_ARB_BASE_ADDR + 0x1000)
	274	#define SEC_MEM_PAGE2 (CAAM_ARB_BASE_ADDR + 0x2000)
	275	#define SEC_MEM_PAGE3 (CAAM_ARB_BASE_ADDR + 0x3000)
	276
	277	#define JR_MID 2 /* Matches ROM configuration */
	278	#define KS_G1 (1 << JR_MID) /* CAAM only */
	279	#define PERM 0x0000B008 /* Clear on release, lock SMAP
	280	* lock SMAG group 1 Blob */
	281
0200020b RC	282	/* HAB WRAPPED KEY header */
	283	#define WRP_HDR_SIZE 0x08
	284	#define HDR_TAG 0x81
	285	#define HDR_PAR 0x41
	286	/* HAB WRAPPED KEY Data */
	287	#define HAB_MOD 0x66
	288	#define HAB_ALG 0x55
	289	#define HAB_FLG 0x00
	290
	291	/* Partition and Page IDs */
	292	#define PARTITION_1 1
	293	#define PAGE_1 1
	294
	295	#define ERROR_IN_PAGE_ALLOC 1
	296	#define ECONSTRJDESC -1
	297
	298	#endif
	299
0200020b RC	300	/* blob_dek:
	301	* Encapsulates the src in a secure blob and stores it dst
	302	* @src: reference to the plaintext
	303	* @dst: reference to the output adrress
	304	* @len: size in bytes of src
	305	* @return: 0 on success, error otherwise
	306	*/
	307	int blob_dek(const u8 src, u8 dst, u8 len);
	308
4fd64746	309	#if defined(CONFIG_ARCH_C29X)
76394c9c AP	310	int sec_init_idx(uint8_t);
	311	#endif
	312	int sec_init(void);
48ef0d2a RG	313	#endif
	314
	315	#endif /* __FSL_SEC_H */