]>
Commit | Line | Data |
---|---|---|
e2211743 | 1 | /* |
dc7c9a1a | 2 | * linux/include/linux/mtd/nand.h |
e2211743 | 3 | * |
2a8e0fc8 CH |
4 | * Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org> |
5 | * Steven J. Hill <sjhill@realitydiluted.com> | |
6 | * Thomas Gleixner <tglx@linutronix.de> | |
e2211743 | 7 | * |
ff94bc40 | 8 | * SPDX-License-Identifier: GPL-2.0+ |
e2211743 | 9 | * |
cfa460ad WJ |
10 | * Info: |
11 | * Contains standard defines and IDs for NAND flash devices | |
e2211743 | 12 | * |
cfa460ad WJ |
13 | * Changelog: |
14 | * See git changelog. | |
e2211743 WD |
15 | */ |
16 | #ifndef __LINUX_MTD_NAND_H | |
17 | #define __LINUX_MTD_NAND_H | |
18 | ||
cfa460ad WJ |
19 | #include "config.h" |
20 | ||
7b15e2bb | 21 | #include "linux/compat.h" |
cfa460ad | 22 | #include "linux/mtd/mtd.h" |
ff94bc40 | 23 | #include "linux/mtd/flashchip.h" |
a47f957a | 24 | #include "linux/mtd/bbm.h" |
addb2e16 BS |
25 | |
26 | struct mtd_info; | |
245eb900 | 27 | struct nand_flash_dev; |
addb2e16 | 28 | /* Scan and identify a NAND device */ |
ff94bc40 HS |
29 | extern int nand_scan(struct mtd_info *mtd, int max_chips); |
30 | /* | |
31 | * Separate phases of nand_scan(), allowing board driver to intervene | |
32 | * and override command or ECC setup according to flash type. | |
33 | */ | |
245eb900 | 34 | extern int nand_scan_ident(struct mtd_info *mtd, int max_chips, |
ff94bc40 | 35 | struct nand_flash_dev *table); |
cfa460ad WJ |
36 | extern int nand_scan_tail(struct mtd_info *mtd); |
37 | ||
addb2e16 | 38 | /* Free resources held by the NAND device */ |
2a8e0fc8 | 39 | extern void nand_release(struct mtd_info *mtd); |
addb2e16 | 40 | |
cfa460ad WJ |
41 | /* Internal helper for board drivers which need to override command function */ |
42 | extern void nand_wait_ready(struct mtd_info *mtd); | |
addb2e16 | 43 | |
2a8e0fc8 CH |
44 | /* |
45 | * This constant declares the max. oobsize / page, which | |
addb2e16 BS |
46 | * is supported now. If you add a chip with bigger oobsize/page |
47 | * adjust this accordingly. | |
48 | */ | |
2580a2a7 SDPP |
49 | #define NAND_MAX_OOBSIZE 1216 |
50 | #define NAND_MAX_PAGESIZE 16384 | |
addb2e16 BS |
51 | |
52 | /* | |
53 | * Constants for hardware specific CLE/ALE/NCE function | |
cfa460ad WJ |
54 | * |
55 | * These are bits which can be or'ed to set/clear multiple | |
56 | * bits in one go. | |
57 | */ | |
addb2e16 | 58 | /* Select the chip by setting nCE to low */ |
cfa460ad | 59 | #define NAND_NCE 0x01 |
addb2e16 | 60 | /* Select the command latch by setting CLE to high */ |
cfa460ad | 61 | #define NAND_CLE 0x02 |
addb2e16 | 62 | /* Select the address latch by setting ALE to high */ |
cfa460ad WJ |
63 | #define NAND_ALE 0x04 |
64 | ||
65 | #define NAND_CTRL_CLE (NAND_NCE | NAND_CLE) | |
66 | #define NAND_CTRL_ALE (NAND_NCE | NAND_ALE) | |
67 | #define NAND_CTRL_CHANGE 0x80 | |
addb2e16 | 68 | |
e2211743 WD |
69 | /* |
70 | * Standard NAND flash commands | |
71 | */ | |
72 | #define NAND_CMD_READ0 0 | |
73 | #define NAND_CMD_READ1 1 | |
cfa460ad | 74 | #define NAND_CMD_RNDOUT 5 |
e2211743 WD |
75 | #define NAND_CMD_PAGEPROG 0x10 |
76 | #define NAND_CMD_READOOB 0x50 | |
77 | #define NAND_CMD_ERASE1 0x60 | |
78 | #define NAND_CMD_STATUS 0x70 | |
79 | #define NAND_CMD_SEQIN 0x80 | |
cfa460ad | 80 | #define NAND_CMD_RNDIN 0x85 |
e2211743 WD |
81 | #define NAND_CMD_READID 0x90 |
82 | #define NAND_CMD_ERASE2 0xd0 | |
2a8e0fc8 | 83 | #define NAND_CMD_PARAM 0xec |
dfe64e2c SL |
84 | #define NAND_CMD_GET_FEATURES 0xee |
85 | #define NAND_CMD_SET_FEATURES 0xef | |
e2211743 WD |
86 | #define NAND_CMD_RESET 0xff |
87 | ||
2a8e0fc8 CH |
88 | #define NAND_CMD_LOCK 0x2a |
89 | #define NAND_CMD_UNLOCK1 0x23 | |
90 | #define NAND_CMD_UNLOCK2 0x24 | |
91 | ||
addb2e16 BS |
92 | /* Extended commands for large page devices */ |
93 | #define NAND_CMD_READSTART 0x30 | |
cfa460ad | 94 | #define NAND_CMD_RNDOUTSTART 0xE0 |
addb2e16 BS |
95 | #define NAND_CMD_CACHEDPROG 0x15 |
96 | ||
cfa460ad WJ |
97 | /* Extended commands for AG-AND device */ |
98 | /* | |
99 | * Note: the command for NAND_CMD_DEPLETE1 is really 0x00 but | |
100 | * there is no way to distinguish that from NAND_CMD_READ0 | |
101 | * until the remaining sequence of commands has been completed | |
102 | * so add a high order bit and mask it off in the command. | |
103 | */ | |
104 | #define NAND_CMD_DEPLETE1 0x100 | |
105 | #define NAND_CMD_DEPLETE2 0x38 | |
106 | #define NAND_CMD_STATUS_MULTI 0x71 | |
107 | #define NAND_CMD_STATUS_ERROR 0x72 | |
108 | /* multi-bank error status (banks 0-3) */ | |
109 | #define NAND_CMD_STATUS_ERROR0 0x73 | |
110 | #define NAND_CMD_STATUS_ERROR1 0x74 | |
111 | #define NAND_CMD_STATUS_ERROR2 0x75 | |
112 | #define NAND_CMD_STATUS_ERROR3 0x76 | |
113 | #define NAND_CMD_STATUS_RESET 0x7f | |
114 | #define NAND_CMD_STATUS_CLEAR 0xff | |
115 | ||
116 | #define NAND_CMD_NONE -1 | |
117 | ||
addb2e16 BS |
118 | /* Status bits */ |
119 | #define NAND_STATUS_FAIL 0x01 | |
120 | #define NAND_STATUS_FAIL_N1 0x02 | |
121 | #define NAND_STATUS_TRUE_READY 0x20 | |
122 | #define NAND_STATUS_READY 0x40 | |
123 | #define NAND_STATUS_WP 0x80 | |
124 | ||
125 | /* | |
126 | * Constants for ECC_MODES | |
127 | */ | |
cfa460ad WJ |
128 | typedef enum { |
129 | NAND_ECC_NONE, | |
130 | NAND_ECC_SOFT, | |
131 | NAND_ECC_HW, | |
132 | NAND_ECC_HW_SYNDROME, | |
f83b7f9e | 133 | NAND_ECC_HW_OOB_FIRST, |
4c6de856 | 134 | NAND_ECC_SOFT_BCH, |
cfa460ad | 135 | } nand_ecc_modes_t; |
addb2e16 | 136 | |
dc7c9a1a | 137 | /* |
addb2e16 | 138 | * Constants for Hardware ECC |
cfa460ad | 139 | */ |
addb2e16 BS |
140 | /* Reset Hardware ECC for read */ |
141 | #define NAND_ECC_READ 0 | |
142 | /* Reset Hardware ECC for write */ | |
143 | #define NAND_ECC_WRITE 1 | |
dfe64e2c | 144 | /* Enable Hardware ECC before syndrome is read back from flash */ |
addb2e16 BS |
145 | #define NAND_ECC_READSYN 2 |
146 | ||
cfa460ad WJ |
147 | /* Bit mask for flags passed to do_nand_read_ecc */ |
148 | #define NAND_GET_DEVICE 0x80 | |
149 | ||
150 | ||
2a8e0fc8 CH |
151 | /* |
152 | * Option constants for bizarre disfunctionality and real | |
153 | * features. | |
154 | */ | |
dfe64e2c | 155 | /* Buswidth is 16 bit */ |
addb2e16 BS |
156 | #define NAND_BUSWIDTH_16 0x00000002 |
157 | /* Device supports partial programming without padding */ | |
158 | #define NAND_NO_PADDING 0x00000004 | |
159 | /* Chip has cache program function */ | |
160 | #define NAND_CACHEPRG 0x00000008 | |
161 | /* Chip has copy back function */ | |
162 | #define NAND_COPYBACK 0x00000010 | |
2a8e0fc8 | 163 | /* |
ff94bc40 HS |
164 | * Chip requires ready check on read (for auto-incremented sequential read). |
165 | * True only for small page devices; large page devices do not support | |
166 | * autoincrement. | |
2a8e0fc8 | 167 | */ |
ff94bc40 HS |
168 | #define NAND_NEED_READRDY 0x00000100 |
169 | ||
cfa460ad WJ |
170 | /* Chip does not allow subpage writes */ |
171 | #define NAND_NO_SUBPAGE_WRITE 0x00000200 | |
172 | ||
2a8e0fc8 CH |
173 | /* Device is one of 'new' xD cards that expose fake nand command set */ |
174 | #define NAND_BROKEN_XD 0x00000400 | |
175 | ||
176 | /* Device behaves just like nand, but is readonly */ | |
177 | #define NAND_ROM 0x00000800 | |
addb2e16 | 178 | |
c788ecfd | 179 | /* Device supports subpage reads */ |
ff94bc40 | 180 | #define NAND_SUBPAGE_READ 0x00001000 |
c788ecfd | 181 | |
addb2e16 | 182 | /* Options valid for Samsung large page devices */ |
ff94bc40 | 183 | #define NAND_SAMSUNG_LP_OPTIONS NAND_CACHEPRG |
addb2e16 BS |
184 | |
185 | /* Macros to identify the above */ | |
addb2e16 | 186 | #define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG)) |
c788ecfd | 187 | #define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ)) |
addb2e16 | 188 | |
addb2e16 | 189 | /* Non chip related options */ |
cfa460ad | 190 | /* This option skips the bbt scan during initialization. */ |
dfe64e2c | 191 | #define NAND_SKIP_BBTSCAN 0x00010000 |
2a8e0fc8 CH |
192 | /* |
193 | * This option is defined if the board driver allocates its own buffers | |
194 | * (e.g. because it needs them DMA-coherent). | |
195 | */ | |
dfe64e2c | 196 | #define NAND_OWN_BUFFERS 0x00020000 |
2a8e0fc8 | 197 | /* Chip may not exist, so silence any errors in scan */ |
dfe64e2c | 198 | #define NAND_SCAN_SILENT_NODEV 0x00040000 |
ff94bc40 HS |
199 | /* |
200 | * Autodetect nand buswidth with readid/onfi. | |
201 | * This suppose the driver will configure the hardware in 8 bits mode | |
202 | * when calling nand_scan_ident, and update its configuration | |
203 | * before calling nand_scan_tail. | |
204 | */ | |
205 | #define NAND_BUSWIDTH_AUTO 0x00080000 | |
2a8e0fc8 | 206 | |
addb2e16 | 207 | /* Options set by nand scan */ |
fb49454b SW |
208 | /* bbt has already been read */ |
209 | #define NAND_BBT_SCANNED 0x40000000 | |
cfa460ad WJ |
210 | /* Nand scan has allocated controller struct */ |
211 | #define NAND_CONTROLLER_ALLOC 0x80000000 | |
addb2e16 | 212 | |
cfa460ad WJ |
213 | /* Cell info constants */ |
214 | #define NAND_CI_CHIPNR_MSK 0x03 | |
215 | #define NAND_CI_CELLTYPE_MSK 0x0C | |
ff94bc40 | 216 | #define NAND_CI_CELLTYPE_SHIFT 2 |
addb2e16 | 217 | |
addb2e16 BS |
218 | /* Keep gcc happy */ |
219 | struct nand_chip; | |
dc7c9a1a | 220 | |
ff94bc40 HS |
221 | /* ONFI features */ |
222 | #define ONFI_FEATURE_16_BIT_BUS (1 << 0) | |
223 | #define ONFI_FEATURE_EXT_PARAM_PAGE (1 << 7) | |
224 | ||
dfe64e2c SL |
225 | /* ONFI timing mode, used in both asynchronous and synchronous mode */ |
226 | #define ONFI_TIMING_MODE_0 (1 << 0) | |
227 | #define ONFI_TIMING_MODE_1 (1 << 1) | |
228 | #define ONFI_TIMING_MODE_2 (1 << 2) | |
229 | #define ONFI_TIMING_MODE_3 (1 << 3) | |
230 | #define ONFI_TIMING_MODE_4 (1 << 4) | |
231 | #define ONFI_TIMING_MODE_5 (1 << 5) | |
232 | #define ONFI_TIMING_MODE_UNKNOWN (1 << 6) | |
233 | ||
234 | /* ONFI feature address */ | |
235 | #define ONFI_FEATURE_ADDR_TIMING_MODE 0x1 | |
236 | ||
ff94bc40 HS |
237 | /* Vendor-specific feature address (Micron) */ |
238 | #define ONFI_FEATURE_ADDR_READ_RETRY 0x89 | |
239 | ||
dfe64e2c SL |
240 | /* ONFI subfeature parameters length */ |
241 | #define ONFI_SUBFEATURE_PARAM_LEN 4 | |
242 | ||
ff94bc40 HS |
243 | /* ONFI optional commands SET/GET FEATURES supported? */ |
244 | #define ONFI_OPT_CMD_SET_GET_FEATURES (1 << 2) | |
245 | ||
0272c718 FF |
246 | struct nand_onfi_params { |
247 | /* rev info and features block */ | |
248 | /* 'O' 'N' 'F' 'I' */ | |
249 | u8 sig[4]; | |
250 | __le16 revision; | |
251 | __le16 features; | |
252 | __le16 opt_cmd; | |
ff94bc40 HS |
253 | u8 reserved0[2]; |
254 | __le16 ext_param_page_length; /* since ONFI 2.1 */ | |
255 | u8 num_of_param_pages; /* since ONFI 2.1 */ | |
256 | u8 reserved1[17]; | |
0272c718 FF |
257 | |
258 | /* manufacturer information block */ | |
259 | char manufacturer[12]; | |
260 | char model[20]; | |
261 | u8 jedec_id; | |
262 | __le16 date_code; | |
263 | u8 reserved2[13]; | |
264 | ||
265 | /* memory organization block */ | |
266 | __le32 byte_per_page; | |
267 | __le16 spare_bytes_per_page; | |
268 | __le32 data_bytes_per_ppage; | |
269 | __le16 spare_bytes_per_ppage; | |
270 | __le32 pages_per_block; | |
271 | __le32 blocks_per_lun; | |
272 | u8 lun_count; | |
273 | u8 addr_cycles; | |
274 | u8 bits_per_cell; | |
275 | __le16 bb_per_lun; | |
276 | __le16 block_endurance; | |
277 | u8 guaranteed_good_blocks; | |
278 | __le16 guaranteed_block_endurance; | |
279 | u8 programs_per_page; | |
280 | u8 ppage_attr; | |
281 | u8 ecc_bits; | |
282 | u8 interleaved_bits; | |
283 | u8 interleaved_ops; | |
284 | u8 reserved3[13]; | |
285 | ||
286 | /* electrical parameter block */ | |
287 | u8 io_pin_capacitance_max; | |
288 | __le16 async_timing_mode; | |
289 | __le16 program_cache_timing_mode; | |
290 | __le16 t_prog; | |
291 | __le16 t_bers; | |
292 | __le16 t_r; | |
293 | __le16 t_ccs; | |
294 | __le16 src_sync_timing_mode; | |
295 | __le16 src_ssync_features; | |
296 | __le16 clk_pin_capacitance_typ; | |
297 | __le16 io_pin_capacitance_typ; | |
298 | __le16 input_pin_capacitance_typ; | |
299 | u8 input_pin_capacitance_max; | |
ff94bc40 | 300 | u8 driver_strength_support; |
0272c718 FF |
301 | __le16 t_int_r; |
302 | __le16 t_ald; | |
303 | u8 reserved4[7]; | |
304 | ||
305 | /* vendor */ | |
ff94bc40 HS |
306 | __le16 vendor_revision; |
307 | u8 vendor[88]; | |
0272c718 FF |
308 | |
309 | __le16 crc; | |
ff94bc40 | 310 | } __packed; |
0272c718 FF |
311 | |
312 | #define ONFI_CRC_BASE 0x4F4E | |
313 | ||
ff94bc40 HS |
314 | /* Extended ECC information Block Definition (since ONFI 2.1) */ |
315 | struct onfi_ext_ecc_info { | |
316 | u8 ecc_bits; | |
317 | u8 codeword_size; | |
318 | __le16 bb_per_lun; | |
319 | __le16 block_endurance; | |
320 | u8 reserved[2]; | |
321 | } __packed; | |
322 | ||
323 | #define ONFI_SECTION_TYPE_0 0 /* Unused section. */ | |
324 | #define ONFI_SECTION_TYPE_1 1 /* for additional sections. */ | |
325 | #define ONFI_SECTION_TYPE_2 2 /* for ECC information. */ | |
326 | struct onfi_ext_section { | |
327 | u8 type; | |
328 | u8 length; | |
329 | } __packed; | |
330 | ||
331 | #define ONFI_EXT_SECTION_MAX 8 | |
332 | ||
333 | /* Extended Parameter Page Definition (since ONFI 2.1) */ | |
334 | struct onfi_ext_param_page { | |
335 | __le16 crc; | |
336 | u8 sig[4]; /* 'E' 'P' 'P' 'S' */ | |
337 | u8 reserved0[10]; | |
338 | struct onfi_ext_section sections[ONFI_EXT_SECTION_MAX]; | |
339 | ||
340 | /* | |
341 | * The actual size of the Extended Parameter Page is in | |
342 | * @ext_param_page_length of nand_onfi_params{}. | |
343 | * The following are the variable length sections. | |
344 | * So we do not add any fields below. Please see the ONFI spec. | |
345 | */ | |
346 | } __packed; | |
347 | ||
348 | struct nand_onfi_vendor_micron { | |
349 | u8 two_plane_read; | |
350 | u8 read_cache; | |
351 | u8 read_unique_id; | |
352 | u8 dq_imped; | |
353 | u8 dq_imped_num_settings; | |
354 | u8 dq_imped_feat_addr; | |
355 | u8 rb_pulldown_strength; | |
356 | u8 rb_pulldown_strength_feat_addr; | |
357 | u8 rb_pulldown_strength_num_settings; | |
358 | u8 otp_mode; | |
359 | u8 otp_page_start; | |
360 | u8 otp_data_prot_addr; | |
361 | u8 otp_num_pages; | |
362 | u8 otp_feat_addr; | |
363 | u8 read_retry_options; | |
364 | u8 reserved[72]; | |
365 | u8 param_revision; | |
366 | } __packed; | |
367 | ||
4e67c571 HS |
368 | struct jedec_ecc_info { |
369 | u8 ecc_bits; | |
370 | u8 codeword_size; | |
371 | __le16 bb_per_lun; | |
372 | __le16 block_endurance; | |
373 | u8 reserved[2]; | |
374 | } __packed; | |
375 | ||
376 | /* JEDEC features */ | |
377 | #define JEDEC_FEATURE_16_BIT_BUS (1 << 0) | |
378 | ||
379 | struct nand_jedec_params { | |
380 | /* rev info and features block */ | |
381 | /* 'J' 'E' 'S' 'D' */ | |
382 | u8 sig[4]; | |
383 | __le16 revision; | |
384 | __le16 features; | |
385 | u8 opt_cmd[3]; | |
386 | __le16 sec_cmd; | |
387 | u8 num_of_param_pages; | |
388 | u8 reserved0[18]; | |
389 | ||
390 | /* manufacturer information block */ | |
391 | char manufacturer[12]; | |
392 | char model[20]; | |
393 | u8 jedec_id[6]; | |
394 | u8 reserved1[10]; | |
395 | ||
396 | /* memory organization block */ | |
397 | __le32 byte_per_page; | |
398 | __le16 spare_bytes_per_page; | |
399 | u8 reserved2[6]; | |
400 | __le32 pages_per_block; | |
401 | __le32 blocks_per_lun; | |
402 | u8 lun_count; | |
403 | u8 addr_cycles; | |
404 | u8 bits_per_cell; | |
405 | u8 programs_per_page; | |
406 | u8 multi_plane_addr; | |
407 | u8 multi_plane_op_attr; | |
408 | u8 reserved3[38]; | |
409 | ||
410 | /* electrical parameter block */ | |
411 | __le16 async_sdr_speed_grade; | |
412 | __le16 toggle_ddr_speed_grade; | |
413 | __le16 sync_ddr_speed_grade; | |
414 | u8 async_sdr_features; | |
415 | u8 toggle_ddr_features; | |
416 | u8 sync_ddr_features; | |
417 | __le16 t_prog; | |
418 | __le16 t_bers; | |
419 | __le16 t_r; | |
420 | __le16 t_r_multi_plane; | |
421 | __le16 t_ccs; | |
422 | __le16 io_pin_capacitance_typ; | |
423 | __le16 input_pin_capacitance_typ; | |
424 | __le16 clk_pin_capacitance_typ; | |
425 | u8 driver_strength_support; | |
426 | __le16 t_ald; | |
427 | u8 reserved4[36]; | |
428 | ||
429 | /* ECC and endurance block */ | |
430 | u8 guaranteed_good_blocks; | |
431 | __le16 guaranteed_block_endurance; | |
432 | struct jedec_ecc_info ecc_info[4]; | |
433 | u8 reserved5[29]; | |
434 | ||
435 | /* reserved */ | |
436 | u8 reserved6[148]; | |
437 | ||
438 | /* vendor */ | |
439 | __le16 vendor_rev_num; | |
440 | u8 reserved7[88]; | |
441 | ||
442 | /* CRC for Parameter Page */ | |
443 | __le16 crc; | |
444 | } __packed; | |
445 | ||
addb2e16 | 446 | /** |
cfa460ad WJ |
447 | * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independent devices |
448 | * @lock: protection lock | |
addb2e16 | 449 | * @active: the mtd device which holds the controller currently |
2a8e0fc8 CH |
450 | * @wq: wait queue to sleep on if a NAND operation is in |
451 | * progress used instead of the per chip wait queue | |
452 | * when a hw controller is available. | |
dc7c9a1a | 453 | */ |
addb2e16 | 454 | struct nand_hw_control { |
ff94bc40 HS |
455 | spinlock_t lock; |
456 | struct nand_chip *active; | |
cfa460ad WJ |
457 | }; |
458 | ||
459 | /** | |
dfe64e2c SL |
460 | * struct nand_ecc_ctrl - Control structure for ECC |
461 | * @mode: ECC mode | |
462 | * @steps: number of ECC steps per page | |
463 | * @size: data bytes per ECC step | |
464 | * @bytes: ECC bytes per step | |
465 | * @strength: max number of correctible bits per ECC step | |
466 | * @total: total number of ECC bytes per page | |
467 | * @prepad: padding information for syndrome based ECC generators | |
468 | * @postpad: padding information for syndrome based ECC generators | |
cfa460ad | 469 | * @layout: ECC layout control struct pointer |
dfe64e2c SL |
470 | * @priv: pointer to private ECC control data |
471 | * @hwctl: function to control hardware ECC generator. Must only | |
cfa460ad | 472 | * be provided if an hardware ECC is available |
dfe64e2c SL |
473 | * @calculate: function for ECC calculation or readback from ECC hardware |
474 | * @correct: function for ECC correction, matching to ECC generator (sw/hw) | |
d3963721 SW |
475 | * @read_page_raw: function to read a raw page without ECC. This function |
476 | * should hide the specific layout used by the ECC | |
477 | * controller and always return contiguous in-band and | |
478 | * out-of-band data even if they're not stored | |
479 | * contiguously on the NAND chip (e.g. | |
480 | * NAND_ECC_HW_SYNDROME interleaves in-band and | |
481 | * out-of-band data). | |
482 | * @write_page_raw: function to write a raw page without ECC. This function | |
483 | * should hide the specific layout used by the ECC | |
484 | * controller and consider the passed data as contiguous | |
485 | * in-band and out-of-band data. ECC controller is | |
486 | * responsible for doing the appropriate transformations | |
487 | * to adapt to its specific layout (e.g. | |
488 | * NAND_ECC_HW_SYNDROME interleaves in-band and | |
489 | * out-of-band data). | |
dfe64e2c SL |
490 | * @read_page: function to read a page according to the ECC generator |
491 | * requirements; returns maximum number of bitflips corrected in | |
492 | * any single ECC step, 0 if bitflips uncorrectable, -EIO hw error | |
493 | * @read_subpage: function to read parts of the page covered by ECC; | |
494 | * returns same as read_page() | |
ff94bc40 | 495 | * @write_subpage: function to write parts of the page covered by ECC. |
dfe64e2c | 496 | * @write_page: function to write a page according to the ECC generator |
2a8e0fc8 | 497 | * requirements. |
dfe64e2c SL |
498 | * @write_oob_raw: function to write chip OOB data without ECC |
499 | * @read_oob_raw: function to read chip OOB data without ECC | |
cfa460ad WJ |
500 | * @read_oob: function to read chip OOB data |
501 | * @write_oob: function to write chip OOB data | |
502 | */ | |
503 | struct nand_ecc_ctrl { | |
2a8e0fc8 CH |
504 | nand_ecc_modes_t mode; |
505 | int steps; | |
506 | int size; | |
507 | int bytes; | |
508 | int total; | |
dfe64e2c | 509 | int strength; |
2a8e0fc8 CH |
510 | int prepad; |
511 | int postpad; | |
cfa460ad | 512 | struct nand_ecclayout *layout; |
2a8e0fc8 CH |
513 | void *priv; |
514 | void (*hwctl)(struct mtd_info *mtd, int mode); | |
515 | int (*calculate)(struct mtd_info *mtd, const uint8_t *dat, | |
516 | uint8_t *ecc_code); | |
517 | int (*correct)(struct mtd_info *mtd, uint8_t *dat, uint8_t *read_ecc, | |
518 | uint8_t *calc_ecc); | |
519 | int (*read_page_raw)(struct mtd_info *mtd, struct nand_chip *chip, | |
dfe64e2c SL |
520 | uint8_t *buf, int oob_required, int page); |
521 | int (*write_page_raw)(struct mtd_info *mtd, struct nand_chip *chip, | |
81c77252 | 522 | const uint8_t *buf, int oob_required, int page); |
2a8e0fc8 | 523 | int (*read_page)(struct mtd_info *mtd, struct nand_chip *chip, |
dfe64e2c | 524 | uint8_t *buf, int oob_required, int page); |
2a8e0fc8 | 525 | int (*read_subpage)(struct mtd_info *mtd, struct nand_chip *chip, |
4e67c571 | 526 | uint32_t offs, uint32_t len, uint8_t *buf, int page); |
ff94bc40 HS |
527 | int (*write_subpage)(struct mtd_info *mtd, struct nand_chip *chip, |
528 | uint32_t offset, uint32_t data_len, | |
81c77252 | 529 | const uint8_t *data_buf, int oob_required, int page); |
dfe64e2c | 530 | int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip, |
81c77252 | 531 | const uint8_t *buf, int oob_required, int page); |
dfe64e2c SL |
532 | int (*write_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip, |
533 | int page); | |
534 | int (*read_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip, | |
535 | int page); | |
536 | int (*read_oob)(struct mtd_info *mtd, struct nand_chip *chip, int page); | |
2a8e0fc8 CH |
537 | int (*write_oob)(struct mtd_info *mtd, struct nand_chip *chip, |
538 | int page); | |
cfa460ad WJ |
539 | }; |
540 | ||
541 | /** | |
542 | * struct nand_buffers - buffer structure for read/write | |
4e67c571 HS |
543 | * @ecccalc: buffer pointer for calculated ECC, size is oobsize. |
544 | * @ecccode: buffer pointer for ECC read from flash, size is oobsize. | |
545 | * @databuf: buffer pointer for data, size is (page size + oobsize). | |
cfa460ad WJ |
546 | * |
547 | * Do not change the order of buffers. databuf and oobrbuf must be in | |
548 | * consecutive order. | |
549 | */ | |
550 | struct nand_buffers { | |
b572595e SG |
551 | uint8_t ecccalc[ALIGN(NAND_MAX_OOBSIZE, ARCH_DMA_MINALIGN)]; |
552 | uint8_t ecccode[ALIGN(NAND_MAX_OOBSIZE, ARCH_DMA_MINALIGN)]; | |
553 | uint8_t databuf[ALIGN(NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE, | |
554 | ARCH_DMA_MINALIGN)]; | |
cfa460ad | 555 | }; |
addb2e16 BS |
556 | |
557 | /** | |
558 | * struct nand_chip - NAND Private Flash Chip Data | |
2a8e0fc8 CH |
559 | * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the |
560 | * flash device | |
561 | * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the | |
562 | * flash device. | |
addb2e16 | 563 | * @read_byte: [REPLACEABLE] read one byte from the chip |
addb2e16 | 564 | * @read_word: [REPLACEABLE] read one word from the chip |
ff94bc40 HS |
565 | * @write_byte: [REPLACEABLE] write a single byte to the chip on the |
566 | * low 8 I/O lines | |
addb2e16 BS |
567 | * @write_buf: [REPLACEABLE] write data from the buffer to the chip |
568 | * @read_buf: [REPLACEABLE] read data from the chip into the buffer | |
addb2e16 | 569 | * @select_chip: [REPLACEABLE] select chip nr |
ff94bc40 HS |
570 | * @block_bad: [REPLACEABLE] check if a block is bad, using OOB markers |
571 | * @block_markbad: [REPLACEABLE] mark a block bad | |
2a8e0fc8 | 572 | * @cmd_ctrl: [BOARDSPECIFIC] hardwarespecific function for controlling |
cfa460ad | 573 | * ALE/CLE/nCE. Also used to write command and address |
2a8e0fc8 CH |
574 | * @init_size: [BOARDSPECIFIC] hardwarespecific function for setting |
575 | * mtd->oobsize, mtd->writesize and so on. | |
576 | * @id_data contains the 8 bytes values of NAND_CMD_READID. | |
577 | * Return with the bus width. | |
dfe64e2c | 578 | * @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accessing |
2a8e0fc8 CH |
579 | * device ready/busy line. If set to NULL no access to |
580 | * ready/busy is available and the ready/busy information | |
581 | * is read from the chip status register. | |
582 | * @cmdfunc: [REPLACEABLE] hardwarespecific function for writing | |
583 | * commands to the chip. | |
584 | * @waitfunc: [REPLACEABLE] hardwarespecific function for wait on | |
585 | * ready. | |
ff94bc40 HS |
586 | * @setup_read_retry: [FLASHSPECIFIC] flash (vendor) specific function for |
587 | * setting the read-retry mode. Mostly needed for MLC NAND. | |
dfe64e2c | 588 | * @ecc: [BOARDSPECIFIC] ECC control structure |
cfa460ad WJ |
589 | * @buffers: buffer structure for read/write |
590 | * @hwcontrol: platform-specific hardware control structure | |
d3963721 | 591 | * @erase: [REPLACEABLE] erase function |
addb2e16 | 592 | * @scan_bbt: [REPLACEABLE] function to scan bad block table |
2a8e0fc8 CH |
593 | * @chip_delay: [BOARDSPECIFIC] chip dependent delay for transferring |
594 | * data from array to read regs (tR). | |
b9365a26 | 595 | * @state: [INTERN] the current state of the NAND device |
dfe64e2c SL |
596 | * @oob_poi: "poison value buffer," used for laying out OOB data |
597 | * before writing | |
2a8e0fc8 CH |
598 | * @page_shift: [INTERN] number of address bits in a page (column |
599 | * address bits). | |
addb2e16 BS |
600 | * @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock |
601 | * @bbt_erase_shift: [INTERN] number of address bits in a bbt entry | |
602 | * @chip_shift: [INTERN] number of address bits in one chip | |
2a8e0fc8 CH |
603 | * @options: [BOARDSPECIFIC] various chip options. They can partly |
604 | * be set to inform nand_scan about special functionality. | |
605 | * See the defines for further explanation. | |
dfe64e2c SL |
606 | * @bbt_options: [INTERN] bad block specific options. All options used |
607 | * here must come from bbm.h. By default, these options | |
608 | * will be copied to the appropriate nand_bbt_descr's. | |
2a8e0fc8 CH |
609 | * @badblockpos: [INTERN] position of the bad block marker in the oob |
610 | * area. | |
dfe64e2c SL |
611 | * @badblockbits: [INTERN] minimum number of set bits in a good block's |
612 | * bad block marker position; i.e., BBM == 11110111b is | |
613 | * not bad when badblockbits == 7 | |
ff94bc40 HS |
614 | * @bits_per_cell: [INTERN] number of bits per cell. i.e., 1 means SLC. |
615 | * @ecc_strength_ds: [INTERN] ECC correctability from the datasheet. | |
616 | * Minimum amount of bit errors per @ecc_step_ds guaranteed | |
617 | * to be correctable. If unknown, set to zero. | |
618 | * @ecc_step_ds: [INTERN] ECC step required by the @ecc_strength_ds, | |
619 | * also from the datasheet. It is the recommended ECC step | |
620 | * size, if known; if unknown, set to zero. | |
d3963721 SW |
621 | * @onfi_timing_mode_default: [INTERN] default ONFI timing mode. This field is |
622 | * either deduced from the datasheet if the NAND | |
623 | * chip is not ONFI compliant or set to 0 if it is | |
624 | * (an ONFI chip is always configured in mode 0 | |
625 | * after a NAND reset) | |
addb2e16 BS |
626 | * @numchips: [INTERN] number of physical chips |
627 | * @chipsize: [INTERN] the size of one chip for multichip arrays | |
628 | * @pagemask: [INTERN] page number mask = number of (pages / chip) - 1 | |
2a8e0fc8 CH |
629 | * @pagebuf: [INTERN] holds the pagenumber which is currently in |
630 | * data_buf. | |
40462e54 PB |
631 | * @pagebuf_bitflips: [INTERN] holds the bitflip count for the page which is |
632 | * currently in data_buf. | |
cfa460ad | 633 | * @subpagesize: [INTERN] holds the subpagesize |
2a8e0fc8 CH |
634 | * @onfi_version: [INTERN] holds the chip ONFI version (BCD encoded), |
635 | * non 0 if ONFI supported. | |
4e67c571 HS |
636 | * @jedec_version: [INTERN] holds the chip JEDEC version (BCD encoded), |
637 | * non 0 if JEDEC supported. | |
2a8e0fc8 CH |
638 | * @onfi_params: [INTERN] holds the ONFI page parameter when ONFI is |
639 | * supported, 0 otherwise. | |
4e67c571 HS |
640 | * @jedec_params: [INTERN] holds the JEDEC parameter page when JEDEC is |
641 | * supported, 0 otherwise. | |
ff94bc40 HS |
642 | * @read_retries: [INTERN] the number of read retry modes supported |
643 | * @onfi_set_features: [REPLACEABLE] set the features for ONFI nand | |
644 | * @onfi_get_features: [REPLACEABLE] get the features for ONFI nand | |
addb2e16 | 645 | * @bbt: [INTERN] bad block table pointer |
2a8e0fc8 CH |
646 | * @bbt_td: [REPLACEABLE] bad block table descriptor for flash |
647 | * lookup. | |
addb2e16 | 648 | * @bbt_md: [REPLACEABLE] bad block table mirror descriptor |
2a8e0fc8 CH |
649 | * @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial |
650 | * bad block scan. | |
651 | * @controller: [REPLACEABLE] a pointer to a hardware controller | |
dfe64e2c | 652 | * structure which is shared among multiple independent |
2a8e0fc8 | 653 | * devices. |
dfe64e2c | 654 | * @priv: [OPTIONAL] pointer to private chip data |
2a8e0fc8 CH |
655 | * @errstat: [OPTIONAL] hardware specific function to perform |
656 | * additional error status checks (determine if errors are | |
657 | * correctable). | |
cfa460ad | 658 | * @write_page: [REPLACEABLE] High-level page write function |
addb2e16 | 659 | */ |
dc7c9a1a WD |
660 | |
661 | struct nand_chip { | |
b616d9b0 | 662 | struct mtd_info mtd; |
2a8e0fc8 CH |
663 | void __iomem *IO_ADDR_R; |
664 | void __iomem *IO_ADDR_W; | |
665 | ||
666 | uint8_t (*read_byte)(struct mtd_info *mtd); | |
667 | u16 (*read_word)(struct mtd_info *mtd); | |
ff94bc40 | 668 | void (*write_byte)(struct mtd_info *mtd, uint8_t byte); |
2a8e0fc8 CH |
669 | void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len); |
670 | void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len); | |
2a8e0fc8 CH |
671 | void (*select_chip)(struct mtd_info *mtd, int chip); |
672 | int (*block_bad)(struct mtd_info *mtd, loff_t ofs, int getchip); | |
673 | int (*block_markbad)(struct mtd_info *mtd, loff_t ofs); | |
674 | void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl); | |
675 | int (*init_size)(struct mtd_info *mtd, struct nand_chip *this, | |
676 | u8 *id_data); | |
677 | int (*dev_ready)(struct mtd_info *mtd); | |
678 | void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column, | |
679 | int page_addr); | |
680 | int(*waitfunc)(struct mtd_info *mtd, struct nand_chip *this); | |
d3963721 | 681 | int (*erase)(struct mtd_info *mtd, int page); |
2a8e0fc8 CH |
682 | int (*scan_bbt)(struct mtd_info *mtd); |
683 | int (*errstat)(struct mtd_info *mtd, struct nand_chip *this, int state, | |
684 | int status, int page); | |
685 | int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip, | |
ff94bc40 HS |
686 | uint32_t offset, int data_len, const uint8_t *buf, |
687 | int oob_required, int page, int cached, int raw); | |
dfe64e2c SL |
688 | int (*onfi_set_features)(struct mtd_info *mtd, struct nand_chip *chip, |
689 | int feature_addr, uint8_t *subfeature_para); | |
690 | int (*onfi_get_features)(struct mtd_info *mtd, struct nand_chip *chip, | |
691 | int feature_addr, uint8_t *subfeature_para); | |
ff94bc40 | 692 | int (*setup_read_retry)(struct mtd_info *mtd, int retry_mode); |
2a8e0fc8 CH |
693 | |
694 | int chip_delay; | |
695 | unsigned int options; | |
dfe64e2c | 696 | unsigned int bbt_options; |
2a8e0fc8 CH |
697 | |
698 | int page_shift; | |
699 | int phys_erase_shift; | |
700 | int bbt_erase_shift; | |
701 | int chip_shift; | |
702 | int numchips; | |
703 | uint64_t chipsize; | |
704 | int pagemask; | |
705 | int pagebuf; | |
40462e54 | 706 | unsigned int pagebuf_bitflips; |
2a8e0fc8 | 707 | int subpagesize; |
ff94bc40 HS |
708 | uint8_t bits_per_cell; |
709 | uint16_t ecc_strength_ds; | |
710 | uint16_t ecc_step_ds; | |
d3963721 | 711 | int onfi_timing_mode_default; |
2a8e0fc8 CH |
712 | int badblockpos; |
713 | int badblockbits; | |
714 | ||
715 | int onfi_version; | |
4e67c571 | 716 | int jedec_version; |
0272c718 | 717 | #ifdef CONFIG_SYS_NAND_ONFI_DETECTION |
ff94bc40 | 718 | struct nand_onfi_params onfi_params; |
0272c718 | 719 | #endif |
4e67c571 HS |
720 | struct nand_jedec_params jedec_params; |
721 | ||
ff94bc40 HS |
722 | int read_retries; |
723 | ||
724 | flstate_t state; | |
cfa460ad | 725 | |
2a8e0fc8 CH |
726 | uint8_t *oob_poi; |
727 | struct nand_hw_control *controller; | |
728 | struct nand_ecclayout *ecclayout; | |
cfa460ad WJ |
729 | |
730 | struct nand_ecc_ctrl ecc; | |
731 | struct nand_buffers *buffers; | |
cfa460ad WJ |
732 | struct nand_hw_control hwcontrol; |
733 | ||
2a8e0fc8 CH |
734 | uint8_t *bbt; |
735 | struct nand_bbt_descr *bbt_td; | |
736 | struct nand_bbt_descr *bbt_md; | |
cfa460ad | 737 | |
2a8e0fc8 | 738 | struct nand_bbt_descr *badblock_pattern; |
cfa460ad | 739 | |
2a8e0fc8 | 740 | void *priv; |
dc7c9a1a WD |
741 | }; |
742 | ||
17cb4b8f SW |
743 | static inline struct nand_chip *mtd_to_nand(struct mtd_info *mtd) |
744 | { | |
745 | return container_of(mtd, struct nand_chip, mtd); | |
746 | } | |
747 | ||
748 | static inline struct mtd_info *nand_to_mtd(struct nand_chip *chip) | |
749 | { | |
750 | return &chip->mtd; | |
751 | } | |
752 | ||
753 | static inline void *nand_get_controller_data(struct nand_chip *chip) | |
754 | { | |
755 | return chip->priv; | |
756 | } | |
757 | ||
758 | static inline void nand_set_controller_data(struct nand_chip *chip, void *priv) | |
759 | { | |
760 | chip->priv = priv; | |
761 | } | |
762 | ||
e2211743 WD |
763 | /* |
764 | * NAND Flash Manufacturer ID Codes | |
765 | */ | |
766 | #define NAND_MFR_TOSHIBA 0x98 | |
767 | #define NAND_MFR_SAMSUNG 0xec | |
addb2e16 BS |
768 | #define NAND_MFR_FUJITSU 0x04 |
769 | #define NAND_MFR_NATIONAL 0x8f | |
770 | #define NAND_MFR_RENESAS 0x07 | |
771 | #define NAND_MFR_STMICRO 0x20 | |
cfa460ad | 772 | #define NAND_MFR_HYNIX 0xad |
7ebb4479 | 773 | #define NAND_MFR_MICRON 0x2c |
c45912d8 | 774 | #define NAND_MFR_AMD 0x01 |
dfe64e2c SL |
775 | #define NAND_MFR_MACRONIX 0xc2 |
776 | #define NAND_MFR_EON 0x92 | |
ff94bc40 HS |
777 | #define NAND_MFR_SANDISK 0x45 |
778 | #define NAND_MFR_INTEL 0x89 | |
d3963721 | 779 | #define NAND_MFR_ATO 0x9b |
ff94bc40 HS |
780 | |
781 | /* The maximum expected count of bytes in the NAND ID sequence */ | |
782 | #define NAND_MAX_ID_LEN 8 | |
783 | ||
784 | /* | |
785 | * A helper for defining older NAND chips where the second ID byte fully | |
786 | * defined the chip, including the geometry (chip size, eraseblock size, page | |
787 | * size). All these chips have 512 bytes NAND page size. | |
788 | */ | |
789 | #define LEGACY_ID_NAND(nm, devid, chipsz, erasesz, opts) \ | |
790 | { .name = (nm), {{ .dev_id = (devid) }}, .pagesize = 512, \ | |
791 | .chipsize = (chipsz), .erasesize = (erasesz), .options = (opts) } | |
792 | ||
793 | /* | |
794 | * A helper for defining newer chips which report their page size and | |
795 | * eraseblock size via the extended ID bytes. | |
796 | * | |
797 | * The real difference between LEGACY_ID_NAND and EXTENDED_ID_NAND is that with | |
798 | * EXTENDED_ID_NAND, manufacturers overloaded the same device ID so that the | |
799 | * device ID now only represented a particular total chip size (and voltage, | |
800 | * buswidth), and the page size, eraseblock size, and OOB size could vary while | |
801 | * using the same device ID. | |
802 | */ | |
803 | #define EXTENDED_ID_NAND(nm, devid, chipsz, opts) \ | |
804 | { .name = (nm), {{ .dev_id = (devid) }}, .chipsize = (chipsz), \ | |
805 | .options = (opts) } | |
806 | ||
807 | #define NAND_ECC_INFO(_strength, _step) \ | |
808 | { .strength_ds = (_strength), .step_ds = (_step) } | |
809 | #define NAND_ECC_STRENGTH(type) ((type)->ecc.strength_ds) | |
810 | #define NAND_ECC_STEP(type) ((type)->ecc.step_ds) | |
e2211743 | 811 | |
addb2e16 BS |
812 | /** |
813 | * struct nand_flash_dev - NAND Flash Device ID Structure | |
ff94bc40 HS |
814 | * @name: a human-readable name of the NAND chip |
815 | * @dev_id: the device ID (the second byte of the full chip ID array) | |
816 | * @mfr_id: manufecturer ID part of the full chip ID array (refers the same | |
817 | * memory address as @id[0]) | |
818 | * @dev_id: device ID part of the full chip ID array (refers the same memory | |
819 | * address as @id[1]) | |
820 | * @id: full device ID array | |
821 | * @pagesize: size of the NAND page in bytes; if 0, then the real page size (as | |
822 | * well as the eraseblock size) is determined from the extended NAND | |
823 | * chip ID array) | |
824 | * @chipsize: total chip size in MiB | |
825 | * @erasesize: eraseblock size in bytes (determined from the extended ID if 0) | |
826 | * @options: stores various chip bit options | |
827 | * @id_len: The valid length of the @id. | |
828 | * @oobsize: OOB size | |
d3963721 | 829 | * @ecc: ECC correctability and step information from the datasheet. |
ff94bc40 HS |
830 | * @ecc.strength_ds: The ECC correctability from the datasheet, same as the |
831 | * @ecc_strength_ds in nand_chip{}. | |
832 | * @ecc.step_ds: The ECC step required by the @ecc.strength_ds, same as the | |
833 | * @ecc_step_ds in nand_chip{}, also from the datasheet. | |
834 | * For example, the "4bit ECC for each 512Byte" can be set with | |
835 | * NAND_ECC_INFO(4, 512). | |
d3963721 SW |
836 | * @onfi_timing_mode_default: the default ONFI timing mode entered after a NAND |
837 | * reset. Should be deduced from timings described | |
838 | * in the datasheet. | |
839 | * | |
e2211743 WD |
840 | */ |
841 | struct nand_flash_dev { | |
addb2e16 | 842 | char *name; |
ff94bc40 HS |
843 | union { |
844 | struct { | |
845 | uint8_t mfr_id; | |
846 | uint8_t dev_id; | |
847 | }; | |
848 | uint8_t id[NAND_MAX_ID_LEN]; | |
849 | }; | |
850 | unsigned int pagesize; | |
851 | unsigned int chipsize; | |
852 | unsigned int erasesize; | |
853 | unsigned int options; | |
854 | uint16_t id_len; | |
855 | uint16_t oobsize; | |
856 | struct { | |
857 | uint16_t strength_ds; | |
858 | uint16_t step_ds; | |
859 | } ecc; | |
d3963721 | 860 | int onfi_timing_mode_default; |
e2211743 WD |
861 | }; |
862 | ||
addb2e16 BS |
863 | /** |
864 | * struct nand_manufacturers - NAND Flash Manufacturer ID Structure | |
865 | * @name: Manufacturer name | |
b9365a26 | 866 | * @id: manufacturer ID code of device. |
addb2e16 BS |
867 | */ |
868 | struct nand_manufacturers { | |
869 | int id; | |
2a8e0fc8 | 870 | char *name; |
addb2e16 BS |
871 | }; |
872 | ||
ff94bc40 HS |
873 | extern struct nand_flash_dev nand_flash_ids[]; |
874 | extern struct nand_manufacturers nand_manuf_ids[]; | |
addb2e16 | 875 | |
cfa460ad | 876 | extern int nand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd); |
cfa460ad | 877 | extern int nand_default_bbt(struct mtd_info *mtd); |
ff94bc40 | 878 | extern int nand_markbad_bbt(struct mtd_info *mtd, loff_t offs); |
86a720aa | 879 | extern int nand_isreserved_bbt(struct mtd_info *mtd, loff_t offs); |
cfa460ad WJ |
880 | extern int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt); |
881 | extern int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr, | |
882 | int allowbbt); | |
883 | extern int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len, | |
2a8e0fc8 | 884 | size_t *retlen, uint8_t *buf); |
addb2e16 | 885 | |
dc7c9a1a WD |
886 | /* |
887 | * Constants for oob configuration | |
888 | */ | |
addb2e16 BS |
889 | #define NAND_SMALL_BADBLOCK_POS 5 |
890 | #define NAND_LARGE_BADBLOCK_POS 0 | |
891 | ||
cfa460ad WJ |
892 | /** |
893 | * struct platform_nand_chip - chip level device structure | |
894 | * @nr_chips: max. number of chips to scan for | |
895 | * @chip_offset: chip number offset | |
896 | * @nr_partitions: number of partitions pointed to by partitions (or zero) | |
897 | * @partitions: mtd partition list | |
898 | * @chip_delay: R/B delay value in us | |
899 | * @options: Option flags, e.g. 16bit buswidth | |
dfe64e2c SL |
900 | * @bbt_options: BBT option flags, e.g. NAND_BBT_USE_FLASH |
901 | * @ecclayout: ECC layout info structure | |
cfa460ad | 902 | * @part_probe_types: NULL-terminated array of probe types |
cfa460ad WJ |
903 | */ |
904 | struct platform_nand_chip { | |
2a8e0fc8 CH |
905 | int nr_chips; |
906 | int chip_offset; | |
907 | int nr_partitions; | |
908 | struct mtd_partition *partitions; | |
909 | struct nand_ecclayout *ecclayout; | |
910 | int chip_delay; | |
911 | unsigned int options; | |
dfe64e2c | 912 | unsigned int bbt_options; |
2a8e0fc8 | 913 | const char **part_probe_types; |
cfa460ad WJ |
914 | }; |
915 | ||
2a8e0fc8 CH |
916 | /* Keep gcc happy */ |
917 | struct platform_device; | |
918 | ||
cfa460ad WJ |
919 | /** |
920 | * struct platform_nand_ctrl - controller level device structure | |
ff94bc40 HS |
921 | * @probe: platform specific function to probe/setup hardware |
922 | * @remove: platform specific function to remove/teardown hardware | |
cfa460ad WJ |
923 | * @hwcontrol: platform specific hardware control structure |
924 | * @dev_ready: platform specific function to read ready/busy pin | |
925 | * @select_chip: platform specific chip select function | |
926 | * @cmd_ctrl: platform specific function for controlling | |
927 | * ALE/CLE/nCE. Also used to write command and address | |
ff94bc40 HS |
928 | * @write_buf: platform specific function for write buffer |
929 | * @read_buf: platform specific function for read buffer | |
930 | * @read_byte: platform specific function to read one byte from chip | |
cfa460ad WJ |
931 | * @priv: private data to transport driver specific settings |
932 | * | |
933 | * All fields are optional and depend on the hardware driver requirements | |
934 | */ | |
935 | struct platform_nand_ctrl { | |
ff94bc40 HS |
936 | int (*probe)(struct platform_device *pdev); |
937 | void (*remove)(struct platform_device *pdev); | |
2a8e0fc8 CH |
938 | void (*hwcontrol)(struct mtd_info *mtd, int cmd); |
939 | int (*dev_ready)(struct mtd_info *mtd); | |
940 | void (*select_chip)(struct mtd_info *mtd, int chip); | |
941 | void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl); | |
ff94bc40 HS |
942 | void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len); |
943 | void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len); | |
dfe64e2c | 944 | unsigned char (*read_byte)(struct mtd_info *mtd); |
2a8e0fc8 | 945 | void *priv; |
cfa460ad WJ |
946 | }; |
947 | ||
948 | /** | |
949 | * struct platform_nand_data - container structure for platform-specific data | |
950 | * @chip: chip level chip structure | |
951 | * @ctrl: controller level device structure | |
952 | */ | |
953 | struct platform_nand_data { | |
2a8e0fc8 CH |
954 | struct platform_nand_chip chip; |
955 | struct platform_nand_ctrl ctrl; | |
cfa460ad WJ |
956 | }; |
957 | ||
958 | /* Some helpers to access the data structures */ | |
959 | static inline | |
960 | struct platform_nand_chip *get_platform_nandchip(struct mtd_info *mtd) | |
961 | { | |
962 | struct nand_chip *chip = mtd->priv; | |
963 | ||
964 | return chip->priv; | |
965 | } | |
966 | ||
ff94bc40 HS |
967 | #ifdef CONFIG_SYS_NAND_ONFI_DETECTION |
968 | /* return the supported features. */ | |
969 | static inline int onfi_feature(struct nand_chip *chip) | |
970 | { | |
971 | return chip->onfi_version ? le16_to_cpu(chip->onfi_params.features) : 0; | |
972 | } | |
82645f81 | 973 | |
dfe64e2c | 974 | /* return the supported asynchronous timing mode. */ |
dfe64e2c SL |
975 | static inline int onfi_get_async_timing_mode(struct nand_chip *chip) |
976 | { | |
977 | if (!chip->onfi_version) | |
978 | return ONFI_TIMING_MODE_UNKNOWN; | |
979 | return le16_to_cpu(chip->onfi_params.async_timing_mode); | |
980 | } | |
981 | ||
982 | /* return the supported synchronous timing mode. */ | |
983 | static inline int onfi_get_sync_timing_mode(struct nand_chip *chip) | |
984 | { | |
985 | if (!chip->onfi_version) | |
986 | return ONFI_TIMING_MODE_UNKNOWN; | |
987 | return le16_to_cpu(chip->onfi_params.src_sync_timing_mode); | |
988 | } | |
989 | #endif | |
990 | ||
ff94bc40 HS |
991 | /* |
992 | * Check if it is a SLC nand. | |
993 | * The !nand_is_slc() can be used to check the MLC/TLC nand chips. | |
994 | * We do not distinguish the MLC and TLC now. | |
995 | */ | |
996 | static inline bool nand_is_slc(struct nand_chip *chip) | |
997 | { | |
998 | return chip->bits_per_cell == 1; | |
999 | } | |
1000 | ||
27ce9e42 BN |
1001 | /** |
1002 | * Check if the opcode's address should be sent only on the lower 8 bits | |
1003 | * @command: opcode to check | |
1004 | */ | |
1005 | static inline int nand_opcode_8bits(unsigned int command) | |
1006 | { | |
6e1899e6 DM |
1007 | switch (command) { |
1008 | case NAND_CMD_READID: | |
1009 | case NAND_CMD_PARAM: | |
1010 | case NAND_CMD_GET_FEATURES: | |
1011 | case NAND_CMD_SET_FEATURES: | |
1012 | return 1; | |
1013 | default: | |
1014 | break; | |
1015 | } | |
1016 | return 0; | |
27ce9e42 BN |
1017 | } |
1018 | ||
4e67c571 HS |
1019 | /* return the supported JEDEC features. */ |
1020 | static inline int jedec_feature(struct nand_chip *chip) | |
1021 | { | |
1022 | return chip->jedec_version ? le16_to_cpu(chip->jedec_params.features) | |
1023 | : 0; | |
1024 | } | |
1025 | ||
ff94bc40 HS |
1026 | /* Standard NAND functions from nand_base.c */ |
1027 | void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len); | |
1028 | void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len); | |
1029 | void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len); | |
1030 | void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len); | |
1031 | uint8_t nand_read_byte(struct mtd_info *mtd); | |
d3963721 SW |
1032 | |
1033 | /* | |
1034 | * struct nand_sdr_timings - SDR NAND chip timings | |
1035 | * | |
1036 | * This struct defines the timing requirements of a SDR NAND chip. | |
1037 | * These informations can be found in every NAND datasheets and the timings | |
1038 | * meaning are described in the ONFI specifications: | |
1039 | * www.onfi.org/~/media/ONFI/specs/onfi_3_1_spec.pdf (chapter 4.15 Timing | |
1040 | * Parameters) | |
1041 | * | |
1042 | * All these timings are expressed in picoseconds. | |
1043 | */ | |
1044 | ||
1045 | struct nand_sdr_timings { | |
1046 | u32 tALH_min; | |
1047 | u32 tADL_min; | |
1048 | u32 tALS_min; | |
1049 | u32 tAR_min; | |
1050 | u32 tCEA_max; | |
1051 | u32 tCEH_min; | |
1052 | u32 tCH_min; | |
1053 | u32 tCHZ_max; | |
1054 | u32 tCLH_min; | |
1055 | u32 tCLR_min; | |
1056 | u32 tCLS_min; | |
1057 | u32 tCOH_min; | |
1058 | u32 tCS_min; | |
1059 | u32 tDH_min; | |
1060 | u32 tDS_min; | |
1061 | u32 tFEAT_max; | |
1062 | u32 tIR_min; | |
1063 | u32 tITC_max; | |
1064 | u32 tRC_min; | |
1065 | u32 tREA_max; | |
1066 | u32 tREH_min; | |
1067 | u32 tRHOH_min; | |
1068 | u32 tRHW_min; | |
1069 | u32 tRHZ_max; | |
1070 | u32 tRLOH_min; | |
1071 | u32 tRP_min; | |
1072 | u32 tRR_min; | |
1073 | u64 tRST_max; | |
1074 | u32 tWB_max; | |
1075 | u32 tWC_min; | |
1076 | u32 tWH_min; | |
1077 | u32 tWHR_min; | |
1078 | u32 tWP_min; | |
1079 | u32 tWW_min; | |
1080 | }; | |
1081 | ||
1082 | /* get timing characteristics from ONFI timing mode. */ | |
1083 | const struct nand_sdr_timings *onfi_async_timing_mode_to_sdr_timings(int mode); | |
e2211743 | 1084 | #endif /* __LINUX_MTD_NAND_H */ |