projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 4678d674 MK |
1 | /* |
| 2 | * Copyright (C) 2005-2009 Samsung Electronics | |
| 3 | * Minkyu Kang <mk7.kang@samsung.com> | |
| 4 | * Kyungmin Park <kyungmin.park@samsung.com> | |
| 5 | * | |
| 1a459660 | 6 | * SPDX-License-Identifier: GPL-2.0+ |
| 4678d674 MK |
7 | */ |
| 8 | ||
| 9 | #ifndef __SAMSUNG_ONENAND_H__ | |
| 10 | #define __SAMSUNG_ONENAND_H__ | |
| 11 | ||
| 12 | /* | |
| 13 | * OneNAND Controller | |
| 14 | */ | |
| 15 | ||
| 16 | #ifndef __ASSEMBLY__ | |
| 17 | struct samsung_onenand { | |
| f3807374 | 18 | unsigned int mem_cfg; /* 0x0000 */ |
| 4678d674 | 19 | unsigned char res1[0xc]; |
| f3807374 | 20 | unsigned int burst_len; /* 0x0010 */ |
| 4678d674 | 21 | unsigned char res2[0xc]; |
| f3807374 | 22 | unsigned int mem_reset; /* 0x0020 */ |
| 4678d674 | 23 | unsigned char res3[0xc]; |
| f3807374 | 24 | unsigned int int_err_stat; /* 0x0030 */ |
| 4678d674 | 25 | unsigned char res4[0xc]; |
| f3807374 | 26 | unsigned int int_err_mask; /* 0x0040 */ |
| 4678d674 | 27 | unsigned char res5[0xc]; |
| f3807374 | 28 | unsigned int int_err_ack; /* 0x0050 */ |
| 4678d674 | 29 | unsigned char res6[0xc]; |
| f3807374 | 30 | unsigned int ecc_err_stat; /* 0x0060 */ |
| 4678d674 | 31 | unsigned char res7[0xc]; |
| f3807374 | 32 | unsigned int manufact_id; /* 0x0070 */ |
| 4678d674 | 33 | unsigned char res8[0xc]; |
| f3807374 | 34 | unsigned int device_id; /* 0x0080 */ |
| 4678d674 | 35 | unsigned char res9[0xc]; |
| f3807374 | 36 | unsigned int data_buf_size; /* 0x0090 */ |
| 4678d674 | 37 | unsigned char res10[0xc]; |
| f3807374 | 38 | unsigned int boot_buf_size; /* 0x00A0 */ |
| 4678d674 | 39 | unsigned char res11[0xc]; |
| f3807374 | 40 | unsigned int buf_amount; /* 0x00B0 */ |
| 4678d674 | 41 | unsigned char res12[0xc]; |
| f3807374 | 42 | unsigned int tech; /* 0x00C0 */ |
| 4678d674 | 43 | unsigned char res13[0xc]; |
| f3807374 | 44 | unsigned int fba; /* 0x00D0 */ |
| 4678d674 | 45 | unsigned char res14[0xc]; |
| f3807374 | 46 | unsigned int fpa; /* 0x00E0 */ |
| 4678d674 | 47 | unsigned char res15[0xc]; |
| f3807374 | 48 | unsigned int fsa; /* 0x00F0 */ |
| 4678d674 | 49 | unsigned char res16[0x3c]; |
| f3807374 | 50 | unsigned int sync_mode; /* 0x0130 */ |
| 4678d674 | 51 | unsigned char res17[0xc]; |
| f3807374 | 52 | unsigned int trans_spare; /* 0x0140 */ |
| 4678d674 | 53 | unsigned char res18[0x3c]; |
| f3807374 | 54 | unsigned int err_page_addr; /* 0x0180 */ |
| 4678d674 | 55 | unsigned char res19[0x1c]; |
| f3807374 | 56 | unsigned int int_pin_en; /* 0x01A0 */ |
| 4678d674 | 57 | unsigned char res20[0x1c]; |
| f3807374 | 58 | unsigned int acc_clock; /* 0x01C0 */ |
| 4678d674 | 59 | unsigned char res21[0x1c]; |
| f3807374 | 60 | unsigned int err_blk_addr; /* 0x01E0 */ |
| 4678d674 | 61 | unsigned char res22[0xc]; |
| f3807374 | 62 | unsigned int flash_ver_id; /* 0x01F0 */ |
| 4678d674 | 63 | unsigned char res23[0x6c]; |
| f3807374 | 64 | unsigned int watchdog_cnt_low; /* 0x0260 */ |
| 4678d674 | 65 | unsigned char res24[0xc]; |
| f3807374 | 66 | unsigned int watchdog_cnt_hi; /* 0x0270 */ |
| 4678d674 | 67 | unsigned char res25[0xc]; |
| f3807374 | 68 | unsigned int sync_write; /* 0x0280 */ |
| 4678d674 | 69 | unsigned char res26[0x1c]; |
| f3807374 | 70 | unsigned int cold_reset; /* 0x02A0 */ |
| 4678d674 | 71 | unsigned char res27[0xc]; |
| f3807374 | 72 | unsigned int ddp_device; /* 0x02B0 */ |
| 4678d674 | 73 | unsigned char res28[0xc]; |
| f3807374 | 74 | unsigned int multi_plane; /* 0x02C0 */ |
| 4678d674 | 75 | unsigned char res29[0x1c]; |
| f3807374 | 76 | unsigned int trans_mode; /* 0x02E0 */ |
| 4678d674 | 77 | unsigned char res30[0x1c]; |
| f3807374 | 78 | unsigned int ecc_err_stat2; /* 0x0300 */ |
| 4678d674 | 79 | unsigned char res31[0xc]; |
| f3807374 | 80 | unsigned int ecc_err_stat3; /* 0x0310 */ |
| 4678d674 | 81 | unsigned char res32[0xc]; |
| f3807374 | 82 | unsigned int ecc_err_stat4; /* 0x0320 */ |
| 4678d674 | 83 | unsigned char res33[0x1c]; |
| f3807374 | 84 | unsigned int dev_page_size; /* 0x0340 */ |
| 4678d674 | 85 | unsigned char res34[0x4c]; |
| f3807374 | 86 | unsigned int int_mon_status; /* 0x0390 */ |
| 4678d674 MK |
87 | }; |
| 88 | #endif | |
| 89 | ||
| 90 | #define ONENAND_MEM_RESET_HOT 0x3 | |
| 91 | #define ONENAND_MEM_RESET_COLD 0x2 | |
| 92 | #define ONENAND_MEM_RESET_WARM 0x1 | |
| 93 | ||
| 94 | #define INT_ERR_ALL 0x3fff | |
| 95 | #define CACHE_OP_ERR (1 << 13) | |
| 96 | #define RST_CMP (1 << 12) | |
| 97 | #define RDY_ACT (1 << 11) | |
| 98 | #define INT_ACT (1 << 10) | |
| 99 | #define UNSUP_CMD (1 << 9) | |
| 100 | #define LOCKED_BLK (1 << 8) | |
| 101 | #define BLK_RW_CMP (1 << 7) | |
| 102 | #define ERS_CMP (1 << 6) | |
| 103 | #define PGM_CMP (1 << 5) | |
| 104 | #define LOAD_CMP (1 << 4) | |
| 105 | #define ERS_FAIL (1 << 3) | |
| 106 | #define PGM_FAIL (1 << 2) | |
| 107 | #define INT_TO (1 << 1) | |
| 108 | #define LD_FAIL_ECC_ERR (1 << 0) | |
| 109 | ||
| 110 | #define TSRF (1 << 0) | |
| 111 | ||
| 112 | /* common initialize function */ | |
| 113 | extern void s3c_onenand_init(struct mtd_info *); | |
| 6b3967bb ŁM |
114 | extern int s5pc110_chip_probe(struct mtd_info *); |
| 115 | extern int s5pc210_chip_probe(struct mtd_info *); | |
| 4678d674 MK |
116 | |
| 117 | #endif |