[people/ms/u-boot.git] / include / miiphy.h

/*----------------------------------------------------------------------------+
|   This source code is dual-licensed.  You may use it under the terms of the
|   GNU General Public License version 2, or under the license below.
|
|	This source code has been made available to you by IBM on an AS-IS
|	basis.	Anyone receiving this source is licensed under IBM
|	copyrights to use it in any way he or she deems fit, including
|	copying it, modifying it, compiling it, and redistributing it either
|	with or without modifications.	No license under IBM patents or
|	patent applications is to be implied by the copyright license.
|
|	Any user of this software should understand that IBM cannot provide
|	technical support for this software and will not be responsible for
|	any consequences resulting from the use of this software.
|
|	Any person who transfers this source code or any derivative work
|	must include the IBM copyright notice, this paragraph, and the
|	preceding two paragraphs in the transferred software.
|
|	COPYRIGHT   I B M   CORPORATION 1999
|	LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M
|
|   Additions (C) Copyright 2009 Industrie Dial Face S.p.A.
+----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------+
|
|  File Name:	miiphy.h
|
|  Function:	Include file defining PHY registers.
|
|  Author:	Mark Wisner
|
+----------------------------------------------------------------------------*/
#ifndef _miiphy_h_
#define _miiphy_h_

#include <net.h>

int miiphy_read (const char *devname, unsigned char addr, unsigned char reg,
		 unsigned short *value);
int miiphy_write (const char *devname, unsigned char addr, unsigned char reg,
		  unsigned short value);
int miiphy_info (const char *devname, unsigned char addr, unsigned int *oui,
		 unsigned char *model, unsigned char *rev);
int miiphy_reset (const char *devname, unsigned char addr);
int miiphy_speed (const char *devname, unsigned char addr);
int miiphy_duplex (const char *devname, unsigned char addr);
int miiphy_is_1000base_x (const char *devname, unsigned char addr);
#ifdef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
int miiphy_link (const char *devname, unsigned char addr);
#endif

void miiphy_init (void);

void miiphy_register (const char *devname,
		      int (*read) (const char *devname, unsigned char addr,
				   unsigned char reg, unsigned short *value),
		      int (*write) (const char *devname, unsigned char addr,
				    unsigned char reg, unsigned short value));

int miiphy_set_current_dev (const char *devname);
const char *miiphy_get_current_dev (void);

void miiphy_listdev (void);

#ifdef CONFIG_BITBANGMII

#define BB_MII_DEVNAME	"bb_miiphy"

struct bb_miiphy_bus {
	char name[NAMESIZE];
	int (*init)(struct bb_miiphy_bus *bus);
	int (*mdio_active)(struct bb_miiphy_bus *bus);
	int (*mdio_tristate)(struct bb_miiphy_bus *bus);
	int (*set_mdio)(struct bb_miiphy_bus *bus, int v);
	int (*get_mdio)(struct bb_miiphy_bus *bus, int *v);
	int (*set_mdc)(struct bb_miiphy_bus *bus, int v);
	int (*delay)(struct bb_miiphy_bus *bus);
#ifdef CONFIG_BITBANGMII_MULTI
	void *priv;
#endif
};

extern struct bb_miiphy_bus bb_miiphy_buses[];
extern int bb_miiphy_buses_num;

void bb_miiphy_init (void);
int bb_miiphy_read (const char *devname, unsigned char addr,
		    unsigned char reg, unsigned short *value);
int bb_miiphy_write (const char *devname, unsigned char addr,
		     unsigned char reg, unsigned short value);
#endif

/* phy seed setup */
#define AUTO			99
#define _1000BASET		1000
#define _100BASET		100
#define _10BASET		10
#define HALF			22
#define FULL			44

/* phy register offsets */
#define PHY_BMCR		0x00
#define PHY_BMSR		0x01
#define PHY_PHYIDR1		0x02
#define PHY_PHYIDR2		0x03
#define PHY_ANAR		0x04
#define PHY_ANLPAR		0x05
#define PHY_ANER		0x06
#define PHY_ANNPTR		0x07
#define PHY_ANLPNP		0x08
#define PHY_1000BTCR		0x09
#define PHY_1000BTSR		0x0A
#define PHY_EXSR		0x0F
#define PHY_PHYSTS		0x10
#define PHY_MIPSCR		0x11
#define PHY_MIPGSR		0x12
#define PHY_DCR			0x13
#define PHY_FCSCR		0x14
#define PHY_RECR		0x15
#define PHY_PCSR		0x16
#define PHY_LBR			0x17
#define PHY_10BTSCR		0x18
#define PHY_PHYCTRL		0x19

/* PHY BMCR */
#define PHY_BMCR_RESET		0x8000
#define PHY_BMCR_LOOP		0x4000
#define PHY_BMCR_100MB		0x2000
#define PHY_BMCR_AUTON		0x1000
#define PHY_BMCR_POWD		0x0800
#define PHY_BMCR_ISO		0x0400
#define PHY_BMCR_RST_NEG	0x0200
#define PHY_BMCR_DPLX		0x0100
#define PHY_BMCR_COL_TST	0x0080

#define PHY_BMCR_SPEED_MASK	0x2040
#define PHY_BMCR_1000_MBPS	0x0040
#define PHY_BMCR_100_MBPS	0x2000
#define PHY_BMCR_10_MBPS	0x0000

/* phy BMSR */
#define PHY_BMSR_100T4		0x8000
#define PHY_BMSR_100TXF		0x4000
#define PHY_BMSR_100TXH		0x2000
#define PHY_BMSR_10TF		0x1000
#define PHY_BMSR_10TH		0x0800
#define PHY_BMSR_EXT_STAT	0x0100
#define PHY_BMSR_PRE_SUP	0x0040
#define PHY_BMSR_AUTN_COMP	0x0020
#define PHY_BMSR_RF		0x0010
#define PHY_BMSR_AUTN_ABLE	0x0008
#define PHY_BMSR_LS		0x0004
#define PHY_BMSR_JD		0x0002
#define PHY_BMSR_EXT		0x0001

/*phy ANLPAR */
#define PHY_ANLPAR_NP		0x8000
#define PHY_ANLPAR_ACK		0x4000
#define PHY_ANLPAR_RF		0x2000
#define PHY_ANLPAR_ASYMP	0x0800
#define PHY_ANLPAR_PAUSE	0x0400
#define PHY_ANLPAR_T4		0x0200
#define PHY_ANLPAR_TXFD		0x0100
#define PHY_ANLPAR_TX		0x0080
#define PHY_ANLPAR_10FD		0x0040
#define PHY_ANLPAR_10		0x0020
#define PHY_ANLPAR_100		0x0380	/* we can run at 100 */
/* phy ANLPAR 1000BASE-X */
#define PHY_X_ANLPAR_NP		0x8000
#define PHY_X_ANLPAR_ACK	0x4000
#define PHY_X_ANLPAR_RF_MASK	0x3000
#define PHY_X_ANLPAR_PAUSE_MASK	0x0180
#define PHY_X_ANLPAR_HD		0x0040
#define PHY_X_ANLPAR_FD		0x0020

#define PHY_ANLPAR_PSB_MASK	0x001f
#define PHY_ANLPAR_PSB_802_3	0x0001
#define PHY_ANLPAR_PSB_802_9	0x0002

/* phy 1000BTCR */
#define PHY_1000BTCR_1000FD	0x0200
#define PHY_1000BTCR_1000HD	0x0100

/* phy 1000BTSR */
#define PHY_1000BTSR_MSCF	0x8000
#define PHY_1000BTSR_MSCR	0x4000
#define PHY_1000BTSR_LRS	0x2000
#define PHY_1000BTSR_RRS	0x1000
#define PHY_1000BTSR_1000FD	0x0800
#define PHY_1000BTSR_1000HD	0x0400

/* phy EXSR */
#define PHY_EXSR_1000XF		0x8000
#define PHY_EXSR_1000XH		0x4000
#define PHY_EXSR_1000TF		0x2000
#define PHY_EXSR_1000TH		0x1000

#endif
Commit	Line	Data
214ec6bb	1	/*----------------------------------------------------------------------------+
31773496 JB	2	\| This source code is dual-licensed. You may use it under the terms of the
31773496 JB	3	\| GNU General Public License version 2, or under the license below.
214ec6bb	4	\|
65bd0e28 WD	5	\| This source code has been made available to you by IBM on an AS-IS
	6	\| basis. Anyone receiving this source is licensed under IBM
	7	\| copyrights to use it in any way he or she deems fit, including
	8	\| copying it, modifying it, compiling it, and redistributing it either
	9	\| with or without modifications. No license under IBM patents or
	10	\| patent applications is to be implied by the copyright license.
214ec6bb	11	\|
65bd0e28 WD	12	\| Any user of this software should understand that IBM cannot provide
	13	\| technical support for this software and will not be responsible for
	14	\| any consequences resulting from the use of this software.
214ec6bb	15	\|
65bd0e28 WD	16	\| Any person who transfers this source code or any derivative work
	17	\| must include the IBM copyright notice, this paragraph, and the
	18	\| preceding two paragraphs in the transferred software.
214ec6bb	19	\|
65bd0e28 WD	20	\| COPYRIGHT I B M CORPORATION 1999
65bd0e28 WD	21	\| LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
4ba31ab3 LCM	22	\|
4ba31ab3 LCM	23	\| Additions (C) Copyright 2009 Industrie Dial Face S.p.A.
214ec6bb WD	24	+----------------------------------------------------------------------------*/
	25	/*----------------------------------------------------------------------------+
	26	\|
65bd0e28	27	\| File Name: miiphy.h
214ec6bb	28	\|
65bd0e28	29	\| Function: Include file defining PHY registers.
214ec6bb	30	\|
65bd0e28	31	\| Author: Mark Wisner
214ec6bb	32	\|
214ec6bb WD	33	+----------------------------------------------------------------------------*/
	34	#ifndef _miiphy_h_
	35	#define _miiphy_h_
	36
63ff004c	37	#include <net.h>
214ec6bb	38
5700bb63	39	int miiphy_read (const char *devname, unsigned char addr, unsigned char reg,
298035df	40	unsigned short *value);
5700bb63	41	int miiphy_write (const char *devname, unsigned char addr, unsigned char reg,
298035df	42	unsigned short value);
5700bb63	43	int miiphy_info (const char devname, unsigned char addr, unsigned int oui,
298035df	44	unsigned char model, unsigned char rev);
5700bb63 MF	45	int miiphy_reset (const char *devname, unsigned char addr);
	46	int miiphy_speed (const char *devname, unsigned char addr);
	47	int miiphy_duplex (const char *devname, unsigned char addr);
	48	int miiphy_is_1000base_x (const char *devname, unsigned char addr);
6d0f6bcf	49	#ifdef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
5700bb63	50	int miiphy_link (const char *devname, unsigned char addr);
fc3e2165	51	#endif
214ec6bb	52
298035df	53	void miiphy_init (void);
d9785c14	54
5700bb63 MF	55	void miiphy_register (const char *devname,
5700bb63 MF	56	int (read) (const char devname, unsigned char addr,
298035df	57	unsigned char reg, unsigned short *value),
5700bb63	58	int (write) (const char devname, unsigned char addr,
298035df	59	unsigned char reg, unsigned short value));
63ff004c	60
5700bb63 MF	61	int miiphy_set_current_dev (const char *devname);
5700bb63 MF	62	const char *miiphy_get_current_dev (void);
63ff004c	63
298035df	64	void miiphy_listdev (void);
63ff004c	65
4ba31ab3 LCM	66	#ifdef CONFIG_BITBANGMII
	67
	68	#define BB_MII_DEVNAME "bb_miiphy"
	69
	70	struct bb_miiphy_bus {
	71	char name[NAMESIZE];
	72	int (init)(struct bb_miiphy_bus bus);
	73	int (mdio_active)(struct bb_miiphy_bus bus);
	74	int (mdio_tristate)(struct bb_miiphy_bus bus);
	75	int (set_mdio)(struct bb_miiphy_bus bus, int v);
	76	int (get_mdio)(struct bb_miiphy_bus bus, int *v);
	77	int (set_mdc)(struct bb_miiphy_bus bus, int v);
	78	int (delay)(struct bb_miiphy_bus bus);
	79	#ifdef CONFIG_BITBANGMII_MULTI
	80	void *priv;
	81	#endif
	82	};
	83
	84	extern struct bb_miiphy_bus bb_miiphy_buses[];
	85	extern int bb_miiphy_buses_num;
63ff004c	86
4ba31ab3	87	void bb_miiphy_init (void);
5700bb63	88	int bb_miiphy_read (const char *devname, unsigned char addr,
298035df	89	unsigned char reg, unsigned short *value);
5700bb63	90	int bb_miiphy_write (const char *devname, unsigned char addr,
298035df	91	unsigned char reg, unsigned short value);
4ba31ab3	92	#endif
214ec6bb WD	93
214ec6bb WD	94	/* phy seed setup */
65bd0e28	95	#define AUTO 99
298035df	96	#define _1000BASET 1000
65bd0e28 WD	97	#define _100BASET 100
	98	#define _10BASET 10
	99	#define HALF 22
	100	#define FULL 44
214ec6bb WD	101
214ec6bb WD	102	/* phy register offsets */
65bd0e28	103	#define PHY_BMCR 0x00
214ec6bb	104	#define PHY_BMSR 0x01
65bd0e28 WD	105	#define PHY_PHYIDR1 0x02
65bd0e28 WD	106	#define PHY_PHYIDR2 0x03
214ec6bb	107	#define PHY_ANAR 0x04
65bd0e28	108	#define PHY_ANLPAR 0x05
214ec6bb	109	#define PHY_ANER 0x06
65bd0e28	110	#define PHY_ANNPTR 0x07
298035df LJ	111	#define PHY_ANLPNP 0x08
	112	#define PHY_1000BTCR 0x09
	113	#define PHY_1000BTSR 0x0A
71bc6e64	114	#define PHY_EXSR 0x0F
65bd0e28 WD	115	#define PHY_PHYSTS 0x10
	116	#define PHY_MIPSCR 0x11
	117	#define PHY_MIPGSR 0x12
	118	#define PHY_DCR 0x13
214ec6bb WD	119	#define PHY_FCSCR 0x14
	120	#define PHY_RECR 0x15
	121	#define PHY_PCSR 0x16
65bd0e28 WD	122	#define PHY_LBR 0x17
	123	#define PHY_10BTSCR 0x18
	124	#define PHY_PHYCTRL 0x19
214ec6bb WD	125
214ec6bb WD	126	/* PHY BMCR */
65bd0e28 WD	127	#define PHY_BMCR_RESET 0x8000
65bd0e28 WD	128	#define PHY_BMCR_LOOP 0x4000
214ec6bb WD	129	#define PHY_BMCR_100MB 0x2000
	130	#define PHY_BMCR_AUTON 0x1000
	131	#define PHY_BMCR_POWD 0x0800
	132	#define PHY_BMCR_ISO 0x0400
	133	#define PHY_BMCR_RST_NEG 0x0200
	134	#define PHY_BMCR_DPLX 0x0100
	135	#define PHY_BMCR_COL_TST 0x0080
	136
298035df LJ	137	#define PHY_BMCR_SPEED_MASK 0x2040
	138	#define PHY_BMCR_1000_MBPS 0x0040
	139	#define PHY_BMCR_100_MBPS 0x2000
	140	#define PHY_BMCR_10_MBPS 0x0000
b9711de1	141
214ec6bb WD	142	/* phy BMSR */
	143	#define PHY_BMSR_100T4 0x8000
	144	#define PHY_BMSR_100TXF 0x4000
	145	#define PHY_BMSR_100TXH 0x2000
	146	#define PHY_BMSR_10TF 0x1000
	147	#define PHY_BMSR_10TH 0x0800
71bc6e64	148	#define PHY_BMSR_EXT_STAT 0x0100
214ec6bb WD	149	#define PHY_BMSR_PRE_SUP 0x0040
	150	#define PHY_BMSR_AUTN_COMP 0x0020
	151	#define PHY_BMSR_RF 0x0010
	152	#define PHY_BMSR_AUTN_ABLE 0x0008
	153	#define PHY_BMSR_LS 0x0004
	154	#define PHY_BMSR_JD 0x0002
	155	#define PHY_BMSR_EXT 0x0001
	156
	157	/phy ANLPAR /
	158	#define PHY_ANLPAR_NP 0x8000
	159	#define PHY_ANLPAR_ACK 0x4000
65bd0e28	160	#define PHY_ANLPAR_RF 0x2000
71bc6e64 LJ	161	#define PHY_ANLPAR_ASYMP 0x0800
71bc6e64 LJ	162	#define PHY_ANLPAR_PAUSE 0x0400
65bd0e28 WD	163	#define PHY_ANLPAR_T4 0x0200
	164	#define PHY_ANLPAR_TXFD 0x0100
	165	#define PHY_ANLPAR_TX 0x0080
214ec6bb	166	#define PHY_ANLPAR_10FD 0x0040
65bd0e28	167	#define PHY_ANLPAR_10 0x0020
298035df	168	#define PHY_ANLPAR_100 0x0380 /* we can run at 100 */
71bc6e64 LJ	169	/* phy ANLPAR 1000BASE-X */
	170	#define PHY_X_ANLPAR_NP 0x8000
	171	#define PHY_X_ANLPAR_ACK 0x4000
	172	#define PHY_X_ANLPAR_RF_MASK 0x3000
	173	#define PHY_X_ANLPAR_PAUSE_MASK 0x0180
	174	#define PHY_X_ANLPAR_HD 0x0040
	175	#define PHY_X_ANLPAR_FD 0x0020
298035df LJ	176
	177	#define PHY_ANLPAR_PSB_MASK 0x001f
	178	#define PHY_ANLPAR_PSB_802_3 0x0001
	179	#define PHY_ANLPAR_PSB_802_9 0x0002
	180
71bc6e64 LJ	181	/* phy 1000BTCR */
	182	#define PHY_1000BTCR_1000FD 0x0200
	183	#define PHY_1000BTCR_1000HD 0x0100
	184
298035df LJ	185	/* phy 1000BTSR */
	186	#define PHY_1000BTSR_MSCF 0x8000
	187	#define PHY_1000BTSR_MSCR 0x4000
	188	#define PHY_1000BTSR_LRS 0x2000
	189	#define PHY_1000BTSR_RRS 0x1000
	190	#define PHY_1000BTSR_1000FD 0x0800
	191	#define PHY_1000BTSR_1000HD 0x0400
855a496f	192
71bc6e64 LJ	193	/* phy EXSR */
	194	#define PHY_EXSR_1000XF 0x8000
	195	#define PHY_EXSR_1000XH 0x4000
	196	#define PHY_EXSR_1000TF 0x2000
	197	#define PHY_EXSR_1000TH 0x1000
	198
214ec6bb	199	#endif