[people/ms/u-boot.git] / include / mmc.h

/*
 * Copyright 2008,2010 Freescale Semiconductor, Inc
 * Andy Fleming
 *
 * Based (loosely) on the Linux code
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef _MMC_H_
#define _MMC_H_

#include <linux/list.h>

#define SD_VERSION_SD	0x20000
#define SD_VERSION_2	(SD_VERSION_SD | 0x20)
#define SD_VERSION_1_0	(SD_VERSION_SD | 0x10)
#define SD_VERSION_1_10	(SD_VERSION_SD | 0x1a)
#define MMC_VERSION_MMC		0x10000
#define MMC_VERSION_UNKNOWN	(MMC_VERSION_MMC)
#define MMC_VERSION_1_2		(MMC_VERSION_MMC | 0x12)
#define MMC_VERSION_1_4		(MMC_VERSION_MMC | 0x14)
#define MMC_VERSION_2_2		(MMC_VERSION_MMC | 0x22)
#define MMC_VERSION_3		(MMC_VERSION_MMC | 0x30)
#define MMC_VERSION_4		(MMC_VERSION_MMC | 0x40)

#define MMC_MODE_HS		0x001
#define MMC_MODE_HS_52MHz	0x010
#define MMC_MODE_4BIT		0x100
#define MMC_MODE_8BIT		0x200
#define MMC_MODE_SPI		0x400

#define SD_DATA_4BIT	0x00040000

#define IS_SD(x) (x->version & SD_VERSION_SD)

#define MMC_DATA_READ		1
#define MMC_DATA_WRITE		2

#define NO_CARD_ERR		-16 /* No SD/MMC card inserted */
#define UNUSABLE_ERR		-17 /* Unusable Card */
#define COMM_ERR		-18 /* Communications Error */
#define TIMEOUT			-19

#define MMC_CMD_GO_IDLE_STATE		0
#define MMC_CMD_SEND_OP_COND		1
#define MMC_CMD_ALL_SEND_CID		2
#define MMC_CMD_SET_RELATIVE_ADDR	3
#define MMC_CMD_SET_DSR			4
#define MMC_CMD_SWITCH			6
#define MMC_CMD_SELECT_CARD		7
#define MMC_CMD_SEND_EXT_CSD		8
#define MMC_CMD_SEND_CSD		9
#define MMC_CMD_SEND_CID		10
#define MMC_CMD_STOP_TRANSMISSION	12
#define MMC_CMD_SEND_STATUS		13
#define MMC_CMD_SET_BLOCKLEN		16
#define MMC_CMD_READ_SINGLE_BLOCK	17
#define MMC_CMD_READ_MULTIPLE_BLOCK	18
#define MMC_CMD_WRITE_SINGLE_BLOCK	24
#define MMC_CMD_WRITE_MULTIPLE_BLOCK	25
#define MMC_CMD_APP_CMD			55
#define MMC_CMD_SPI_READ_OCR		58
#define MMC_CMD_SPI_CRC_ON_OFF		59

#define SD_CMD_SEND_RELATIVE_ADDR	3
#define SD_CMD_SWITCH_FUNC		6
#define SD_CMD_SEND_IF_COND		8

#define SD_CMD_APP_SET_BUS_WIDTH	6
#define SD_CMD_APP_SEND_OP_COND		41
#define SD_CMD_APP_SEND_SCR		51

/* SCR definitions in different words */
#define SD_HIGHSPEED_BUSY	0x00020000
#define SD_HIGHSPEED_SUPPORTED	0x00020000

#define MMC_HS_TIMING		0x00000100
#define MMC_HS_52MHZ		0x2

#define OCR_BUSY		0x80000000
#define OCR_HCS			0x40000000
#define OCR_VOLTAGE_MASK	0x007FFF80
#define OCR_ACCESS_MODE		0x60000000

#define MMC_STATUS_MASK		(~0x0206BF7F)
#define MMC_STATUS_RDY_FOR_DATA (1 << 8)
#define MMC_STATUS_CURR_STATE	(0xf << 9)
#define MMC_STATUS_ERROR	(1 << 19)

#define MMC_VDD_165_195		0x00000080	/* VDD voltage 1.65 - 1.95 */
#define MMC_VDD_20_21		0x00000100	/* VDD voltage 2.0 ~ 2.1 */
#define MMC_VDD_21_22		0x00000200	/* VDD voltage 2.1 ~ 2.2 */
#define MMC_VDD_22_23		0x00000400	/* VDD voltage 2.2 ~ 2.3 */
#define MMC_VDD_23_24		0x00000800	/* VDD voltage 2.3 ~ 2.4 */
#define MMC_VDD_24_25		0x00001000	/* VDD voltage 2.4 ~ 2.5 */
#define MMC_VDD_25_26		0x00002000	/* VDD voltage 2.5 ~ 2.6 */
#define MMC_VDD_26_27		0x00004000	/* VDD voltage 2.6 ~ 2.7 */
#define MMC_VDD_27_28		0x00008000	/* VDD voltage 2.7 ~ 2.8 */
#define MMC_VDD_28_29		0x00010000	/* VDD voltage 2.8 ~ 2.9 */
#define MMC_VDD_29_30		0x00020000	/* VDD voltage 2.9 ~ 3.0 */
#define MMC_VDD_30_31		0x00040000	/* VDD voltage 3.0 ~ 3.1 */
#define MMC_VDD_31_32		0x00080000	/* VDD voltage 3.1 ~ 3.2 */
#define MMC_VDD_32_33		0x00100000	/* VDD voltage 3.2 ~ 3.3 */
#define MMC_VDD_33_34		0x00200000	/* VDD voltage 3.3 ~ 3.4 */
#define MMC_VDD_34_35		0x00400000	/* VDD voltage 3.4 ~ 3.5 */
#define MMC_VDD_35_36		0x00800000	/* VDD voltage 3.5 ~ 3.6 */

#define MMC_SWITCH_MODE_CMD_SET		0x00 /* Change the command set */
#define MMC_SWITCH_MODE_SET_BITS	0x01 /* Set bits in EXT_CSD byte
						addressed by index which are
						1 in value field */
#define MMC_SWITCH_MODE_CLEAR_BITS	0x02 /* Clear bits in EXT_CSD byte
						addressed by index, which are
						1 in value field */
#define MMC_SWITCH_MODE_WRITE_BYTE	0x03 /* Set target byte to value */

#define SD_SWITCH_CHECK		0
#define SD_SWITCH_SWITCH	1

/*
 * EXT_CSD fields
 */

#define EXT_CSD_BUS_WIDTH	183	/* R/W */
#define EXT_CSD_HS_TIMING	185	/* R/W */
#define EXT_CSD_CARD_TYPE	196	/* RO */
#define EXT_CSD_REV		192	/* RO */
#define EXT_CSD_SEC_CNT		212	/* RO, 4 bytes */

/*
 * EXT_CSD field definitions
 */

#define EXT_CSD_CMD_SET_NORMAL		(1 << 0)
#define EXT_CSD_CMD_SET_SECURE		(1 << 1)
#define EXT_CSD_CMD_SET_CPSECURE	(1 << 2)

#define EXT_CSD_CARD_TYPE_26	(1 << 0)	/* Card can run at 26MHz */
#define EXT_CSD_CARD_TYPE_52	(1 << 1)	/* Card can run at 52MHz */

#define EXT_CSD_BUS_WIDTH_1	0	/* Card is in 1 bit mode */
#define EXT_CSD_BUS_WIDTH_4	1	/* Card is in 4 bit mode */
#define EXT_CSD_BUS_WIDTH_8	2	/* Card is in 8 bit mode */

#define R1_ILLEGAL_COMMAND		(1 << 22)
#define R1_APP_CMD			(1 << 5)

#define MMC_RSP_PRESENT (1 << 0)
#define MMC_RSP_136	(1 << 1)		/* 136 bit response */
#define MMC_RSP_CRC	(1 << 2)		/* expect valid crc */
#define MMC_RSP_BUSY	(1 << 3)		/* card may send busy */
#define MMC_RSP_OPCODE	(1 << 4)		/* response contains opcode */

#define MMC_RSP_NONE	(0)
#define MMC_RSP_R1	(MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
#define MMC_RSP_R1b	(MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE| \
			MMC_RSP_BUSY)
#define MMC_RSP_R2	(MMC_RSP_PRESENT|MMC_RSP_136|MMC_RSP_CRC)
#define MMC_RSP_R3	(MMC_RSP_PRESENT)
#define MMC_RSP_R4	(MMC_RSP_PRESENT)
#define MMC_RSP_R5	(MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
#define MMC_RSP_R6	(MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
#define MMC_RSP_R7	(MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)


struct mmc_cid {
	unsigned long psn;
	unsigned short oid;
	unsigned char mid;
	unsigned char prv;
	unsigned char mdt;
	char pnm[7];
};

/*
 * WARNING!
 *
 * This structure is used by atmel_mci.c only.
 * It works for the AVR32 architecture but NOT
 * for ARM/AT91 architectures.
 * Its use is highly depreciated.
 * After the atmel_mci.c driver for AVR32 has
 * been replaced this structure will be removed.
 */
struct mmc_csd
{
	u8	csd_structure:2,
		spec_vers:4,
		rsvd1:2;
	u8	taac;
	u8	nsac;
	u8	tran_speed;
	u16	ccc:12,
		read_bl_len:4;
	u64	read_bl_partial:1,
		write_blk_misalign:1,
		read_blk_misalign:1,
		dsr_imp:1,
		rsvd2:2,
		c_size:12,
		vdd_r_curr_min:3,
		vdd_r_curr_max:3,
		vdd_w_curr_min:3,
		vdd_w_curr_max:3,
		c_size_mult:3,
		sector_size:5,
		erase_grp_size:5,
		wp_grp_size:5,
		wp_grp_enable:1,
		default_ecc:2,
		r2w_factor:3,
		write_bl_len:4,
		write_bl_partial:1,
		rsvd3:5;
	u8	file_format_grp:1,
		copy:1,
		perm_write_protect:1,
		tmp_write_protect:1,
		file_format:2,
		ecc:2;
	u8	crc:7;
	u8	one:1;
};

struct mmc_cmd {
	ushort cmdidx;
	uint resp_type;
	uint cmdarg;
	uint response[4];
	uint flags;
};

struct mmc_data {
	union {
		char *dest;
		const char *src; /* src buffers don't get written to */
	};
	uint flags;
	uint blocks;
	uint blocksize;
};

struct mmc {
	struct list_head link;
	char name[32];
	void *priv;
	uint voltages;
	uint version;
	uint f_min;
	uint f_max;
	int high_capacity;
	uint bus_width;
	uint clock;
	uint card_caps;
	uint host_caps;
	uint ocr;
	uint scr[2];
	uint csd[4];
	uint cid[4];
	ushort rca;
	uint tran_speed;
	uint read_bl_len;
	uint write_bl_len;
	u64 capacity;
	block_dev_desc_t block_dev;
	int (*send_cmd)(struct mmc *mmc,
			struct mmc_cmd *cmd, struct mmc_data *data);
	void (*set_ios)(struct mmc *mmc);
	int (*init)(struct mmc *mmc);
	uint b_max;
};

int mmc_register(struct mmc *mmc);
int mmc_initialize(bd_t *bis);
int mmc_init(struct mmc *mmc);
int mmc_read(struct mmc *mmc, u64 src, uchar *dst, int size);
void mmc_set_clock(struct mmc *mmc, uint clock);
struct mmc *find_mmc_device(int dev_num);
int mmc_set_dev(int dev_num);
void print_mmc_devices(char separator);
int get_mmc_num(void);
int board_mmc_getcd(u8 *cd, struct mmc *mmc);

#ifdef CONFIG_GENERIC_MMC
int atmel_mci_init(void *regs);
#define mmc_host_is_spi(mmc)	((mmc)->host_caps & MMC_MODE_SPI)
struct mmc *mmc_spi_init(uint bus, uint cs, uint speed, uint mode);
#else
int mmc_legacy_init(int verbose);
#endif

#endif /* _MMC_H_ */
Commit	Line	Data
71f95118	1	/*
4a6ee172	2	* Copyright 2008,2010 Freescale Semiconductor, Inc
272cc70b AF	3	* Andy Fleming
	4	*
	5	* Based (loosely) on the Linux code
71f95118 WD	6	*
	7	* See file CREDITS for list of people who contributed to this
	8	* project.
	9	*
	10	* This program is free software; you can redistribute it and/or
	11	* modify it under the terms of the GNU General Public License as
	12	* published by the Free Software Foundation; either version 2 of
	13	* the License, or (at your option) any later version.
	14	*
	15	* This program is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
abe2c93f	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
71f95118 WD	18	* GNU General Public License for more details.
	19	*
	20	* You should have received a copy of the GNU General Public License
	21	* along with this program; if not, write to the Free Software
	22	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	23	* MA 02111-1307 USA
	24	*/
	25
	26	#ifndef _MMC_H_
	27	#define _MMC_H_
71f95118	28
272cc70b AF	29	#include <linux/list.h>
	30
	31	#define SD_VERSION_SD 0x20000
	32	#define SD_VERSION_2 (SD_VERSION_SD \| 0x20)
	33	#define SD_VERSION_1_0 (SD_VERSION_SD \| 0x10)
	34	#define SD_VERSION_1_10 (SD_VERSION_SD \| 0x1a)
	35	#define MMC_VERSION_MMC 0x10000
	36	#define MMC_VERSION_UNKNOWN (MMC_VERSION_MMC)
	37	#define MMC_VERSION_1_2 (MMC_VERSION_MMC \| 0x12)
	38	#define MMC_VERSION_1_4 (MMC_VERSION_MMC \| 0x14)
	39	#define MMC_VERSION_2_2 (MMC_VERSION_MMC \| 0x22)
	40	#define MMC_VERSION_3 (MMC_VERSION_MMC \| 0x30)
	41	#define MMC_VERSION_4 (MMC_VERSION_MMC \| 0x40)
	42
	43	#define MMC_MODE_HS 0x001
	44	#define MMC_MODE_HS_52MHz 0x010
	45	#define MMC_MODE_4BIT 0x100
	46	#define MMC_MODE_8BIT 0x200
d52ebf10	47	#define MMC_MODE_SPI 0x400
272cc70b AF	48
	49	#define SD_DATA_4BIT 0x00040000
	50
79b91de9	51	#define IS_SD(x) (x->version & SD_VERSION_SD)
272cc70b AF	52
	53	#define MMC_DATA_READ 1
	54	#define MMC_DATA_WRITE 2
	55
	56	#define NO_CARD_ERR -16 /* No SD/MMC card inserted */
	57	#define UNUSABLE_ERR -17 /* Unusable Card */
	58	#define COMM_ERR -18 /* Communications Error */
	59	#define TIMEOUT -19
	60
341188b9 HS	61	#define MMC_CMD_GO_IDLE_STATE 0
	62	#define MMC_CMD_SEND_OP_COND 1
	63	#define MMC_CMD_ALL_SEND_CID 2
	64	#define MMC_CMD_SET_RELATIVE_ADDR 3
	65	#define MMC_CMD_SET_DSR 4
272cc70b	66	#define MMC_CMD_SWITCH 6
341188b9	67	#define MMC_CMD_SELECT_CARD 7
272cc70b	68	#define MMC_CMD_SEND_EXT_CSD 8
341188b9 HS	69	#define MMC_CMD_SEND_CSD 9
341188b9 HS	70	#define MMC_CMD_SEND_CID 10
272cc70b	71	#define MMC_CMD_STOP_TRANSMISSION 12
341188b9 HS	72	#define MMC_CMD_SEND_STATUS 13
	73	#define MMC_CMD_SET_BLOCKLEN 16
	74	#define MMC_CMD_READ_SINGLE_BLOCK 17
	75	#define MMC_CMD_READ_MULTIPLE_BLOCK 18
272cc70b AF	76	#define MMC_CMD_WRITE_SINGLE_BLOCK 24
272cc70b AF	77	#define MMC_CMD_WRITE_MULTIPLE_BLOCK 25
341188b9	78	#define MMC_CMD_APP_CMD 55
d52ebf10 TC	79	#define MMC_CMD_SPI_READ_OCR 58
d52ebf10 TC	80	#define MMC_CMD_SPI_CRC_ON_OFF 59
341188b9	81
341188b9	82	#define SD_CMD_SEND_RELATIVE_ADDR 3
272cc70b	83	#define SD_CMD_SWITCH_FUNC 6
341188b9 HS	84	#define SD_CMD_SEND_IF_COND 8
	85
	86	#define SD_CMD_APP_SET_BUS_WIDTH 6
	87	#define SD_CMD_APP_SEND_OP_COND 41
272cc70b AF	88	#define SD_CMD_APP_SEND_SCR 51
	89
	90	/* SCR definitions in different words */
	91	#define SD_HIGHSPEED_BUSY 0x00020000
	92	#define SD_HIGHSPEED_SUPPORTED 0x00020000
	93
	94	#define MMC_HS_TIMING 0x00000100
	95	#define MMC_HS_52MHZ 0x2
	96
abe2c93f TC	97	#define OCR_BUSY 0x80000000
abe2c93f TC	98	#define OCR_HCS 0x40000000
31cacbab RR	99	#define OCR_VOLTAGE_MASK 0x007FFF80
31cacbab RR	100	#define OCR_ACCESS_MODE 0x60000000
272cc70b	101
5d4fc8d9	102	#define MMC_STATUS_MASK (~0x0206BF7F)
abe2c93f TC	103	#define MMC_STATUS_RDY_FOR_DATA (1 << 8)
abe2c93f TC	104	#define MMC_STATUS_CURR_STATE (0xf << 9)
ed018b21	105	#define MMC_STATUS_ERROR (1 << 19)
5d4fc8d9	106
272cc70b AF	107	#define MMC_VDD_165_195 0x00000080 /* VDD voltage 1.65 - 1.95 */
	108	#define MMC_VDD_20_21 0x00000100 /* VDD voltage 2.0 ~ 2.1 */
	109	#define MMC_VDD_21_22 0x00000200 /* VDD voltage 2.1 ~ 2.2 */
	110	#define MMC_VDD_22_23 0x00000400 /* VDD voltage 2.2 ~ 2.3 */
	111	#define MMC_VDD_23_24 0x00000800 /* VDD voltage 2.3 ~ 2.4 */
	112	#define MMC_VDD_24_25 0x00001000 /* VDD voltage 2.4 ~ 2.5 */
	113	#define MMC_VDD_25_26 0x00002000 /* VDD voltage 2.5 ~ 2.6 */
	114	#define MMC_VDD_26_27 0x00004000 /* VDD voltage 2.6 ~ 2.7 */
	115	#define MMC_VDD_27_28 0x00008000 /* VDD voltage 2.7 ~ 2.8 */
	116	#define MMC_VDD_28_29 0x00010000 /* VDD voltage 2.8 ~ 2.9 */
	117	#define MMC_VDD_29_30 0x00020000 /* VDD voltage 2.9 ~ 3.0 */
	118	#define MMC_VDD_30_31 0x00040000 /* VDD voltage 3.0 ~ 3.1 */
	119	#define MMC_VDD_31_32 0x00080000 /* VDD voltage 3.1 ~ 3.2 */
	120	#define MMC_VDD_32_33 0x00100000 /* VDD voltage 3.2 ~ 3.3 */
	121	#define MMC_VDD_33_34 0x00200000 /* VDD voltage 3.3 ~ 3.4 */
	122	#define MMC_VDD_34_35 0x00400000 /* VDD voltage 3.4 ~ 3.5 */
	123	#define MMC_VDD_35_36 0x00800000 /* VDD voltage 3.5 ~ 3.6 */
	124
	125	#define MMC_SWITCH_MODE_CMD_SET 0x00 /* Change the command set */
	126	#define MMC_SWITCH_MODE_SET_BITS 0x01 /* Set bits in EXT_CSD byte
	127	addressed by index which are
	128	1 in value field */
	129	#define MMC_SWITCH_MODE_CLEAR_BITS 0x02 /* Clear bits in EXT_CSD byte
	130	addressed by index, which are
	131	1 in value field */
	132	#define MMC_SWITCH_MODE_WRITE_BYTE 0x03 /* Set target byte to value */
	133
	134	#define SD_SWITCH_CHECK 0
	135	#define SD_SWITCH_SWITCH 1
	136
	137	/*
	138	* EXT_CSD fields
	139	*/
	140
	141	#define EXT_CSD_BUS_WIDTH 183 /* R/W */
	142	#define EXT_CSD_HS_TIMING 185 /* R/W */
	143	#define EXT_CSD_CARD_TYPE 196 /* RO */
	144	#define EXT_CSD_REV 192 /* RO */
	145	#define EXT_CSD_SEC_CNT 212 /* RO, 4 bytes */
	146
	147	/*
	148	* EXT_CSD field definitions
	149	*/
	150
abe2c93f TC	151	#define EXT_CSD_CMD_SET_NORMAL (1 << 0)
	152	#define EXT_CSD_CMD_SET_SECURE (1 << 1)
	153	#define EXT_CSD_CMD_SET_CPSECURE (1 << 2)
272cc70b	154
abe2c93f TC	155	#define EXT_CSD_CARD_TYPE_26 (1 << 0) /* Card can run at 26MHz */
abe2c93f TC	156	#define EXT_CSD_CARD_TYPE_52 (1 << 1) /* Card can run at 52MHz */
272cc70b AF	157
	158	#define EXT_CSD_BUS_WIDTH_1 0 /* Card is in 1 bit mode */
	159	#define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */
	160	#define EXT_CSD_BUS_WIDTH_8 2 /* Card is in 8 bit mode */
341188b9	161
1de97f98 AF	162	#define R1_ILLEGAL_COMMAND (1 << 22)
	163	#define R1_APP_CMD (1 << 5)
	164
272cc70b	165	#define MMC_RSP_PRESENT (1 << 0)
abe2c93f TC	166	#define MMC_RSP_136 (1 << 1) /* 136 bit response */
	167	#define MMC_RSP_CRC (1 << 2) /* expect valid crc */
	168	#define MMC_RSP_BUSY (1 << 3) /* card may send busy */
	169	#define MMC_RSP_OPCODE (1 << 4) /* response contains opcode */
272cc70b	170
abe2c93f TC	171	#define MMC_RSP_NONE (0)
abe2c93f TC	172	#define MMC_RSP_R1 (MMC_RSP_PRESENT\|MMC_RSP_CRC\|MMC_RSP_OPCODE)
272cc70b AF	173	#define MMC_RSP_R1b (MMC_RSP_PRESENT\|MMC_RSP_CRC\|MMC_RSP_OPCODE\| \
272cc70b AF	174	MMC_RSP_BUSY)
abe2c93f TC	175	#define MMC_RSP_R2 (MMC_RSP_PRESENT\|MMC_RSP_136\|MMC_RSP_CRC)
	176	#define MMC_RSP_R3 (MMC_RSP_PRESENT)
	177	#define MMC_RSP_R4 (MMC_RSP_PRESENT)
	178	#define MMC_RSP_R5 (MMC_RSP_PRESENT\|MMC_RSP_CRC\|MMC_RSP_OPCODE)
	179	#define MMC_RSP_R6 (MMC_RSP_PRESENT\|MMC_RSP_CRC\|MMC_RSP_OPCODE)
	180	#define MMC_RSP_R7 (MMC_RSP_PRESENT\|MMC_RSP_CRC\|MMC_RSP_OPCODE)
272cc70b	181
71f95118	182
1de97f98 AF	183	struct mmc_cid {
	184	unsigned long psn;
	185	unsigned short oid;
	186	unsigned char mid;
	187	unsigned char prv;
	188	unsigned char mdt;
	189	char pnm[7];
	190	};
	191
1592ef85 RM	192	/*
	193	* WARNING!
	194	*
	195	* This structure is used by atmel_mci.c only.
	196	* It works for the AVR32 architecture but NOT
	197	* for ARM/AT91 architectures.
	198	* Its use is highly depreciated.
	199	* After the atmel_mci.c driver for AVR32 has
	200	* been replaced this structure will be removed.
	201	*/
1de97f98 AF	202	struct mmc_csd
	203	{
	204	u8 csd_structure:2,
	205	spec_vers:4,
	206	rsvd1:2;
	207	u8 taac;
	208	u8 nsac;
	209	u8 tran_speed;
	210	u16 ccc:12,
	211	read_bl_len:4;
	212	u64 read_bl_partial:1,
	213	write_blk_misalign:1,
	214	read_blk_misalign:1,
	215	dsr_imp:1,
	216	rsvd2:2,
	217	c_size:12,
	218	vdd_r_curr_min:3,
	219	vdd_r_curr_max:3,
	220	vdd_w_curr_min:3,
	221	vdd_w_curr_max:3,
	222	c_size_mult:3,
	223	sector_size:5,
	224	erase_grp_size:5,
	225	wp_grp_size:5,
	226	wp_grp_enable:1,
	227	default_ecc:2,
	228	r2w_factor:3,
	229	write_bl_len:4,
	230	write_bl_partial:1,
	231	rsvd3:5;
	232	u8 file_format_grp:1,
	233	copy:1,
	234	perm_write_protect:1,
	235	tmp_write_protect:1,
	236	file_format:2,
	237	ecc:2;
	238	u8 crc:7;
	239	u8 one:1;
	240	};
	241
272cc70b AF	242	struct mmc_cmd {
	243	ushort cmdidx;
	244	uint resp_type;
	245	uint cmdarg;
0b453ffe	246	uint response[4];
272cc70b AF	247	uint flags;
	248	};
	249
	250	struct mmc_data {
	251	union {
	252	char *dest;
	253	const char src; / src buffers don't get written to */
	254	};
	255	uint flags;
	256	uint blocks;
	257	uint blocksize;
	258	};
	259
	260	struct mmc {
	261	struct list_head link;
	262	char name[32];
	263	void *priv;
	264	uint voltages;
	265	uint version;
	266	uint f_min;
	267	uint f_max;
	268	int high_capacity;
	269	uint bus_width;
	270	uint clock;
	271	uint card_caps;
	272	uint host_caps;
	273	uint ocr;
	274	uint scr[2];
	275	uint csd[4];
0b453ffe	276	uint cid[4];
272cc70b AF	277	ushort rca;
	278	uint tran_speed;
	279	uint read_bl_len;
	280	uint write_bl_len;
	281	u64 capacity;
	282	block_dev_desc_t block_dev;
	283	int (send_cmd)(struct mmc mmc,
	284	struct mmc_cmd cmd, struct mmc_data data);
	285	void (set_ios)(struct mmc mmc);
	286	int (init)(struct mmc mmc);
57418d21	287	uint b_max;
272cc70b AF	288	};
	289
	290	int mmc_register(struct mmc *mmc);
	291	int mmc_initialize(bd_t *bis);
	292	int mmc_init(struct mmc *mmc);
	293	int mmc_read(struct mmc mmc, u64 src, uchar dst, int size);
4a6ee172	294	void mmc_set_clock(struct mmc *mmc, uint clock);
272cc70b	295	struct mmc *find_mmc_device(int dev_num);
89716964	296	int mmc_set_dev(int dev_num);
272cc70b	297	void print_mmc_devices(char separator);
ea6ebe21	298	int get_mmc_num(void);
11fdade2	299	int board_mmc_getcd(u8 cd, struct mmc mmc);
272cc70b	300
1592ef85 RM	301	#ifdef CONFIG_GENERIC_MMC
1592ef85 RM	302	int atmel_mci_init(void *regs);
d52ebf10 TC	303	#define mmc_host_is_spi(mmc) ((mmc)->host_caps & MMC_MODE_SPI)
d52ebf10 TC	304	struct mmc *mmc_spi_init(uint bus, uint cs, uint speed, uint mode);
1592ef85	305	#else
272cc70b AF	306	int mmc_legacy_init(int verbose);
272cc70b AF	307	#endif
1592ef85	308
71f95118	309	#endif /* _MMC_H_ */