projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 1df49e27 WD |
1 | /* |
| 2 | * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com> | |
| 3 | * Andreas Heppel <aheppel@sysgo.de> | |
| 4 | * | |
| 1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
| 1df49e27 WD |
6 | */ |
| 7 | ||
| 8 | #ifndef _MPC106_PCI_H | |
| 9 | #define _MPC106_PCI_H | |
| 10 | ||
| 11 | /* | |
| 12 | * Defines for the MPC106 PCI Config address and data registers followed by | |
| 13 | * defines for the standard PCI device configuration header. | |
| 14 | */ | |
| 53677ef1 | 15 | #define PCIDEVID_MPC106 0x0 |
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16 | |
| 17 | /* | |
| 18 | * MPC106 Registers | |
| 19 | */ | |
| 20 | #define MPC106_REG 0x80000000 | |
| 21 | ||
| 6d0f6bcf | 22 | #ifdef CONFIG_SYS_ADDRESS_MAP_A |
| 53677ef1 | 23 | #define MPC106_REG_ADDR 0x80000cf8 |
| 1df49e27 WD |
24 | #define MPC106_REG_DATA 0x80000cfc |
| 25 | #define MPC106_ISA_IO_PHYS 0x80000000 | |
| 26 | #define MPC106_ISA_IO_BUS 0x00000000 | |
| 27 | #define MPC106_ISA_IO_SIZE 0x00800000 | |
| 28 | #define MPC106_PCI_IO_PHYS 0x81000000 | |
| 29 | #define MPC106_PCI_IO_BUS 0x01000000 | |
| 30 | #define MPC106_PCI_IO_SIZE 0x3e800000 | |
| 31 | #define MPC106_PCI_MEM_PHYS 0xc0000000 | |
| 32 | #define MPC106_PCI_MEM_BUS 0x00000000 | |
| 33 | #define MPC106_PCI_MEM_SIZE 0x3f000000 | |
| 34 | #define MPC106_PCI_MEMORY_PHYS 0x00000000 | |
| 35 | #define MPC106_PCI_MEMORY_BUS 0x80000000 | |
| 36 | #define MPC106_PCI_MEMORY_SIZE 0x80000000 | |
| 37 | #else | |
| 53677ef1 | 38 | #define MPC106_REG_ADDR 0xfec00cf8 |
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39 | #define MPC106_REG_DATA 0xfee00cfc |
| 40 | #define MPC106_ISA_MEM_PHYS 0xfd000000 | |
| 41 | #define MPC106_ISA_MEM_BUS 0x00000000 | |
| 42 | #define MPC106_ISA_MEM_SIZE 0x01000000 | |
| 43 | #define MPC106_ISA_IO_PHYS 0xfe000000 | |
| 44 | #define MPC106_ISA_IO_BUS 0x00000000 | |
| 45 | #define MPC106_ISA_IO_SIZE 0x00800000 | |
| 46 | #define MPC106_PCI_IO_PHYS 0xfe800000 | |
| 47 | #define MPC106_PCI_IO_BUS 0x00800000 | |
| 48 | #define MPC106_PCI_IO_SIZE 0x00400000 | |
| 49 | #define MPC106_PCI_MEM_PHYS 0x80000000 | |
| 50 | #define MPC106_PCI_MEM_BUS 0x80000000 | |
| 51 | #define MPC106_PCI_MEM_SIZE 0x7d000000 | |
| 52 | #define MPC106_PCI_MEMORY_PHYS 0x00000000 | |
| 53 | #define MPC106_PCI_MEMORY_BUS 0x00000000 | |
| 54 | #define MPC106_PCI_MEMORY_SIZE 0x40000000 | |
| 55 | #endif | |
| 56 | ||
| 57 | #define CMD_SERR 0x0100 | |
| 58 | #define PCI_CMD_MASTER 0x0004 | |
| 59 | #define PCI_CMD_MEMEN 0x0002 | |
| 60 | #define PCI_CMD_IOEN 0x0001 | |
| 61 | ||
| 62 | #define PCI_STAT_NO_RSV_BITS 0xffff | |
| 63 | ||
| 53677ef1 WD |
64 | #define PCI_BUSNUM 0x40 |
| 65 | #define PCI_SUBBUSNUM 0x41 | |
| 66 | #define PCI_DISCOUNT 0x42 | |
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67 | |
| 68 | #define PCI_PICR1 0xA8 | |
| 69 | #define PICR1_CF_CBA(value) ((value & 0xff) << 24) | |
| 70 | #define PICR1_CF_BREAD_WS(value) ((value & 0x3) << 22) | |
| 71 | #define PICR1_PROC_TYPE_603 0x40000 | |
| 72 | #define PICR1_PROC_TYPE_604 0x60000 | |
| 73 | #define PICR1_MCP_EN 0x800 | |
| 74 | #define PICR1_CF_DPARK 0x200 | |
| 75 | #define PICR1_CF_LOOP_SNOOP 0x10 | |
| 76 | #define PICR1_CF_L2_COPY_BACK 0x2 | |
| 77 | #define PICR1_CF_L2_CACHE_MASK 0x3 | |
| 78 | #define PICR1_CF_APARK 0x8 | |
| 79 | #define PICR1_ADDRESS_MAP 0x10000 | |
| 80 | #define PICR1_XIO_MODE 0x80000 | |
| 81 | #define PICR1_CF_CACHE_1G 0x200000 | |
| 82 | ||
| 83 | #define PCI_PICR2 0xAC | |
| 84 | #define PICR2_CF_SNOOP_WS(value) ((value & 0x3) << 18) | |
| 85 | #define PICR2_CF_FLUSH_L2 0x10000000 | |
| 86 | #define PICR2_CF_L2_HIT_DELAY(value) ((value & 0x3) << 9) | |
| 87 | #define PICR2_CF_APHASE_WS(value) ((value & 0x3) << 2) | |
| 88 | #define PICR2_CF_INV_MODE 0x00001000 | |
| 89 | #define PICR2_CF_MOD_HIGH 0x00020000 | |
| 90 | #define PICR2_CF_HIT_HIGH 0x00010000 | |
| 91 | #define PICR2_L2_SIZE_256K 0x00000000 | |
| 92 | #define PICR2_L2_SIZE_512K 0x00000010 | |
| 93 | #define PICR2_L2_SIZE_1MB 0x00000020 | |
| 94 | #define PICR2_L2_EN 0x40000000 | |
| 95 | #define PICR2_L2_UPDATE_EN 0x80000000 | |
| 96 | #define PICR2_CF_ADDR_ONLY_DISABLE 0x00004000 | |
| 97 | #define PICR2_CF_FAST_CASTOUT 0x00000080 | |
| 98 | #define PICR2_CF_WDATA 0x00000001 | |
| 99 | #define PICR2_CF_DATA_RAM_PBURST 0x00400000 | |
| 100 | ||
| 101 | /* | |
| 102 | * Memory controller | |
| 103 | */ | |
| 104 | #define MPC106_MCCR1 0xF0 | |
| 105 | #define MCCR1_TYPE_EDO 0x00020000 | |
| 106 | #define MCCR1_BK0_9BITS 0x0 | |
| 107 | #define MCCR1_BK0_10BITS 0x1 | |
| 108 | #define MCCR1_BK0_11BITS 0x2 | |
| 109 | #define MCCR1_BK0_12BITS 0x3 | |
| 110 | #define MCCR1_BK1_9BITS 0x0 | |
| 111 | #define MCCR1_BK1_10BITS 0x4 | |
| 112 | #define MCCR1_BK1_11BITS 0x8 | |
| 113 | #define MCCR1_BK1_12BITS 0xC | |
| 114 | #define MCCR1_BK2_9BITS 0x00 | |
| 115 | #define MCCR1_BK2_10BITS 0x10 | |
| 116 | #define MCCR1_BK2_11BITS 0x20 | |
| 117 | #define MCCR1_BK2_12BITS 0x30 | |
| 118 | #define MCCR1_BK3_9BITS 0x00 | |
| 119 | #define MCCR1_BK3_10BITS 0x40 | |
| 120 | #define MCCR1_BK3_11BITS 0x80 | |
| 121 | #define MCCR1_BK3_12BITS 0xC0 | |
| 122 | #define MCCR1_MEMGO 0x00080000 | |
| 123 | ||
| 124 | #define MPC106_MCCR2 0xF4 | |
| 125 | #define MPC106_MCCR3 0xF8 | |
| 126 | #define MPC106_MCCR4 0xFC | |
| 127 | ||
| 128 | #define MPC106_MSAR1 0x80 | |
| 129 | #define MPC106_EMSAR1 0x88 | |
| 130 | #define MPC106_EMSAR2 0x8C | |
| 131 | #define MPC106_MEAR1 0x90 | |
| 132 | #define MPC106_EMEAR1 0x98 | |
| 133 | #define MPC106_EMEAR2 0x9C | |
| 134 | ||
| 135 | #define MPC106_MBER 0xA0 | |
| 136 | #define MBER_BANK0 0x1 | |
| 137 | #define MBER_BANK1 0x2 | |
| 138 | #define MBER_BANK2 0x4 | |
| 139 | #define MBER_BANK3 0x8 | |
| 140 | ||
| 141 | #endif |