projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 945af8d7 WD |
1 | /* |
| 2 | * include/asm-ppc/mpc5xxx.h | |
| 3 | * | |
| fd428c05 | 4 | * Prototypes, etc. for the Motorola MPC5xxx |
| 945af8d7 WD |
5 | * embedded cpu chips |
| 6 | * | |
| 7 | * 2003 (c) MontaVista, Software, Inc. | |
| 8 | * Author: Dale Farnsworth <dfarnsworth@mvista.com> | |
| 9 | * | |
| 10 | * 2003 (C) Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
| 11 | * | |
| 1a459660 | 12 | * SPDX-License-Identifier: GPL-2.0+ |
| 945af8d7 WD |
13 | */ |
| 14 | #ifndef __ASMPPC_MPC5XXX_H | |
| 15 | #define __ASMPPC_MPC5XXX_H | |
| 16 | ||
| 4e325fbf DZ |
17 | #include <asm/types.h> |
| 18 | ||
| 945af8d7 | 19 | /* Processor name */ |
| 945af8d7 | 20 | #define CPU_ID_STR "MPC5200" |
| 945af8d7 WD |
21 | |
| 22 | /* Exception offsets (PowerPC standard) */ | |
| 23 | #define EXC_OFF_SYS_RESET 0x0100 | |
| 02032e8f | 24 | #define _START_OFFSET EXC_OFF_SYS_RESET |
| 945af8d7 | 25 | |
| 7152b1d0 | 26 | /* useful macros for manipulating CSx_START/STOP */ |
| 7152b1d0 WD |
27 | #define START_REG(start) ((start) >> 16) |
| 28 | #define STOP_REG(start, size) (((start) + (size) - 1) >> 16) | |
| 7152b1d0 | 29 | |
| 945af8d7 WD |
30 | /* Internal memory map */ |
| 31 | ||
| 6d0f6bcf JCPV |
32 | #define MPC5XXX_CS0_START (CONFIG_SYS_MBAR + 0x0004) |
| 33 | #define MPC5XXX_CS0_STOP (CONFIG_SYS_MBAR + 0x0008) | |
| 34 | #define MPC5XXX_CS1_START (CONFIG_SYS_MBAR + 0x000c) | |
| 35 | #define MPC5XXX_CS1_STOP (CONFIG_SYS_MBAR + 0x0010) | |
| 36 | #define MPC5XXX_CS2_START (CONFIG_SYS_MBAR + 0x0014) | |
| 37 | #define MPC5XXX_CS2_STOP (CONFIG_SYS_MBAR + 0x0018) | |
| 38 | #define MPC5XXX_CS3_START (CONFIG_SYS_MBAR + 0x001c) | |
| 39 | #define MPC5XXX_CS3_STOP (CONFIG_SYS_MBAR + 0x0020) | |
| 40 | #define MPC5XXX_CS4_START (CONFIG_SYS_MBAR + 0x0024) | |
| 41 | #define MPC5XXX_CS4_STOP (CONFIG_SYS_MBAR + 0x0028) | |
| 42 | #define MPC5XXX_CS5_START (CONFIG_SYS_MBAR + 0x002c) | |
| 43 | #define MPC5XXX_CS5_STOP (CONFIG_SYS_MBAR + 0x0030) | |
| 44 | #define MPC5XXX_BOOTCS_START (CONFIG_SYS_MBAR + 0x004c) | |
| 45 | #define MPC5XXX_BOOTCS_STOP (CONFIG_SYS_MBAR + 0x0050) | |
| 46 | #define MPC5XXX_ADDECR (CONFIG_SYS_MBAR + 0x0054) | |
| 945af8d7 | 47 | |
| 6d0f6bcf JCPV |
48 | #define MPC5XXX_CS6_START (CONFIG_SYS_MBAR + 0x0058) |
| 49 | #define MPC5XXX_CS6_STOP (CONFIG_SYS_MBAR + 0x005c) | |
| 50 | #define MPC5XXX_CS7_START (CONFIG_SYS_MBAR + 0x0060) | |
| 51 | #define MPC5XXX_CS7_STOP (CONFIG_SYS_MBAR + 0x0064) | |
| 52 | #define MPC5XXX_SDRAM_CS0CFG (CONFIG_SYS_MBAR + 0x0034) | |
| 53 | #define MPC5XXX_SDRAM_CS1CFG (CONFIG_SYS_MBAR + 0x0038) | |
| 945af8d7 | 54 | |
| 6d0f6bcf JCPV |
55 | #define MPC5XXX_SDRAM (CONFIG_SYS_MBAR + 0x0100) |
| 56 | #define MPC5XXX_CDM (CONFIG_SYS_MBAR + 0x0200) | |
| 57 | #define MPC5XXX_LPB (CONFIG_SYS_MBAR + 0x0300) | |
| 58 | #define MPC5XXX_ICTL (CONFIG_SYS_MBAR + 0x0500) | |
| 59 | #define MPC5XXX_GPT (CONFIG_SYS_MBAR + 0x0600) | |
| 60 | #define MPC5XXX_GPIO (CONFIG_SYS_MBAR + 0x0b00) | |
| 61 | #define MPC5XXX_WU_GPIO (CONFIG_SYS_MBAR + 0x0c00) | |
| 62 | #define MPC5XXX_PCI (CONFIG_SYS_MBAR + 0x0d00) | |
| 63 | #define MPC5XXX_SPI (CONFIG_SYS_MBAR + 0x0f00) | |
| 64 | #define MPC5XXX_USB (CONFIG_SYS_MBAR + 0x1000) | |
| 65 | #define MPC5XXX_SDMA (CONFIG_SYS_MBAR + 0x1200) | |
| 66 | #define MPC5XXX_XLBARB (CONFIG_SYS_MBAR + 0x1f00) | |
| 945af8d7 | 67 | |
| 6d0f6bcf JCPV |
68 | #define MPC5XXX_PSC1 (CONFIG_SYS_MBAR + 0x2000) |
| 69 | #define MPC5XXX_PSC2 (CONFIG_SYS_MBAR + 0x2200) | |
| 70 | #define MPC5XXX_PSC3 (CONFIG_SYS_MBAR + 0x2400) | |
| 71 | #define MPC5XXX_PSC4 (CONFIG_SYS_MBAR + 0x2600) | |
| 72 | #define MPC5XXX_PSC5 (CONFIG_SYS_MBAR + 0x2800) | |
| 73 | #define MPC5XXX_PSC6 (CONFIG_SYS_MBAR + 0x2c00) | |
| 945af8d7 | 74 | |
| 6d0f6bcf JCPV |
75 | #define MPC5XXX_FEC (CONFIG_SYS_MBAR + 0x3000) |
| 76 | #define MPC5XXX_ATA (CONFIG_SYS_MBAR + 0x3A00) | |
| 945af8d7 | 77 | |
| 6d0f6bcf JCPV |
78 | #define MPC5XXX_I2C1 (CONFIG_SYS_MBAR + 0x3D00) |
| 79 | #define MPC5XXX_I2C2 (CONFIG_SYS_MBAR + 0x3D40) | |
| 531716e1 | 80 | |
| 6d0f6bcf | 81 | #define MPC5XXX_SRAM (CONFIG_SYS_MBAR + 0x8000) |
| 945af8d7 | 82 | #define MPC5XXX_SRAM_SIZE (16*1024) |
| 945af8d7 WD |
83 | |
| 84 | /* SDRAM Controller */ | |
| 85 | #define MPC5XXX_SDRAM_MODE (MPC5XXX_SDRAM + 0x0000) | |
| 86 | #define MPC5XXX_SDRAM_CTRL (MPC5XXX_SDRAM + 0x0004) | |
| 87 | #define MPC5XXX_SDRAM_CONFIG1 (MPC5XXX_SDRAM + 0x0008) | |
| 88 | #define MPC5XXX_SDRAM_CONFIG2 (MPC5XXX_SDRAM + 0x000c) | |
| b66a9383 | 89 | #define MPC5XXX_SDRAM_SDELAY (MPC5XXX_SDRAM + 0x0090) |
| 945af8d7 WD |
90 | |
| 91 | /* Clock Distribution Module */ | |
| 92 | #define MPC5XXX_CDM_JTAGID (MPC5XXX_CDM + 0x0000) | |
| 93 | #define MPC5XXX_CDM_PORCFG (MPC5XXX_CDM + 0x0004) | |
| bef92e21 | 94 | #define MPC5XXX_CDM_BRDCRMB (MPC5XXX_CDM + 0x0008) |
| 945af8d7 | 95 | #define MPC5XXX_CDM_CFG (MPC5XXX_CDM + 0x000c) |
| 80885a9d | 96 | #define MPC5XXX_CDM_48_FDC (MPC5XXX_CDM + 0x0010) |
| de3ce8c5 | 97 | #define MPC5XXX_CDM_CLK_ENA (MPC5XXX_CDM + 0x0014) |
| 945af8d7 WD |
98 | #define MPC5XXX_CDM_SRESET (MPC5XXX_CDM + 0x0020) |
| 99 | ||
| 100 | /* Local Plus Bus interface */ | |
| 101 | #define MPC5XXX_CS0_CFG (MPC5XXX_LPB + 0x0000) | |
| 102 | #define MPC5XXX_CS1_CFG (MPC5XXX_LPB + 0x0004) | |
| 103 | #define MPC5XXX_CS2_CFG (MPC5XXX_LPB + 0x0008) | |
| 104 | #define MPC5XXX_CS3_CFG (MPC5XXX_LPB + 0x000c) | |
| 105 | #define MPC5XXX_CS4_CFG (MPC5XXX_LPB + 0x0010) | |
| 106 | #define MPC5XXX_CS5_CFG (MPC5XXX_LPB + 0x0014) | |
| 107 | #define MPC5XXX_BOOTCS_CFG MPC5XXX_CS0_CFG | |
| 108 | #define MPC5XXX_CS_CTRL (MPC5XXX_LPB + 0x0018) | |
| 109 | #define MPC5XXX_CS_STATUS (MPC5XXX_LPB + 0x001c) | |
| 945af8d7 WD |
110 | #define MPC5XXX_CS6_CFG (MPC5XXX_LPB + 0x0020) |
| 111 | #define MPC5XXX_CS7_CFG (MPC5XXX_LPB + 0x0024) | |
| 112 | #define MPC5XXX_CS_BURST (MPC5XXX_LPB + 0x0028) | |
| 113 | #define MPC5XXX_CS_DEADCYCLE (MPC5XXX_LPB + 0x002c) | |
| 945af8d7 | 114 | |
| 4aeb251f WD |
115 | /* XLB Arbiter registers */ |
| 116 | #define MPC5XXX_XLBARB_CFG (MPC5XXX_XLBARB + 0x40) | |
| 117 | #define MPC5XXX_XLBARB_MPRIEN (MPC5XXX_XLBARB + 0x64) | |
| 118 | #define MPC5XXX_XLBARB_MPRIVAL (MPC5XXX_XLBARB + 0x68) | |
| 4aeb251f | 119 | |
| 945af8d7 WD |
120 | /* GPIO registers */ |
| 121 | #define MPC5XXX_GPS_PORT_CONFIG (MPC5XXX_GPIO + 0x0000) | |
| 122 | ||
| 6c7a1408 WD |
123 | /* Standard GPIO registers (simple, output only and simple interrupt */ |
| 124 | #define MPC5XXX_GPIO_ENABLE (MPC5XXX_GPIO + 0x0004) | |
| 125 | #define MPC5XXX_GPIO_ODE (MPC5XXX_GPIO + 0x0008) | |
| 126 | #define MPC5XXX_GPIO_DIR (MPC5XXX_GPIO + 0x000c) | |
| 127 | #define MPC5XXX_GPIO_DATA_O (MPC5XXX_GPIO + 0x0010) | |
| 128 | #define MPC5XXX_GPIO_DATA_I (MPC5XXX_GPIO + 0x0014) | |
| 129 | #define MPC5XXX_GPIO_OO_ENABLE (MPC5XXX_GPIO + 0x0018) | |
| 130 | #define MPC5XXX_GPIO_OO_DATA (MPC5XXX_GPIO + 0x001C) | |
| 131 | #define MPC5XXX_GPIO_SI_ENABLE (MPC5XXX_GPIO + 0x0020) | |
| 132 | #define MPC5XXX_GPIO_SI_ODE (MPC5XXX_GPIO + 0x0024) | |
| 133 | #define MPC5XXX_GPIO_SI_DIR (MPC5XXX_GPIO + 0x0028) | |
| 134 | #define MPC5XXX_GPIO_SI_DATA (MPC5XXX_GPIO + 0x002C) | |
| 135 | #define MPC5XXX_GPIO_SI_IEN (MPC5XXX_GPIO + 0x0030) | |
| 136 | #define MPC5XXX_GPIO_SI_ITYPE (MPC5XXX_GPIO + 0x0034) | |
| 137 | #define MPC5XXX_GPIO_SI_MEN (MPC5XXX_GPIO + 0x0038) | |
| 138 | #define MPC5XXX_GPIO_SI_STATUS (MPC5XXX_GPIO + 0x003C) | |
| 139 | ||
| 132ba5fd WD |
140 | /* WakeUp GPIO registers */ |
| 141 | #define MPC5XXX_WU_GPIO_ENABLE (MPC5XXX_WU_GPIO + 0x0000) | |
| 142 | #define MPC5XXX_WU_GPIO_ODE (MPC5XXX_WU_GPIO + 0x0004) | |
| 143 | #define MPC5XXX_WU_GPIO_DIR (MPC5XXX_WU_GPIO + 0x0008) | |
| dae80f3c BS |
144 | #define MPC5XXX_WU_GPIO_DATA_O (MPC5XXX_WU_GPIO + 0x000c) |
| 145 | #define MPC5XXX_WU_GPIO_DATA_I (MPC5XXX_WU_GPIO + 0x0020) | |
| 146 | ||
| 9531a238 | 147 | /* GPIO pins, for Rev.B chip */ |
| dae80f3c BS |
148 | #define GPIO_WKUP_7 0x80000000UL |
| 149 | #define GPIO_PSC6_0 0x10000000UL | |
| 150 | #define GPIO_PSC3_9 0x04000000UL | |
| 151 | #define GPIO_PSC1_4 0x01000000UL | |
| 9531a238 | 152 | #define GPIO_PSC2_4 0x02000000UL |
| 132ba5fd | 153 | |
| 5e0de0e2 AS |
154 | #define MPC5XXX_GPIO_SIMPLE_PSC6_3 0x20000000UL |
| 155 | #define MPC5XXX_GPIO_SIMPLE_PSC6_2 0x10000000UL | |
| 156 | #define MPC5XXX_GPIO_SIMPLE_PSC3_7 0x00002000UL | |
| 157 | #define MPC5XXX_GPIO_SIMPLE_PSC3_6 0x00001000UL | |
| 158 | #define MPC5XXX_GPIO_SIMPLE_PSC3_3 0x00000800UL | |
| 159 | #define MPC5XXX_GPIO_SIMPLE_PSC3_2 0x00000400UL | |
| 160 | #define MPC5XXX_GPIO_SIMPLE_PSC3_1 0x00000200UL | |
| 161 | #define MPC5XXX_GPIO_SIMPLE_PSC3_0 0x00000100UL | |
| 162 | #define MPC5XXX_GPIO_SIMPLE_PSC2_3 0x00000080UL | |
| 163 | #define MPC5XXX_GPIO_SIMPLE_PSC2_2 0x00000040UL | |
| 164 | #define MPC5XXX_GPIO_SIMPLE_PSC2_1 0x00000020UL | |
| 165 | #define MPC5XXX_GPIO_SIMPLE_PSC2_0 0x00000010UL | |
| 166 | #define MPC5XXX_GPIO_SIMPLE_PSC1_3 0x00000008UL | |
| 167 | #define MPC5XXX_GPIO_SIMPLE_PSC1_2 0x00000004UL | |
| 168 | #define MPC5XXX_GPIO_SIMPLE_PSC1_1 0x00000002UL | |
| 169 | #define MPC5XXX_GPIO_SIMPLE_PSC1_0 0x00000001UL | |
| 170 | ||
| 4e325fbf DZ |
171 | #define MPC5XXX_GPIO_SINT_ETH_16 0x80 |
| 172 | #define MPC5XXX_GPIO_SINT_ETH_15 0x40 | |
| 173 | #define MPC5XXX_GPIO_SINT_ETH_14 0x20 | |
| 174 | #define MPC5XXX_GPIO_SINT_ETH_13 0x10 | |
| 175 | #define MPC5XXX_GPIO_SINT_USB1_9 0x08 | |
| 176 | #define MPC5XXX_GPIO_SINT_PSC3_8 0x04 | |
| 5e0de0e2 AS |
177 | #define MPC5XXX_GPIO_SINT_PSC3_5 0x02 |
| 178 | #define MPC5XXX_GPIO_SINT_PSC3_4 0x01 | |
| 179 | ||
| 180 | #define MPC5XXX_GPIO_WKUP_7 0x80 | |
| 181 | #define MPC5XXX_GPIO_WKUP_6 0x40 | |
| 182 | #define MPC5XXX_GPIO_WKUP_PSC6_1 0x20 | |
| 183 | #define MPC5XXX_GPIO_WKUP_PSC6_0 0x10 | |
| 184 | #define MPC5XXX_GPIO_WKUP_ETH17 0x08 | |
| 185 | #define MPC5XXX_GPIO_WKUP_PSC3_9 0x04 | |
| 186 | #define MPC5XXX_GPIO_WKUP_PSC2_4 0x02 | |
| 187 | #define MPC5XXX_GPIO_WKUP_PSC1_4 0x01 | |
| 188 | ||
| 96e48cf6 WD |
189 | /* PCI registers */ |
| 190 | #define MPC5XXX_PCI_CMD (MPC5XXX_PCI + 0x04) | |
| 191 | #define MPC5XXX_PCI_CFG (MPC5XXX_PCI + 0x0c) | |
| 192 | #define MPC5XXX_PCI_BAR0 (MPC5XXX_PCI + 0x10) | |
| 193 | #define MPC5XXX_PCI_BAR1 (MPC5XXX_PCI + 0x14) | |
| 96e48cf6 WD |
194 | #define MPC5XXX_PCI_GSCR (MPC5XXX_PCI + 0x60) |
| 195 | #define MPC5XXX_PCI_TBATR0 (MPC5XXX_PCI + 0x64) | |
| 196 | #define MPC5XXX_PCI_TBATR1 (MPC5XXX_PCI + 0x68) | |
| 197 | #define MPC5XXX_PCI_TCR (MPC5XXX_PCI + 0x6c) | |
| 198 | #define MPC5XXX_PCI_IW0BTAR (MPC5XXX_PCI + 0x70) | |
| 199 | #define MPC5XXX_PCI_IW1BTAR (MPC5XXX_PCI + 0x74) | |
| 200 | #define MPC5XXX_PCI_IW2BTAR (MPC5XXX_PCI + 0x78) | |
| 201 | #define MPC5XXX_PCI_IWCR (MPC5XXX_PCI + 0x80) | |
| 202 | #define MPC5XXX_PCI_ICR (MPC5XXX_PCI + 0x84) | |
| 203 | #define MPC5XXX_PCI_ISR (MPC5XXX_PCI + 0x88) | |
| 204 | #define MPC5XXX_PCI_ARB (MPC5XXX_PCI + 0x8c) | |
| 205 | #define MPC5XXX_PCI_CAR (MPC5XXX_PCI + 0xf8) | |
| 96e48cf6 | 206 | |
| 945af8d7 WD |
207 | /* Interrupt Controller registers */ |
| 208 | #define MPC5XXX_ICTL_PER_MASK (MPC5XXX_ICTL + 0x0000) | |
| 209 | #define MPC5XXX_ICTL_PER_PRIO1 (MPC5XXX_ICTL + 0x0004) | |
| 210 | #define MPC5XXX_ICTL_PER_PRIO2 (MPC5XXX_ICTL + 0x0008) | |
| 211 | #define MPC5XXX_ICTL_PER_PRIO3 (MPC5XXX_ICTL + 0x000c) | |
| 212 | #define MPC5XXX_ICTL_EXT (MPC5XXX_ICTL + 0x0010) | |
| 213 | #define MPC5XXX_ICTL_CRIT (MPC5XXX_ICTL + 0x0014) | |
| 214 | #define MPC5XXX_ICTL_MAIN_PRIO1 (MPC5XXX_ICTL + 0x0018) | |
| 215 | #define MPC5XXX_ICTL_MAIN_PRIO2 (MPC5XXX_ICTL + 0x001c) | |
| 216 | #define MPC5XXX_ICTL_STS (MPC5XXX_ICTL + 0x0024) | |
| 217 | #define MPC5XXX_ICTL_CRIT_STS (MPC5XXX_ICTL + 0x0028) | |
| 218 | #define MPC5XXX_ICTL_MAIN_STS (MPC5XXX_ICTL + 0x002c) | |
| 219 | #define MPC5XXX_ICTL_PER_STS (MPC5XXX_ICTL + 0x0030) | |
| 220 | #define MPC5XXX_ICTL_BUS_STS (MPC5XXX_ICTL + 0x0038) | |
| 221 | ||
| 43835aac DZ |
222 | #define NR_IRQS 64 |
| 223 | ||
| 224 | /* IRQ mapping - these are our logical IRQ numbers */ | |
| 225 | #define MPC5XXX_CRIT_IRQ_NUM 4 | |
| 226 | #define MPC5XXX_MAIN_IRQ_NUM 17 | |
| 227 | #define MPC5XXX_SDMA_IRQ_NUM 17 | |
| 228 | #define MPC5XXX_PERP_IRQ_NUM 23 | |
| 229 | ||
| 230 | #define MPC5XXX_CRIT_IRQ_BASE 1 | |
| 231 | #define MPC5XXX_MAIN_IRQ_BASE (MPC5XXX_CRIT_IRQ_BASE + MPC5XXX_CRIT_IRQ_NUM) | |
| 232 | #define MPC5XXX_SDMA_IRQ_BASE (MPC5XXX_MAIN_IRQ_BASE + MPC5XXX_MAIN_IRQ_NUM) | |
| 233 | #define MPC5XXX_PERP_IRQ_BASE (MPC5XXX_SDMA_IRQ_BASE + MPC5XXX_SDMA_IRQ_NUM) | |
| 234 | ||
| 235 | #define MPC5XXX_IRQ0 (MPC5XXX_CRIT_IRQ_BASE + 0) | |
| 236 | #define MPC5XXX_SLICE_TIMER_0_IRQ (MPC5XXX_CRIT_IRQ_BASE + 1) | |
| 237 | #define MPC5XXX_HI_INT_IRQ (MPC5XXX_CRIT_IRQ_BASE + 2) | |
| 238 | #define MPC5XXX_CCS_IRQ (MPC5XXX_CRIT_IRQ_BASE + 3) | |
| 239 | ||
| 240 | #define MPC5XXX_IRQ1 (MPC5XXX_MAIN_IRQ_BASE + 1) | |
| 241 | #define MPC5XXX_IRQ2 (MPC5XXX_MAIN_IRQ_BASE + 2) | |
| 242 | #define MPC5XXX_IRQ3 (MPC5XXX_MAIN_IRQ_BASE + 3) | |
| 243 | #define MPC5XXX_RTC_PINT_IRQ (MPC5XXX_MAIN_IRQ_BASE + 5) | |
| 244 | #define MPC5XXX_RTC_SINT_IRQ (MPC5XXX_MAIN_IRQ_BASE + 6) | |
| 245 | #define MPC5XXX_RTC_GPIO_STD_IRQ (MPC5XXX_MAIN_IRQ_BASE + 7) | |
| 246 | #define MPC5XXX_RTC_GPIO_WKUP_IRQ (MPC5XXX_MAIN_IRQ_BASE + 8) | |
| 247 | #define MPC5XXX_TMR0_IRQ (MPC5XXX_MAIN_IRQ_BASE + 9) | |
| 248 | #define MPC5XXX_TMR1_IRQ (MPC5XXX_MAIN_IRQ_BASE + 10) | |
| 249 | #define MPC5XXX_TMR2_IRQ (MPC5XXX_MAIN_IRQ_BASE + 11) | |
| 250 | #define MPC5XXX_TMR3_IRQ (MPC5XXX_MAIN_IRQ_BASE + 12) | |
| 251 | #define MPC5XXX_TMR4_IRQ (MPC5XXX_MAIN_IRQ_BASE + 13) | |
| 252 | #define MPC5XXX_TMR5_IRQ (MPC5XXX_MAIN_IRQ_BASE + 14) | |
| 253 | #define MPC5XXX_TMR6_IRQ (MPC5XXX_MAIN_IRQ_BASE + 15) | |
| 254 | #define MPC5XXX_TMR7_IRQ (MPC5XXX_MAIN_IRQ_BASE + 16) | |
| 255 | ||
| 256 | #define MPC5XXX_SDMA_IRQ (MPC5XXX_PERP_IRQ_BASE + 0) | |
| 257 | #define MPC5XXX_PSC1_IRQ (MPC5XXX_PERP_IRQ_BASE + 1) | |
| 258 | #define MPC5XXX_PSC2_IRQ (MPC5XXX_PERP_IRQ_BASE + 2) | |
| 259 | #define MPC5XXX_PSC3_IRQ (MPC5XXX_PERP_IRQ_BASE + 3) | |
| 260 | #define MPC5XXX_PSC6_IRQ (MPC5XXX_PERP_IRQ_BASE + 4) | |
| 261 | #define MPC5XXX_IRDA_IRQ (MPC5XXX_PERP_IRQ_BASE + 4) | |
| 262 | #define MPC5XXX_FEC_IRQ (MPC5XXX_PERP_IRQ_BASE + 5) | |
| 263 | #define MPC5XXX_USB_IRQ (MPC5XXX_PERP_IRQ_BASE + 6) | |
| 264 | #define MPC5XXX_ATA_IRQ (MPC5XXX_PERP_IRQ_BASE + 7) | |
| 265 | #define MPC5XXX_PCI_CNTRL_IRQ (MPC5XXX_PERP_IRQ_BASE + 8) | |
| 266 | #define MPC5XXX_PCI_SCIRX_IRQ (MPC5XXX_PERP_IRQ_BASE + 9) | |
| 267 | #define MPC5XXX_PCI_SCITX_IRQ (MPC5XXX_PERP_IRQ_BASE + 10) | |
| 268 | #define MPC5XXX_PSC4_IRQ (MPC5XXX_PERP_IRQ_BASE + 11) | |
| 269 | #define MPC5XXX_PSC5_IRQ (MPC5XXX_PERP_IRQ_BASE + 12) | |
| 270 | #define MPC5XXX_SPI_MODF_IRQ (MPC5XXX_PERP_IRQ_BASE + 13) | |
| 271 | #define MPC5XXX_SPI_SPIF_IRQ (MPC5XXX_PERP_IRQ_BASE + 14) | |
| 272 | #define MPC5XXX_I2C1_IRQ (MPC5XXX_PERP_IRQ_BASE + 15) | |
| 273 | #define MPC5XXX_I2C2_IRQ (MPC5XXX_PERP_IRQ_BASE + 16) | |
| 274 | #define MPC5XXX_MSCAN1_IRQ (MPC5XXX_PERP_IRQ_BASE + 17) | |
| 275 | #define MPC5XXX_MSCAN2_IRQ (MPC5XXX_PERP_IRQ_BASE + 18) | |
| 276 | #define MPC5XXX_IR_RX_IRQ (MPC5XXX_PERP_IRQ_BASE + 19) | |
| 277 | #define MPC5XXX_IR_TX_IRQ (MPC5XXX_PERP_IRQ_BASE + 20) | |
| 278 | #define MPC5XXX_XLB_ARB_IRQ (MPC5XXX_PERP_IRQ_BASE + 21) | |
| 279 | #define MPC5XXX_BDLC_IRQ (MPC5XXX_PERP_IRQ_BASE + 22) | |
| 280 | ||
| d94f92cb WD |
281 | /* General Purpose Timers registers */ |
| 282 | #define MPC5XXX_GPT0_ENABLE (MPC5XXX_GPT + 0x0) | |
| 283 | #define MPC5XXX_GPT0_COUNTER (MPC5XXX_GPT + 0x4) | |
| 6d3bc9b8 | 284 | #define MPC5XXX_GPT0_STATUS (MPC5XXX_GPT + 0x0C) |
| f4733a07 WD |
285 | #define MPC5XXX_GPT1_ENABLE (MPC5XXX_GPT + 0x10) |
| 286 | #define MPC5XXX_GPT1_COUNTER (MPC5XXX_GPT + 0x14) | |
| 6d3bc9b8 | 287 | #define MPC5XXX_GPT1_STATUS (MPC5XXX_GPT + 0x1C) |
| f4733a07 WD |
288 | #define MPC5XXX_GPT2_ENABLE (MPC5XXX_GPT + 0x20) |
| 289 | #define MPC5XXX_GPT2_COUNTER (MPC5XXX_GPT + 0x24) | |
| 6d3bc9b8 | 290 | #define MPC5XXX_GPT2_STATUS (MPC5XXX_GPT + 0x2C) |
| f4733a07 WD |
291 | #define MPC5XXX_GPT3_ENABLE (MPC5XXX_GPT + 0x30) |
| 292 | #define MPC5XXX_GPT3_COUNTER (MPC5XXX_GPT + 0x34) | |
| 6d3bc9b8 | 293 | #define MPC5XXX_GPT3_STATUS (MPC5XXX_GPT + 0x3C) |
| f4733a07 WD |
294 | #define MPC5XXX_GPT4_ENABLE (MPC5XXX_GPT + 0x40) |
| 295 | #define MPC5XXX_GPT4_COUNTER (MPC5XXX_GPT + 0x44) | |
| 6d3bc9b8 | 296 | #define MPC5XXX_GPT4_STATUS (MPC5XXX_GPT + 0x4C) |
| f4733a07 | 297 | #define MPC5XXX_GPT5_ENABLE (MPC5XXX_GPT + 0x50) |
| 6d3bc9b8 | 298 | #define MPC5XXX_GPT5_STATUS (MPC5XXX_GPT + 0x5C) |
| f4733a07 WD |
299 | #define MPC5XXX_GPT5_COUNTER (MPC5XXX_GPT + 0x54) |
| 300 | #define MPC5XXX_GPT6_ENABLE (MPC5XXX_GPT + 0x60) | |
| 301 | #define MPC5XXX_GPT6_COUNTER (MPC5XXX_GPT + 0x64) | |
| 6d3bc9b8 | 302 | #define MPC5XXX_GPT6_STATUS (MPC5XXX_GPT + 0x6C) |
| f4733a07 WD |
303 | #define MPC5XXX_GPT7_ENABLE (MPC5XXX_GPT + 0x70) |
| 304 | #define MPC5XXX_GPT7_COUNTER (MPC5XXX_GPT + 0x74) | |
| 6d3bc9b8 MB |
305 | #define MPC5XXX_GPT7_STATUS (MPC5XXX_GPT + 0x7C) |
| 306 | ||
| 307 | #define MPC5XXX_GPT_GPIO_PIN(status) ((0x00000100 & (status)) >> 8) | |
| f4733a07 | 308 | |
| a0bdf49e | 309 | #define MPC5XXX_GPT7_PWMCFG (MPC5XXX_GPT + 0x78) |
| d94f92cb | 310 | |
| 132ba5fd WD |
311 | /* ATA registers */ |
| 312 | #define MPC5XXX_ATA_HOST_CONFIG (MPC5XXX_ATA + 0x0000) | |
| 313 | #define MPC5XXX_ATA_PIO1 (MPC5XXX_ATA + 0x0008) | |
| 314 | #define MPC5XXX_ATA_PIO2 (MPC5XXX_ATA + 0x000C) | |
| 315 | #define MPC5XXX_ATA_SHARE_COUNT (MPC5XXX_ATA + 0x002C) | |
| 316 | ||
| 531716e1 WD |
317 | /* I2Cn control register bits */ |
| 318 | #define I2C_EN 0x80 | |
| 319 | #define I2C_IEN 0x40 | |
| 320 | #define I2C_STA 0x20 | |
| 321 | #define I2C_TX 0x10 | |
| 322 | #define I2C_TXAK 0x08 | |
| 323 | #define I2C_RSTA 0x04 | |
| 324 | #define I2C_INIT_MASK (I2C_EN | I2C_STA | I2C_TX | I2C_RSTA) | |
| 325 | ||
| 326 | /* I2Cn status register bits */ | |
| 327 | #define I2C_CF 0x80 | |
| 328 | #define I2C_AAS 0x40 | |
| 329 | #define I2C_BB 0x20 | |
| 330 | #define I2C_AL 0x10 | |
| 331 | #define I2C_SRW 0x04 | |
| 332 | #define I2C_IF 0x02 | |
| 333 | #define I2C_RXAK 0x01 | |
| 334 | ||
| 6325b778 GB |
335 | /* SPI control register 1 bits */ |
| 336 | #define SPI_CR_LSBFE 0x01 | |
| 337 | #define SPI_CR_SSOE 0x02 | |
| 338 | #define SPI_CR_CPHA 0x04 | |
| 339 | #define SPI_CR_CPOL 0x08 | |
| 340 | #define SPI_CR_MSTR 0x10 | |
| 341 | #define SPI_CR_SWOM 0x20 | |
| 342 | #define SPI_CR_SPE 0x40 | |
| 343 | #define SPI_CR_SPIE 0x80 | |
| 344 | ||
| 345 | /* SPI status register bits */ | |
| 346 | #define SPI_SR_MODF 0x10 | |
| 347 | #define SPI_SR_WCOL 0x40 | |
| 348 | #define SPI_SR_SPIF 0x80 | |
| 349 | ||
| 350 | /* SPI port data register bits */ | |
| 351 | #define SPI_PDR_SS 0x08 | |
| 352 | ||
| 945af8d7 WD |
353 | /* Programmable Serial Controller (PSC) status register bits */ |
| 354 | #define PSC_SR_CDE 0x0080 | |
| 355 | #define PSC_SR_RXRDY 0x0100 | |
| 356 | #define PSC_SR_RXFULL 0x0200 | |
| 357 | #define PSC_SR_TXRDY 0x0400 | |
| 358 | #define PSC_SR_TXEMP 0x0800 | |
| 359 | #define PSC_SR_OE 0x1000 | |
| 360 | #define PSC_SR_PE 0x2000 | |
| 361 | #define PSC_SR_FE 0x4000 | |
| 362 | #define PSC_SR_RB 0x8000 | |
| 363 | ||
| 364 | /* PSC Command values */ | |
| 365 | #define PSC_RX_ENABLE 0x0001 | |
| 366 | #define PSC_RX_DISABLE 0x0002 | |
| 367 | #define PSC_TX_ENABLE 0x0004 | |
| 368 | #define PSC_TX_DISABLE 0x0008 | |
| 369 | #define PSC_SEL_MODE_REG_1 0x0010 | |
| 370 | #define PSC_RST_RX 0x0020 | |
| 371 | #define PSC_RST_TX 0x0030 | |
| 372 | #define PSC_RST_ERR_STAT 0x0040 | |
| 373 | #define PSC_RST_BRK_CHG_INT 0x0050 | |
| 374 | #define PSC_START_BRK 0x0060 | |
| 375 | #define PSC_STOP_BRK 0x0070 | |
| 376 | ||
| 377 | /* PSC Rx FIFO status bits */ | |
| 378 | #define PSC_RX_FIFO_ERR 0x0040 | |
| 379 | #define PSC_RX_FIFO_UF 0x0020 | |
| 380 | #define PSC_RX_FIFO_OF 0x0010 | |
| 381 | #define PSC_RX_FIFO_FR 0x0008 | |
| 382 | #define PSC_RX_FIFO_FULL 0x0004 | |
| 383 | #define PSC_RX_FIFO_ALARM 0x0002 | |
| 384 | #define PSC_RX_FIFO_EMPTY 0x0001 | |
| 385 | ||
| 386 | /* PSC interrupt mask bits */ | |
| 387 | #define PSC_IMR_TXRDY 0x0100 | |
| 388 | #define PSC_IMR_RXRDY 0x0200 | |
| 389 | #define PSC_IMR_DB 0x0400 | |
| 390 | #define PSC_IMR_IPC 0x8000 | |
| 391 | ||
| 392 | /* PSC input port change bits */ | |
| 393 | #define PSC_IPCR_CTS 0x01 | |
| 394 | #define PSC_IPCR_DCD 0x02 | |
| 395 | ||
| 396 | /* PSC mode fields */ | |
| 397 | #define PSC_MODE_5_BITS 0x00 | |
| 398 | #define PSC_MODE_6_BITS 0x01 | |
| 399 | #define PSC_MODE_7_BITS 0x02 | |
| 400 | #define PSC_MODE_8_BITS 0x03 | |
| 401 | #define PSC_MODE_PAREVEN 0x00 | |
| 402 | #define PSC_MODE_PARODD 0x04 | |
| 403 | #define PSC_MODE_PARFORCE 0x08 | |
| 404 | #define PSC_MODE_PARNONE 0x10 | |
| 405 | #define PSC_MODE_ERR 0x20 | |
| 406 | #define PSC_MODE_FFULL 0x40 | |
| 407 | #define PSC_MODE_RXRTS 0x80 | |
| 408 | ||
| 409 | #define PSC_MODE_ONE_STOP_5_BITS 0x00 | |
| 410 | #define PSC_MODE_ONE_STOP 0x07 | |
| 411 | #define PSC_MODE_TWO_STOP 0x0f | |
| 412 | ||
| 132ba5fd WD |
413 | /* ATA config fields */ |
| 414 | #define MPC5xxx_ATA_HOSTCONF_SMR 0x80000000UL /* State machine | |
| 415 | reset */ | |
| 416 | #define MPC5xxx_ATA_HOSTCONF_FR 0x40000000UL /* FIFO Reset */ | |
| 417 | #define MPC5xxx_ATA_HOSTCONF_IE 0x02000000UL /* Enable interrupt | |
| 418 | in PIO */ | |
| 419 | #define MPC5xxx_ATA_HOSTCONF_IORDY 0x01000000UL /* Drive supports | |
| 420 | IORDY protocol */ | |
| 421 | ||
| 945af8d7 | 422 | #ifndef __ASSEMBLY__ |
| 4e325fbf DZ |
423 | /* Memory map registers */ |
| 424 | struct mpc5xxx_mmap_ctl { | |
| 425 | volatile u32 mbar; | |
| 426 | volatile u32 cs0_start; /* 0x0004 */ | |
| 427 | volatile u32 cs0_stop; | |
| 428 | volatile u32 cs1_start; /* 0x000c */ | |
| 429 | volatile u32 cs1_stop; | |
| 430 | volatile u32 cs2_start; /* 0x0014 */ | |
| 431 | volatile u32 cs2_stop; | |
| 432 | volatile u32 cs3_start; /* 0x001c */ | |
| 433 | volatile u32 cs3_stop; | |
| 434 | volatile u32 cs4_start; /* 0x0024 */ | |
| 435 | volatile u32 cs4_stop; | |
| 436 | volatile u32 cs5_start; /* 0x002c */ | |
| 437 | volatile u32 cs5_stop; | |
| 4e325fbf DZ |
438 | volatile u32 sdram0; /* 0x0034 */ |
| 439 | volatile u32 sdram1; /* 0x0038 */ | |
| 440 | volatile u32 dummy1[4]; /* 0x003c */ | |
| 4e325fbf DZ |
441 | volatile u32 boot_start; /* 0x004c */ |
| 442 | volatile u32 boot_stop; | |
| 4e325fbf | 443 | volatile u32 ipbi_ws_ctrl; /* 0x0054 */ |
| 4e325fbf DZ |
444 | volatile u32 cs6_start; /* 0x0058 */ |
| 445 | volatile u32 cs6_stop; | |
| 446 | volatile u32 cs7_start; /* 0x0060 */ | |
| 447 | volatile u32 cs7_stop; | |
| 4e325fbf DZ |
448 | }; |
| 449 | ||
| 450 | /* Clock distribution module */ | |
| 451 | struct mpc5xxx_cdm { | |
| 452 | volatile u32 jtagid; /* 0x0000 */ | |
| 453 | volatile u32 porcfg; | |
| 454 | volatile u32 brdcrmb; /* 0x0008 */ | |
| 455 | volatile u32 cfg; | |
| 456 | volatile u32 fourtyeight_fdc;/* 0x0010 */ | |
| 457 | volatile u32 clock_enable; | |
| 458 | volatile u32 system_osc; /* 0x0018 */ | |
| 459 | volatile u32 ccscr; | |
| 460 | volatile u32 sreset; /* 0x0020 */ | |
| 461 | volatile u32 pll_status; | |
| 462 | volatile u32 psc1_mccr; /* 0x0028 */ | |
| 463 | volatile u32 psc2_mccr; | |
| 464 | volatile u32 psc3_mccr; /* 0x0030 */ | |
| 465 | volatile u32 psc6_mccr; | |
| 466 | }; | |
| 467 | ||
| 468 | /* SDRAM controller */ | |
| 469 | struct mpc5xxx_sdram { | |
| 470 | volatile u32 mode; | |
| 471 | volatile u32 ctrl; | |
| 472 | volatile u32 config1; | |
| 473 | volatile u32 config2; | |
| 4e325fbf | 474 | volatile u32 dummy[32]; |
| 4e325fbf DZ |
475 | volatile u32 sdelay; |
| 476 | }; | |
| 477 | ||
| 478 | struct mpc5xxx_lpb { | |
| 479 | volatile u32 cs0_cfg; | |
| 480 | volatile u32 cs1_cfg; | |
| 481 | volatile u32 cs2_cfg; | |
| 482 | volatile u32 cs3_cfg; | |
| 483 | volatile u32 cs4_cfg; | |
| 484 | volatile u32 cs5_cfg; | |
| 485 | volatile u32 cs_ctrl; | |
| 486 | volatile u32 cs_status; | |
| 4e325fbf DZ |
487 | volatile u32 cs6_cfg; |
| 488 | volatile u32 cs7_cfg; | |
| 489 | volatile u32 cs_burst; | |
| 490 | volatile u32 cs_deadcycle; | |
| 4e325fbf DZ |
491 | }; |
| 492 | ||
| 493 | ||
| 945af8d7 WD |
494 | struct mpc5xxx_psc { |
| 495 | volatile u8 mode; /* PSC + 0x00 */ | |
| 496 | volatile u8 reserved0[3]; | |
| 497 | union { /* PSC + 0x04 */ | |
| 498 | volatile u16 status; | |
| 499 | volatile u16 clock_select; | |
| 500 | } sr_csr; | |
| 501 | #define psc_status sr_csr.status | |
| 502 | #define psc_clock_select sr_csr.clock_select | |
| 503 | volatile u16 reserved1; | |
| 504 | volatile u8 command; /* PSC + 0x08 */ | |
| 505 | volatile u8 reserved2[3]; | |
| 506 | union { /* PSC + 0x0c */ | |
| 507 | volatile u8 buffer_8; | |
| 508 | volatile u16 buffer_16; | |
| 509 | volatile u32 buffer_32; | |
| 510 | } buffer; | |
| 511 | #define psc_buffer_8 buffer.buffer_8 | |
| 512 | #define psc_buffer_16 buffer.buffer_16 | |
| 513 | #define psc_buffer_32 buffer.buffer_32 | |
| 514 | union { /* PSC + 0x10 */ | |
| 515 | volatile u8 ipcr; | |
| 516 | volatile u8 acr; | |
| 517 | } ipcr_acr; | |
| 518 | #define psc_ipcr ipcr_acr.ipcr | |
| 519 | #define psc_acr ipcr_acr.acr | |
| 520 | volatile u8 reserved3[3]; | |
| 521 | union { /* PSC + 0x14 */ | |
| 522 | volatile u16 isr; | |
| 523 | volatile u16 imr; | |
| 524 | } isr_imr; | |
| 525 | #define psc_isr isr_imr.isr | |
| 526 | #define psc_imr isr_imr.imr | |
| 527 | volatile u16 reserved4; | |
| 528 | volatile u8 ctur; /* PSC + 0x18 */ | |
| 529 | volatile u8 reserved5[3]; | |
| 530 | volatile u8 ctlr; /* PSC + 0x1c */ | |
| 6617aae9 WD |
531 | volatile u8 reserved6[3]; |
| 532 | volatile u16 ccr; /* PSC + 0x20 */ | |
| 533 | volatile u8 reserved7[14]; | |
| 945af8d7 | 534 | volatile u8 ivr; /* PSC + 0x30 */ |
| 945af8d7 | 535 | volatile u8 reserved8[3]; |
| 6617aae9 | 536 | volatile u8 ip; /* PSC + 0x34 */ |
| 945af8d7 | 537 | volatile u8 reserved9[3]; |
| 6617aae9 | 538 | volatile u8 op1; /* PSC + 0x38 */ |
| 945af8d7 | 539 | volatile u8 reserved10[3]; |
| 6617aae9 | 540 | volatile u8 op0; /* PSC + 0x3c */ |
| 945af8d7 | 541 | volatile u8 reserved11[3]; |
| 6617aae9 | 542 | volatile u32 sicr; /* PSC + 0x40 */ |
| 945af8d7 WD |
543 | volatile u8 ircr1; /* PSC + 0x44 */ |
| 544 | volatile u8 reserved12[3]; | |
| 545 | volatile u8 ircr2; /* PSC + 0x44 */ | |
| 546 | volatile u8 reserved13[3]; | |
| 547 | volatile u8 irsdr; /* PSC + 0x4c */ | |
| 548 | volatile u8 reserved14[3]; | |
| 549 | volatile u8 irmdr; /* PSC + 0x50 */ | |
| 550 | volatile u8 reserved15[3]; | |
| 551 | volatile u8 irfdr; /* PSC + 0x54 */ | |
| 552 | volatile u8 reserved16[3]; | |
| 553 | volatile u16 rfnum; /* PSC + 0x58 */ | |
| 554 | volatile u16 reserved17; | |
| 555 | volatile u16 tfnum; /* PSC + 0x5c */ | |
| 556 | volatile u16 reserved18; | |
| 557 | volatile u32 rfdata; /* PSC + 0x60 */ | |
| 558 | volatile u16 rfstat; /* PSC + 0x64 */ | |
| 559 | volatile u16 reserved20; | |
| 560 | volatile u8 rfcntl; /* PSC + 0x68 */ | |
| 561 | volatile u8 reserved21[5]; | |
| 562 | volatile u16 rfalarm; /* PSC + 0x6e */ | |
| 563 | volatile u16 reserved22; | |
| 564 | volatile u16 rfrptr; /* PSC + 0x72 */ | |
| 565 | volatile u16 reserved23; | |
| 566 | volatile u16 rfwptr; /* PSC + 0x76 */ | |
| 567 | volatile u16 reserved24; | |
| 568 | volatile u16 rflrfptr; /* PSC + 0x7a */ | |
| 569 | volatile u16 reserved25; | |
| 570 | volatile u16 rflwfptr; /* PSC + 0x7e */ | |
| 571 | volatile u32 tfdata; /* PSC + 0x80 */ | |
| 572 | volatile u16 tfstat; /* PSC + 0x84 */ | |
| 573 | volatile u16 reserved26; | |
| 574 | volatile u8 tfcntl; /* PSC + 0x88 */ | |
| 575 | volatile u8 reserved27[5]; | |
| 576 | volatile u16 tfalarm; /* PSC + 0x8e */ | |
| 577 | volatile u16 reserved28; | |
| 578 | volatile u16 tfrptr; /* PSC + 0x92 */ | |
| 579 | volatile u16 reserved29; | |
| 580 | volatile u16 tfwptr; /* PSC + 0x96 */ | |
| 581 | volatile u16 reserved30; | |
| 582 | volatile u16 tflrfptr; /* PSC + 0x9a */ | |
| 583 | volatile u16 reserved31; | |
| 584 | volatile u16 tflwfptr; /* PSC + 0x9e */ | |
| 585 | }; | |
| 586 | ||
| 587 | struct mpc5xxx_intr { | |
| 588 | volatile u32 per_mask; /* INTR + 0x00 */ | |
| 589 | volatile u32 per_pri1; /* INTR + 0x04 */ | |
| 590 | volatile u32 per_pri2; /* INTR + 0x08 */ | |
| 591 | volatile u32 per_pri3; /* INTR + 0x0c */ | |
| 592 | volatile u32 ctrl; /* INTR + 0x10 */ | |
| 593 | volatile u32 main_mask; /* INTR + 0x14 */ | |
| 594 | volatile u32 main_pri1; /* INTR + 0x18 */ | |
| 595 | volatile u32 main_pri2; /* INTR + 0x1c */ | |
| 596 | volatile u32 reserved1; /* INTR + 0x20 */ | |
| 597 | volatile u32 enc_status; /* INTR + 0x24 */ | |
| 598 | volatile u32 crit_status; /* INTR + 0x28 */ | |
| 599 | volatile u32 main_status; /* INTR + 0x2c */ | |
| 600 | volatile u32 per_status; /* INTR + 0x30 */ | |
| 601 | volatile u32 reserved2; /* INTR + 0x34 */ | |
| 602 | volatile u32 per_error; /* INTR + 0x38 */ | |
| 603 | }; | |
| 604 | ||
| 605 | struct mpc5xxx_gpio { | |
| 606 | volatile u32 port_config; /* GPIO + 0x00 */ | |
| 607 | volatile u32 simple_gpioe; /* GPIO + 0x04 */ | |
| 608 | volatile u32 simple_ode; /* GPIO + 0x08 */ | |
| 609 | volatile u32 simple_ddr; /* GPIO + 0x0c */ | |
| 610 | volatile u32 simple_dvo; /* GPIO + 0x10 */ | |
| 611 | volatile u32 simple_ival; /* GPIO + 0x14 */ | |
| 612 | volatile u8 outo_gpioe; /* GPIO + 0x18 */ | |
| 613 | volatile u8 reserved1[3]; /* GPIO + 0x19 */ | |
| 614 | volatile u8 outo_dvo; /* GPIO + 0x1c */ | |
| 615 | volatile u8 reserved2[3]; /* GPIO + 0x1d */ | |
| 616 | volatile u8 sint_gpioe; /* GPIO + 0x20 */ | |
| 617 | volatile u8 reserved3[3]; /* GPIO + 0x21 */ | |
| 618 | volatile u8 sint_ode; /* GPIO + 0x24 */ | |
| 619 | volatile u8 reserved4[3]; /* GPIO + 0x25 */ | |
| 620 | volatile u8 sint_ddr; /* GPIO + 0x28 */ | |
| 621 | volatile u8 reserved5[3]; /* GPIO + 0x29 */ | |
| 622 | volatile u8 sint_dvo; /* GPIO + 0x2c */ | |
| 623 | volatile u8 reserved6[3]; /* GPIO + 0x2d */ | |
| 624 | volatile u8 sint_inten; /* GPIO + 0x30 */ | |
| 625 | volatile u8 reserved7[3]; /* GPIO + 0x31 */ | |
| 626 | volatile u16 sint_itype; /* GPIO + 0x34 */ | |
| 627 | volatile u16 reserved8; /* GPIO + 0x36 */ | |
| 628 | volatile u8 gpio_control; /* GPIO + 0x38 */ | |
| 629 | volatile u8 reserved9[3]; /* GPIO + 0x39 */ | |
| 630 | volatile u8 sint_istat; /* GPIO + 0x3c */ | |
| 631 | volatile u8 sint_ival; /* GPIO + 0x3d */ | |
| 632 | volatile u8 bus_errs; /* GPIO + 0x3e */ | |
| 633 | volatile u8 reserved10; /* GPIO + 0x3f */ | |
| 634 | }; | |
| 635 | ||
| 4e325fbf DZ |
636 | struct mpc5xxx_wu_gpio { |
| 637 | volatile u8 enable; /* WU_GPIO + 0x00 */ | |
| 638 | volatile u8 reserved1[3]; /* WU_GPIO + 0x01 */ | |
| 639 | volatile u8 ode; /* WU_GPIO + 0x04 */ | |
| 640 | volatile u8 reserved2[3]; /* WU_GPIO + 0x05 */ | |
| 641 | volatile u8 ddr; /* WU_GPIO + 0x08 */ | |
| 642 | volatile u8 reserved3[3]; /* WU_GPIO + 0x09 */ | |
| 643 | volatile u8 dvo; /* WU_GPIO + 0x0c */ | |
| 644 | volatile u8 reserved4[3]; /* WU_GPIO + 0x0d */ | |
| 645 | volatile u8 inten; /* WU_GPIO + 0x10 */ | |
| 646 | volatile u8 reserved5[3]; /* WU_GPIO + 0x11 */ | |
| 647 | volatile u8 iinten; /* WU_GPIO + 0x14 */ | |
| 648 | volatile u8 reserved6[3]; /* WU_GPIO + 0x15 */ | |
| 649 | volatile u16 itype; /* WU_GPIO + 0x18 */ | |
| 650 | volatile u8 reserved7[2]; /* WU_GPIO + 0x1a */ | |
| 651 | volatile u8 master_enable; /* WU_GPIO + 0x1c */ | |
| 652 | volatile u8 reserved8[3]; /* WU_GPIO + 0x1d */ | |
| 653 | volatile u8 ival; /* WU_GPIO + 0x20 */ | |
| 654 | volatile u8 reserved9[3]; /* WU_GPIO + 0x21 */ | |
| 655 | volatile u8 status; /* WU_GPIO + 0x24 */ | |
| 656 | volatile u8 reserved10[3]; /* WU_GPIO + 0x25 */ | |
| 657 | }; | |
| 658 | ||
| 945af8d7 WD |
659 | struct mpc5xxx_sdma { |
| 660 | volatile u32 taskBar; /* SDMA + 0x00 */ | |
| 661 | volatile u32 currentPointer; /* SDMA + 0x04 */ | |
| 662 | volatile u32 endPointer; /* SDMA + 0x08 */ | |
| 663 | volatile u32 variablePointer; /* SDMA + 0x0c */ | |
| 664 | ||
| 665 | volatile u8 IntVect1; /* SDMA + 0x10 */ | |
| 666 | volatile u8 IntVect2; /* SDMA + 0x11 */ | |
| 667 | volatile u16 PtdCntrl; /* SDMA + 0x12 */ | |
| 668 | ||
| 669 | volatile u32 IntPend; /* SDMA + 0x14 */ | |
| 670 | volatile u32 IntMask; /* SDMA + 0x18 */ | |
| 671 | ||
| 672 | volatile u16 tcr_0; /* SDMA + 0x1c */ | |
| 673 | volatile u16 tcr_1; /* SDMA + 0x1e */ | |
| 674 | volatile u16 tcr_2; /* SDMA + 0x20 */ | |
| 675 | volatile u16 tcr_3; /* SDMA + 0x22 */ | |
| 676 | volatile u16 tcr_4; /* SDMA + 0x24 */ | |
| 677 | volatile u16 tcr_5; /* SDMA + 0x26 */ | |
| 678 | volatile u16 tcr_6; /* SDMA + 0x28 */ | |
| 679 | volatile u16 tcr_7; /* SDMA + 0x2a */ | |
| 680 | volatile u16 tcr_8; /* SDMA + 0x2c */ | |
| 681 | volatile u16 tcr_9; /* SDMA + 0x2e */ | |
| 682 | volatile u16 tcr_a; /* SDMA + 0x30 */ | |
| 683 | volatile u16 tcr_b; /* SDMA + 0x32 */ | |
| 684 | volatile u16 tcr_c; /* SDMA + 0x34 */ | |
| 685 | volatile u16 tcr_d; /* SDMA + 0x36 */ | |
| 686 | volatile u16 tcr_e; /* SDMA + 0x38 */ | |
| 687 | volatile u16 tcr_f; /* SDMA + 0x3a */ | |
| 688 | ||
| 689 | volatile u8 IPR0; /* SDMA + 0x3c */ | |
| 690 | volatile u8 IPR1; /* SDMA + 0x3d */ | |
| 691 | volatile u8 IPR2; /* SDMA + 0x3e */ | |
| 692 | volatile u8 IPR3; /* SDMA + 0x3f */ | |
| 693 | volatile u8 IPR4; /* SDMA + 0x40 */ | |
| 694 | volatile u8 IPR5; /* SDMA + 0x41 */ | |
| 695 | volatile u8 IPR6; /* SDMA + 0x42 */ | |
| 696 | volatile u8 IPR7; /* SDMA + 0x43 */ | |
| 697 | volatile u8 IPR8; /* SDMA + 0x44 */ | |
| 698 | volatile u8 IPR9; /* SDMA + 0x45 */ | |
| 699 | volatile u8 IPR10; /* SDMA + 0x46 */ | |
| 700 | volatile u8 IPR11; /* SDMA + 0x47 */ | |
| 701 | volatile u8 IPR12; /* SDMA + 0x48 */ | |
| 702 | volatile u8 IPR13; /* SDMA + 0x49 */ | |
| 703 | volatile u8 IPR14; /* SDMA + 0x4a */ | |
| 704 | volatile u8 IPR15; /* SDMA + 0x4b */ | |
| 705 | volatile u8 IPR16; /* SDMA + 0x4c */ | |
| 706 | volatile u8 IPR17; /* SDMA + 0x4d */ | |
| 707 | volatile u8 IPR18; /* SDMA + 0x4e */ | |
| 708 | volatile u8 IPR19; /* SDMA + 0x4f */ | |
| 709 | volatile u8 IPR20; /* SDMA + 0x50 */ | |
| 710 | volatile u8 IPR21; /* SDMA + 0x51 */ | |
| 711 | volatile u8 IPR22; /* SDMA + 0x52 */ | |
| 712 | volatile u8 IPR23; /* SDMA + 0x53 */ | |
| 713 | volatile u8 IPR24; /* SDMA + 0x54 */ | |
| 714 | volatile u8 IPR25; /* SDMA + 0x55 */ | |
| 715 | volatile u8 IPR26; /* SDMA + 0x56 */ | |
| 716 | volatile u8 IPR27; /* SDMA + 0x57 */ | |
| 717 | volatile u8 IPR28; /* SDMA + 0x58 */ | |
| 718 | volatile u8 IPR29; /* SDMA + 0x59 */ | |
| 719 | volatile u8 IPR30; /* SDMA + 0x5a */ | |
| 720 | volatile u8 IPR31; /* SDMA + 0x5b */ | |
| 721 | ||
| 722 | volatile u32 res1; /* SDMA + 0x5c */ | |
| 723 | volatile u32 res2; /* SDMA + 0x60 */ | |
| 724 | volatile u32 res3; /* SDMA + 0x64 */ | |
| 725 | volatile u32 MDEDebug; /* SDMA + 0x68 */ | |
| 726 | volatile u32 ADSDebug; /* SDMA + 0x6c */ | |
| 727 | volatile u32 Value1; /* SDMA + 0x70 */ | |
| 728 | volatile u32 Value2; /* SDMA + 0x74 */ | |
| 729 | volatile u32 Control; /* SDMA + 0x78 */ | |
| 730 | volatile u32 Status; /* SDMA + 0x7c */ | |
| 731 | volatile u32 EU00; /* SDMA + 0x80 */ | |
| 732 | volatile u32 EU01; /* SDMA + 0x84 */ | |
| 733 | volatile u32 EU02; /* SDMA + 0x88 */ | |
| 734 | volatile u32 EU03; /* SDMA + 0x8c */ | |
| 735 | volatile u32 EU04; /* SDMA + 0x90 */ | |
| 736 | volatile u32 EU05; /* SDMA + 0x94 */ | |
| 737 | volatile u32 EU06; /* SDMA + 0x98 */ | |
| 738 | volatile u32 EU07; /* SDMA + 0x9c */ | |
| 739 | volatile u32 EU10; /* SDMA + 0xa0 */ | |
| 740 | volatile u32 EU11; /* SDMA + 0xa4 */ | |
| 741 | volatile u32 EU12; /* SDMA + 0xa8 */ | |
| 742 | volatile u32 EU13; /* SDMA + 0xac */ | |
| 743 | volatile u32 EU14; /* SDMA + 0xb0 */ | |
| 744 | volatile u32 EU15; /* SDMA + 0xb4 */ | |
| 745 | volatile u32 EU16; /* SDMA + 0xb8 */ | |
| 746 | volatile u32 EU17; /* SDMA + 0xbc */ | |
| 747 | volatile u32 EU20; /* SDMA + 0xc0 */ | |
| 748 | volatile u32 EU21; /* SDMA + 0xc4 */ | |
| 749 | volatile u32 EU22; /* SDMA + 0xc8 */ | |
| 750 | volatile u32 EU23; /* SDMA + 0xcc */ | |
| 751 | volatile u32 EU24; /* SDMA + 0xd0 */ | |
| 752 | volatile u32 EU25; /* SDMA + 0xd4 */ | |
| 753 | volatile u32 EU26; /* SDMA + 0xd8 */ | |
| 754 | volatile u32 EU27; /* SDMA + 0xdc */ | |
| 755 | volatile u32 EU30; /* SDMA + 0xe0 */ | |
| 756 | volatile u32 EU31; /* SDMA + 0xe4 */ | |
| 757 | volatile u32 EU32; /* SDMA + 0xe8 */ | |
| 758 | volatile u32 EU33; /* SDMA + 0xec */ | |
| 759 | volatile u32 EU34; /* SDMA + 0xf0 */ | |
| 760 | volatile u32 EU35; /* SDMA + 0xf4 */ | |
| 761 | volatile u32 EU36; /* SDMA + 0xf8 */ | |
| 762 | volatile u32 EU37; /* SDMA + 0xfc */ | |
| 763 | }; | |
| 764 | ||
| 531716e1 WD |
765 | struct mpc5xxx_i2c { |
| 766 | volatile u32 madr; /* I2Cn + 0x00 */ | |
| 767 | volatile u32 mfdr; /* I2Cn + 0x04 */ | |
| 768 | volatile u32 mcr; /* I2Cn + 0x08 */ | |
| 769 | volatile u32 msr; /* I2Cn + 0x0C */ | |
| 770 | volatile u32 mdr; /* I2Cn + 0x10 */ | |
| 771 | }; | |
| 772 | ||
| 6617aae9 WD |
773 | struct mpc5xxx_spi { |
| 774 | volatile u8 cr1; /* SPI + 0x0F00 */ | |
| 775 | volatile u8 cr2; /* SPI + 0x0F01 */ | |
| 776 | volatile u8 reserved1[2]; | |
| 777 | volatile u8 brr; /* SPI + 0x0F04 */ | |
| 778 | volatile u8 sr; /* SPI + 0x0F05 */ | |
| 779 | volatile u8 reserved2[3]; | |
| 780 | volatile u8 dr; /* SPI + 0x0F09 */ | |
| 781 | volatile u8 reserved3[3]; | |
| 782 | volatile u8 pdr; /* SPI + 0x0F0D */ | |
| 783 | volatile u8 reserved4[2]; | |
| 784 | volatile u8 ddr; /* SPI + 0x0F10 */ | |
| 785 | }; | |
| 786 | ||
| 787 | ||
| 788 | struct mpc5xxx_gpt { | |
| 789 | volatile u32 emsr; /* GPT + Timer# * 0x10 + 0x00 */ | |
| 790 | volatile u32 cir; /* GPT + Timer# * 0x10 + 0x04 */ | |
| 791 | volatile u32 pwmcr; /* GPT + Timer# * 0x10 + 0x08 */ | |
| 792 | volatile u32 sr; /* GPT + Timer# * 0x10 + 0x0c */ | |
| 793 | }; | |
| 794 | ||
| 795 | struct mpc5xxx_gpt_0_7 { | |
| 796 | struct mpc5xxx_gpt gpt0; | |
| 797 | struct mpc5xxx_gpt gpt1; | |
| 798 | struct mpc5xxx_gpt gpt2; | |
| 799 | struct mpc5xxx_gpt gpt3; | |
| 800 | struct mpc5xxx_gpt gpt4; | |
| 801 | struct mpc5xxx_gpt gpt5; | |
| 802 | struct mpc5xxx_gpt gpt6; | |
| 803 | struct mpc5xxx_gpt gpt7; | |
| 804 | }; | |
| 805 | ||
| 806 | struct mscan_buffer { | |
| 807 | volatile u8 idr[0x8]; /* 0x00 */ | |
| 808 | volatile u8 dsr[0x10]; /* 0x08 */ | |
| 809 | volatile u8 dlr; /* 0x18 */ | |
| 810 | volatile u8 tbpr; /* 0x19 */ /* This register is not applicable for receive buffers */ | |
| 811 | volatile u16 rsrv1; /* 0x1A */ | |
| 812 | volatile u8 tsrh; /* 0x1C */ | |
| 813 | volatile u8 tsrl; /* 0x1D */ | |
| 814 | volatile u16 rsrv2; /* 0x1E */ | |
| 815 | }; | |
| 816 | ||
| 817 | struct mpc5xxx_mscan { | |
| 818 | volatile u8 canctl0; /* MSCAN + 0x00 */ | |
| 819 | volatile u8 canctl1; /* MSCAN + 0x01 */ | |
| 820 | volatile u16 rsrv1; /* MSCAN + 0x02 */ | |
| 821 | volatile u8 canbtr0; /* MSCAN + 0x04 */ | |
| 822 | volatile u8 canbtr1; /* MSCAN + 0x05 */ | |
| 823 | volatile u16 rsrv2; /* MSCAN + 0x06 */ | |
| 824 | volatile u8 canrflg; /* MSCAN + 0x08 */ | |
| 825 | volatile u8 canrier; /* MSCAN + 0x09 */ | |
| 826 | volatile u16 rsrv3; /* MSCAN + 0x0A */ | |
| 827 | volatile u8 cantflg; /* MSCAN + 0x0C */ | |
| 828 | volatile u8 cantier; /* MSCAN + 0x0D */ | |
| 829 | volatile u16 rsrv4; /* MSCAN + 0x0E */ | |
| 830 | volatile u8 cantarq; /* MSCAN + 0x10 */ | |
| 831 | volatile u8 cantaak; /* MSCAN + 0x11 */ | |
| 832 | volatile u16 rsrv5; /* MSCAN + 0x12 */ | |
| 833 | volatile u8 cantbsel; /* MSCAN + 0x14 */ | |
| 834 | volatile u8 canidac; /* MSCAN + 0x15 */ | |
| 835 | volatile u16 rsrv6[3]; /* MSCAN + 0x16 */ | |
| 836 | volatile u8 canrxerr; /* MSCAN + 0x1C */ | |
| 837 | volatile u8 cantxerr; /* MSCAN + 0x1D */ | |
| 838 | volatile u16 rsrv7; /* MSCAN + 0x1E */ | |
| 839 | volatile u8 canidar0; /* MSCAN + 0x20 */ | |
| 840 | volatile u8 canidar1; /* MSCAN + 0x21 */ | |
| 841 | volatile u16 rsrv8; /* MSCAN + 0x22 */ | |
| 842 | volatile u8 canidar2; /* MSCAN + 0x24 */ | |
| 843 | volatile u8 canidar3; /* MSCAN + 0x25 */ | |
| 844 | volatile u16 rsrv9; /* MSCAN + 0x26 */ | |
| 845 | volatile u8 canidmr0; /* MSCAN + 0x28 */ | |
| 846 | volatile u8 canidmr1; /* MSCAN + 0x29 */ | |
| 847 | volatile u16 rsrv10; /* MSCAN + 0x2A */ | |
| 848 | volatile u8 canidmr2; /* MSCAN + 0x2C */ | |
| 849 | volatile u8 canidmr3; /* MSCAN + 0x2D */ | |
| 850 | volatile u16 rsrv11; /* MSCAN + 0x2E */ | |
| 851 | volatile u8 canidar4; /* MSCAN + 0x30 */ | |
| 852 | volatile u8 canidar5; /* MSCAN + 0x31 */ | |
| 853 | volatile u16 rsrv12; /* MSCAN + 0x32 */ | |
| 854 | volatile u8 canidar6; /* MSCAN + 0x34 */ | |
| 855 | volatile u8 canidar7; /* MSCAN + 0x35 */ | |
| 856 | volatile u16 rsrv13; /* MSCAN + 0x36 */ | |
| 857 | volatile u8 canidmr4; /* MSCAN + 0x38 */ | |
| 858 | volatile u8 canidmr5; /* MSCAN + 0x39 */ | |
| 859 | volatile u16 rsrv14; /* MSCAN + 0x3A */ | |
| 860 | volatile u8 canidmr6; /* MSCAN + 0x3C */ | |
| 861 | volatile u8 canidmr7; /* MSCAN + 0x3D */ | |
| 862 | volatile u16 rsrv15; /* MSCAN + 0x3E */ | |
| 863 | ||
| 864 | struct mscan_buffer canrxfg; /* MSCAN + 0x40 */ /* Foreground receive buffer */ | |
| 865 | struct mscan_buffer cantxfg; /* MSCAN + 0x60 */ /* Foreground transmit buffer */ | |
| 866 | }; | |
| 867 | ||
| 18e89890 DZ |
868 | struct mpc5xxx_xlb { |
| 869 | volatile u8 reserved[0x40]; /* XLB + 0x00 */ | |
| 870 | volatile u32 config; /* XLB + 0x40 */ | |
| 871 | volatile u32 version; /* XLB + 0x44 */ | |
| 872 | volatile u32 status; /* XLB + 0x48 */ | |
| 873 | volatile u32 int_enable; /* XLB + 0x4c */ | |
| 874 | volatile u32 addr_capture; /* XLB + 0x50 */ | |
| 875 | volatile u32 bus_sig_capture; /* XLB + 0x54 */ | |
| 876 | volatile u32 addr_timeout; /* XLB + 0x58 */ | |
| 877 | volatile u32 data_timeout; /* XLB + 0x5c */ | |
| 878 | volatile u32 bus_act_timeout; /* XLB + 0x60 */ | |
| 879 | volatile u32 master_pri_enable; /* XLB + 0x64 */ | |
| 880 | volatile u32 master_priority; /* XLB + 0x68 */ | |
| 881 | volatile u32 base_address; /* XLB + 0x6c */ | |
| 882 | volatile u32 snoop_window; /* XLB + 0x70 */ | |
| 883 | }; | |
| 884 | ||
| 3d500013 AG |
885 | struct pci_controller; |
| 886 | ||
| 945af8d7 WD |
887 | /* function prototypes */ |
| 888 | void loadtask(int basetask, int tasks); | |
| 3d500013 | 889 | void pci_mpc5xxx_init(struct pci_controller *); |
| 945af8d7 WD |
890 | |
| 891 | #endif /* __ASSEMBLY__ */ | |
| 892 | ||
| 893 | #endif /* __ASMPPC_MPC5XXX_H */ |