projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 945af8d7 WD |
1 | /* |
| 2 | * (C) Copyright 2003 | |
| 3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
| 4 | * | |
| 5 | * This file is based on code | |
| 6 | * (C) Copyright Motorola, Inc., 2000 | |
| 7 | * | |
| 8 | * odin smartdma header file | |
| 9 | */ | |
| 10 | ||
| 11 | #ifndef __MPC5XXX_SDMA_H | |
| 12 | #define __MPC5XXX_SDMA_H | |
| 13 | ||
| 14 | #include <common.h> | |
| 15 | #include <mpc5xxx.h> | |
| 16 | ||
| 17 | /* Task number assignment */ | |
| 18 | #define FEC_RECV_TASK_NO 0 | |
| 19 | #define FEC_XMIT_TASK_NO 1 | |
| 20 | ||
| 21 | /*---------------------------------------------------------------------*/ | |
| 22 | ||
| 23 | /* Stuff for Ethernet Tx/Rx tasks */ | |
| 24 | ||
| 25 | /*---------------------------------------------------------------------*/ | |
| 26 | ||
| 27 | /* Layout of Ethernet controller Parameter SRAM area: | |
| 28 | ---------------------------------------------------------------- | |
| 29 | 0x00: TBD_BASE, base address of TX BD ring | |
| 30 | 0x04: TBD_NEXT, address of next TX BD to be processed | |
| 31 | 0x08: RBD_BASE, base address of RX BD ring | |
| 32 | 0x0C: RBD_NEXT, address of next RX BD to be processed | |
| 33 | --------------------------------------------------------------- | |
| 34 | ALL PARAMETERS ARE ALL LONGWORDS (FOUR BYTES EACH). | |
| 35 | */ | |
| 36 | ||
| 37 | /* base address of SRAM area to store parameters used by Ethernet tasks */ | |
| 38 | #define FEC_PARAM_BASE (MPC5XXX_SRAM + 0x0800) | |
| 39 | ||
| 40 | /* base address of SRAM area for buffer descriptors */ | |
| 41 | #define FEC_BD_BASE (MPC5XXX_SRAM + 0x0820) | |
| 42 | ||
| 43 | /*---------------------------------------------------------------------*/ | |
| 44 | ||
| 45 | /* common shortcuts used by driver C code */ | |
| 46 | ||
| 47 | /*---------------------------------------------------------------------*/ | |
| 48 | ||
| 49 | /* Disable SmartDMA task */ | |
| 50 | #define SDMA_TASK_DISABLE(tasknum) \ | |
| 51 | { \ | |
| 52 | volatile ushort *tcr = (ushort *)(MPC5XXX_SDMA + 0x0000001c + 2 * tasknum); \ | |
| 53 | *tcr = (*tcr) & (~0x8000); \ | |
| 54 | } | |
| 55 | ||
| 56 | /* Enable SmartDMA task */ | |
| 57 | #define SDMA_TASK_ENABLE(tasknum) \ | |
| 58 | { \ | |
| 59 | volatile ushort *tcr = (ushort *) (MPC5XXX_SDMA + 0x0000001c + 2 * tasknum); \ | |
| 60 | *tcr = (*tcr) | 0x8000; \ | |
| 61 | } | |
| 62 | ||
| 63 | /* Enable interrupt */ | |
| 64 | #define SDMA_INT_ENABLE(tasknum) \ | |
| 65 | { \ | |
| 66 | struct mpc5xxx_sdma *sdma = (struct mpc5xxx_sdma *)MPC5XXX_SDMA; \ | |
| 67 | sdma->IntMask &= ~(1 << tasknum); \ | |
| 68 | } | |
| 69 | ||
| 70 | /* Disable interrupt */ | |
| 71 | #define SDMA_INT_DISABLE(tasknum) \ | |
| 72 | { \ | |
| 73 | struct mpc5xxx_sdma *sdma = (struct mpc5xxx_sdma *)MPC5XXX_SDMA; \ | |
| 74 | sdma->IntMask |= (1 << tasknum); \ | |
| 75 | } | |
| 76 | ||
| 77 | ||
| 78 | /* Clear interrupt pending bits */ | |
| 79 | #define SDMA_CLEAR_IEVENT(tasknum) \ | |
| 80 | { \ | |
| 81 | struct mpc5xxx_sdma *sdma = (struct mpc5xxx_sdma *)MPC5XXX_SDMA; \ | |
| 82 | sdma->IntPend = (1 << tasknum); \ | |
| 83 | } | |
| 84 | ||
| 16263087 | 85 | /* get interrupt pending bit of a task */ |
| 945af8d7 WD |
86 | #define SDMA_GET_PENDINGBIT(tasknum) \ |
| 87 | ((*(vu_long *)(MPC5XXX_SDMA + 0x14)) & (1<<(tasknum))) | |
| 88 | ||
| 16263087 | 89 | /* get interrupt mask bit of a task */ |
| 945af8d7 WD |
90 | #define SDMA_GET_MASKBIT(tasknum) \ |
| 91 | ((*(vu_long *)(MPC5XXX_SDMA + 0x18)) & (1<<(tasknum))) | |
| 92 | ||
| 93 | #endif /* __MPC5XXX_SDMA_H */ |