projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| c609719b WD |
1 | /* |
| 2 | * Copyright Rob Taylor, Flying Pig Systems Ltd. 2000. | |
| 3 | * Copyright (C) 2001, James Dougherty, jfd@cs.stanford.edu | |
| 4 | * | |
| 3765b3e7 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
| c609719b WD |
6 | */ |
| 7 | ||
| 8 | #ifndef __MPC824X_H__ | |
| 9 | #define __MPC824X_H__ | |
| 10 | ||
| 11 | #include <config.h> | |
| 12 | ||
| 13 | /* CPU Types */ | |
| 14 | #define CPU_TYPE_601 0x01 /* PPC 601 CPU */ | |
| 15 | #define CPU_TYPE_602 0x02 /* PPC 602 CPU */ | |
| 16 | #define CPU_TYPE_603 0x03 /* PPC 603 CPU */ | |
| 17 | #define CPU_TYPE_603E 0x06 /* PPC 603e CPU */ | |
| 18 | #define CPU_TYPE_603P 0x07 /* PPC 603p CPU */ | |
| 19 | #define CPU_TYPE_604 0x04 /* PPC 604 CPU */ | |
| 20 | #define CPU_TYPE_604E 0x09 /* PPC 604e CPU */ | |
| 21 | #define CPU_TYPE_604R 0x0a /* PPC 604r CPU */ | |
| 22 | #define CPU_TYPE_750 0x08 /* PPC 750 CPU */ | |
| 23 | #define CPU_TYPE_8240 0x81 /* PPC 8240 CPU */ | |
| 24 | #define CPU_TYPE_8245 0x8081 /* PPC 8245/8241 CPU */ | |
| 25 | #define _CACHE_ALIGN_SIZE 32 /* cache line size */ | |
| 26 | ||
| 27 | /* spr976 - DMISS data tlb miss address register | |
| 28 | * spr977 - DCMP data tlb miss compare register | |
| 29 | * spr978 - HASH1 PTEG1 address register | |
| 30 | * spr980 - HASH2 PTEG2 address register | |
| 31 | * IMISS - instruction tlb miss address register | |
| 32 | * ICMP - instruction TLB mis compare register | |
| 33 | * RPA - real page address register | |
| 34 | * HID0 - hardware implemntation register | |
| 35 | * HID2 - instruction address breakpoint register | |
| 36 | */ | |
| 37 | ||
| 38 | /* Kahlua/MPC8240 defines */ | |
| 39 | #define VEN_DEV_ID 0x00021057 /* Vendor and Dev. ID for MPC106 */ | |
| 40 | #define KAHLUA_ID 0x00031057 /* Vendor & Dev Id for Kahlua's PCI */ | |
| 41 | #define KAHLUA2_ID 0x00061057 /* 8245 is aka Kahlua-2 */ | |
| 42 | #define BMC_BASE 0x80000000 /* Kahlua ID in PCI Memory space */ | |
| 43 | #define CHRP_REG_ADDR 0xfec00000 /* MPC107 Config, Map B */ | |
| 44 | #define CHRP_REG_DATA 0xfee00000 /* MPC107 Config, Map B */ | |
| 45 | #define CHRP_ISA_MEM_PHYS 0xfd000000 | |
| 46 | #define CHRP_ISA_MEM_BUS 0x00000000 | |
| 47 | #define CHRP_ISA_MEM_SIZE 0x01000000 | |
| 48 | #define CHRP_ISA_IO_PHYS 0xfe000000 | |
| 49 | #define CHRP_ISA_IO_BUS 0x00000000 | |
| 50 | #define CHRP_ISA_IO_SIZE 0x00800000 | |
| 51 | #define CHRP_PCI_IO_PHYS 0xfe800000 | |
| 52 | #define CHRP_PCI_IO_BUS 0x00800000 | |
| 53 | #define CHRP_PCI_IO_SIZE 0x00400000 | |
| 54 | #define CHRP_PCI_MEM_PHYS 0x80000000 | |
| 55 | #define CHRP_PCI_MEM_BUS 0x80000000 | |
| 56 | #define CHRP_PCI_MEM_SIZE 0x7d000000 | |
| 57 | #define CHRP_PCI_MEMORY_PHYS 0x00000000 | |
| 58 | #define CHRP_PCI_MEMORY_BUS 0x00000000 | |
| 59 | #define CHRP_PCI_MEMORY_SIZE 0x40000000 | |
| 60 | #define PREP_REG_ADDR 0x80000cf8 /* MPC107 Config, Map A */ | |
| 61 | #define PREP_REG_DATA 0x80000cfc /* MPC107 Config, Map A */ | |
| 62 | #define PREP_ISA_IO_PHYS 0x80000000 | |
| 63 | #define PREP_ISA_IO_BUS 0x00000000 | |
| 64 | #define PREP_ISA_IO_SIZE 0x00800000 | |
| 65 | #define PREP_PCI_IO_PHYS 0x81000000 | |
| 66 | #define PREP_PCI_IO_BUS 0x01000000 | |
| 67 | #define PREP_PCI_IO_SIZE 0x3e800000 | |
| 68 | #define PREP_PCI_MEM_PHYS 0xc0000000 | |
| 69 | #define PREP_PCI_MEM_BUS 0x00000000 | |
| 70 | #define PREP_PCI_MEM_SIZE 0x3f000000 | |
| 71 | #define PREP_PCI_MEMORY_PHYS 0x00000000 | |
| 72 | #define PREP_PCI_MEMORY_BUS 0x80000000 | |
| 73 | #define PREP_PCI_MEMORY_SIZE 0x80000000 | |
| 74 | #define MPC107_PCI_CMD 0x80000004 /* MPC107 PCI cmd reg */ | |
| 1636d1c8 | 75 | #define MPC107_PCI_STAT 0x80000006 /* MPC107 PCI status reg */ |
| c609719b WD |
76 | #define PROC_INT1_ADR 0x800000a8 /* MPC107 Processor i/f cfg1 */ |
| 77 | #define PROC_INT2_ADR 0x800000ac /* MPC107 Processor i/f cfg2 */ | |
| 78 | #define MEM_CONT1_ADR 0x800000f0 /* MPC107 Memory control config. 1 */ | |
| 79 | #define MEM_CONT2_ADR 0x800000f4 /* MPC107 Memory control config. 2 */ | |
| 80 | #define MEM_CONT3_ADR 0x800000f8 /* MPC107 Memory control config. 3 */ | |
| 81 | #define MEM_CONT4_ADR 0x800000fc /* MPC107 Memory control config. 4 */ | |
| 82 | #define MEM_ERREN1_ADR 0x800000c0 /* MPC107 Memory error enable 1 */ | |
| 83 | #define MEM_START1_ADR 0x80000080 /* MPC107 Memory starting addr */ | |
| 84 | #define MEM_START2_ADR 0x80000084 /* MPC107 Memory starting addr-lo */ | |
| 1636d1c8 WD |
85 | #define XMEM_START1_ADR 0x80000088 /* MPC107 Extended mem. start addr-hi*/ |
| 86 | #define XMEM_START2_ADR 0x8000008c /* MPC107 Extended mem. start addr-lo*/ | |
| c609719b WD |
87 | #define MEM_END1_ADR 0x80000090 /* MPC107 Memory ending address */ |
| 88 | #define MEM_END2_ADR 0x80000094 /* MPC107 Memory ending addr-lo */ | |
| 89 | #define XMEM_END1_ADR 0x80000098 /* MPC107 Extended mem. end addrs-hi */ | |
| 90 | #define XMEM_END2_ADR 0x8000009c /* MPC107 Extended mem. end addrs-lo*/ | |
| 91 | #define OUT_DRV_CONT 0x80000073 /* MPC107 Output Driver Control reg */ | |
| 92 | #define MEM_EN_ADR 0x800000a0 /* Memory bank enable */ | |
| 93 | #define PAGE_MODE 0x800000a3 /* MPC107 Page Mode Counter/Timer */ | |
| 94 | ||
| 95 | /*----------------------------------------------------------------------- | |
| 96 | * Exception offsets (PowerPC standard) | |
| 97 | */ | |
| 98 | #define EXC_OFF_RESERVED0 0x0000 /* Reserved */ | |
| 99 | #define EXC_OFF_SYS_RESET 0x0100 /* System reset */ | |
| 100 | #define EXC_OFF_MACH_CHCK 0x0200 /* Machine Check */ | |
| 101 | #define EXC_OFF_DATA_STOR 0x0300 /* Data Storage */ | |
| 102 | #define EXC_OFF_INS_STOR 0x0400 /* Instruction Storage */ | |
| 103 | #define EXC_OFF_EXTERNAL 0x0500 /* External */ | |
| 104 | #define EXC_OFF_ALIGN 0x0600 /* Alignment */ | |
| 105 | #define EXC_OFF_PROGRAM 0x0700 /* Program */ | |
| 106 | #define EXC_OFF_FPUNAVAIL 0x0800 /* Floating-point Unavailable */ | |
| 107 | #define EXC_OFF_DECR 0x0900 /* Decrementer */ | |
| 108 | #define EXC_OFF_RESERVED1 0x0A00 /* Reserved */ | |
| 109 | #define EXC_OFF_RESERVED2 0x0B00 /* Reserved */ | |
| 110 | #define EXC_OFF_SYS_CALL 0x0C00 /* System Call */ | |
| 111 | #define EXC_OFF_TRACE 0x0D00 /* Trace */ | |
| 112 | #define EXC_OFF_FPUNASSIST 0x0E00 /* Floating-point Assist */ | |
| 113 | ||
| 114 | /* 0x0E10 - 0x0FFF are marked reserved in The PowerPC Architecture book */ | |
| 115 | /* these found in DINK code - may not apply to 8240*/ | |
| 116 | #define EXC_OFF_PMI 0x0F00 /* Performance Monitoring Interrupt */ | |
| 117 | #define EXC_OFF_VMXUI 0x0F20 /* VMX (AltiVec) Unavailable Interrupt */ | |
| 118 | ||
| 119 | /* 0x1000 - 0x2FFF are implementation specific */ | |
| 120 | /* these found in DINK code - may not apply to 8240 */ | |
| 121 | #define EXC_OFF_ITME 0x1000 /* Instruction Translation Miss Exception */ | |
| 122 | #define EXC_OFF_DLTME 0x1100 /* Data Load Translation Miss Exception */ | |
| 123 | #define EXC_OFF_DSTME 0x1200 /* Data Store Translation Miss Exception */ | |
| 124 | #define EXC_OFF_IABE 0x1300 /* Instruction Addr Breakpoint Exception */ | |
| 125 | #define EXC_OFF_SMIE 0x1400 /* System Management Interrupt Exception */ | |
| 126 | #define EXC_OFF_JMDDI 0x1600 /* Java Mode denorm detect Interr -- WTF??*/ | |
| 127 | #define EXC_OFF_RMTE 0x2000 /* Run Mode or Trace Exception */ | |
| 128 | ||
| 02032e8f RJ |
129 | #define _START_OFFSET EXC_OFF_SYS_RESET |
| 130 | ||
| c609719b WD |
131 | #define MAP_A_CONFIG_ADDR_HIGH 0x8000 /* Upper half of CONFIG_ADDR for Map A */ |
| 132 | #define MAP_A_CONFIG_ADDR_LOW 0x0CF8 /* Lower half of CONFIG_ADDR for Map A */ | |
| 133 | #define MAP_A_CONFIG_DATA_HIGH 0x8000 /* Upper half of CONFIG_DAT for Map A */ | |
| 134 | #define MAP_A_CONFIG_DATA_LOW 0x0CFC /* Lower half of CONFIG_DAT for Map A */ | |
| 135 | #define MAP_B_CONFIG_ADDR_HIGH 0xfec0 /* Upper half of CONFIG_ADDR for Map B */ | |
| 136 | #define MAP_B_CONFIG_ADDR_LOW 0x0000 /* Lower half of CONFIG_ADDR for Map B */ | |
| 137 | #define MAP_B_CONFIG_DATA_HIGH 0xfee0 /* Upper half of CONFIG_DAT for Map B */ | |
| 138 | #define MAP_B_CONFIG_DATA_LOW 0x0000 /* Lower half of CONFIG_DAT for Map B */ | |
| 139 | ||
| 140 | ||
| 6d0f6bcf | 141 | #if defined(CONFIG_SYS_ADDR_MAP_A) |
| c609719b WD |
142 | #define CONFIG_ADDR_HIGH MAP_A_CONFIG_ADDR_HIGH /* Upper half of CONFIG_ADDR */ |
| 143 | #define CONFIG_ADDR_LOW MAP_A_CONFIG_ADDR_LOW /* Lower half of CONFIG_ADDR */ | |
| 144 | #define CONFIG_DATA_HIGH MAP_A_CONFIG_DATA_HIGH /* Upper half of CONFIG_DAT */ | |
| 145 | #define CONFIG_DATA_LOW MAP_A_CONFIG_DATA_LOW /* Lower half of CONFIG_DAT */ | |
| 146 | #else /* Assume Map B, default */ | |
| 147 | #define CONFIG_ADDR_HIGH MAP_B_CONFIG_ADDR_HIGH /* Upper half of CONFIG_ADDR */ | |
| 148 | #define CONFIG_ADDR_LOW MAP_B_CONFIG_ADDR_LOW /* Lower half of CONFIG_ADDR */ | |
| 149 | #define CONFIG_DATA_HIGH MAP_B_CONFIG_DATA_HIGH /* Upper half of CONFIG_DAT */ | |
| 150 | #define CONFIG_DATA_LOW MAP_B_CONFIG_DATA_LOW /* Lower half of CONFIG_DAT */ | |
| 151 | #endif | |
| 152 | ||
| 153 | #define CONFIG_ADDR (CONFIG_ADDR_HIGH << 16 | CONFIG_ADDR_LOW) | |
| 154 | ||
| 155 | #define CONFIG_DATA (CONFIG_DATA_HIGH << 16 | CONFIG_DATA_LOW) | |
| 156 | ||
| 157 | /* Macros to write to config registers. addr should be a constant in all cases */ | |
| 158 | ||
| 159 | #define CONFIG_WRITE_BYTE( addr, data ) \ | |
| 160 | __asm__ __volatile__( \ | |
| 161 | " stwbrx %1, 0, %0\n \ | |
| 162 | sync\n \ | |
| 163 | stb %3, %4(%2)\n \ | |
| 164 | sync " \ | |
| 165 | : /* no output */ \ | |
| 166 | : "r" (CONFIG_ADDR), "r" ((addr) & ~3), \ | |
| 167 | "b" (CONFIG_DATA), "r" (data), \ | |
| 168 | "n" ((addr) & 3)); | |
| 169 | ||
| 170 | #define CONFIG_WRITE_HALFWORD( addr, data ) \ | |
| 171 | __asm__ __volatile__( \ | |
| 172 | " stwbrx %1, 0, %0\n \ | |
| 173 | sync\n \ | |
| 174 | sthbrx %3, %4, %2\n \ | |
| 175 | sync " \ | |
| 176 | : /* no output */ \ | |
| 177 | : "r" (CONFIG_ADDR), "r" ((addr) & ~3), \ | |
| 178 | "r" (CONFIG_DATA), "r" (data), \ | |
| 179 | "b" ((addr) & 3)); | |
| 180 | ||
| 181 | /* this assumes it's writeing on word boundaries*/ | |
| 182 | #define CONFIG_WRITE_WORD( addr, data ) \ | |
| 183 | __asm__ __volatile__( \ | |
| 184 | " stwbrx %1, 0, %0\n \ | |
| 185 | sync\n \ | |
| 186 | stwbrx %3, 0, %2\n \ | |
| 187 | sync " \ | |
| 188 | : /* no output */ \ | |
| 189 | : "r" (CONFIG_ADDR), "r" (addr), \ | |
| 190 | "r" (CONFIG_DATA), "r" (data)); | |
| 191 | ||
| 192 | /* Configuration register reads*/ | |
| 193 | ||
| 194 | #define CONFIG_READ_BYTE( addr, reg ) \ | |
| 195 | __asm__ ( \ | |
| 196 | " stwbrx %1, 0, %2\n \ | |
| 197 | sync\n \ | |
| 198 | lbz %0, %4(%3)\n \ | |
| 199 | sync " \ | |
| 200 | : "=r" (reg) \ | |
| 201 | : "r" ((addr) & ~3), "r" (CONFIG_ADDR), \ | |
| 202 | "b" (CONFIG_DATA), "n" ((addr) & 3)); | |
| 203 | ||
| 204 | ||
| 205 | #define CONFIG_READ_HALFWORD( addr, reg ) \ | |
| 206 | __asm__ ( \ | |
| 207 | " stwbrx %1, 0, %2\n \ | |
| 208 | sync\n \ | |
| 209 | lhbrx %0, %4, %3\n \ | |
| 210 | sync " \ | |
| 211 | : "=r" (reg) \ | |
| 212 | : "r" ((addr) & ~3), "r" (CONFIG_ADDR), \ | |
| 213 | "r" (CONFIG_DATA), \ | |
| 214 | "b" ((addr) & 3)); | |
| 215 | ||
| 216 | /* this assumes it's reading on word boundaries*/ | |
| 217 | #define CONFIG_READ_WORD( addr, reg ) \ | |
| 218 | __asm__ ( \ | |
| 219 | " stwbrx %1, 0, %2\n \ | |
| 220 | sync\n \ | |
| 221 | lwbrx %0, 0, %3\n \ | |
| 222 | sync " \ | |
| 223 | : "=r" (reg) \ | |
| 224 | : "r" (addr), "r" (CONFIG_ADDR),\ | |
| 225 | "r" (CONFIG_DATA)); | |
| 226 | ||
| 227 | /* | |
| 228 | * configuration register 'addresses'. | |
| 229 | * These are described in chaper 5 of the 8240 users manual. | |
| 230 | * Where the register has an abreviation in the manual, this has | |
| 231 | * been usaed here, otherwise a name in keeping with the norm has | |
| 232 | * been invented. | |
| 233 | * Note that some of these registers aren't documented in the manual. | |
| 234 | */ | |
| 235 | ||
| 236 | #define PCICR 0x80000004 /* PCI Command Register */ | |
| 237 | #define PCISR 0x80000006 /* PCI Status Register */ | |
| 238 | #define REVID 0x80000008 /* CPU revision id */ | |
| 239 | #define PIR 0x80000009 /* PCI Programming Interface Register */ | |
| 240 | #define PBCCR 0x8000000b /* PCI Base Class Code Register */ | |
| 241 | #define PCLSR 0x8000000c /* Processor Cache Line Size Register */ | |
| 242 | #define PLTR 0x8000000d /* PCI Latancy Timer Register */ | |
| 243 | #define PHTR 0x8000000e /* PCI Header Type Register */ | |
| 244 | #define BISTCTRL 0x8000000f /* BIST Control */ | |
| 16263087 | 245 | #define LMBAR 0x80000010 /* Local Base Address Register */ |
| c609719b WD |
246 | #define PCSRBAR 0x80000014 /* PCSR Base Address Register */ |
| 247 | #define ILR 0x8000003c /* PCI Interrupt Line Register */ | |
| 248 | #define IPR 0x8000003d /* Interrupt Pin Register */ | |
| 249 | #define MINGNT 0x8000003e /* MIN GNI */ | |
| 250 | #define MAXLAT 0x8000003f /* MAX LAT */ | |
| 251 | #define PCIACR 0x80000046 /* PCI Arbiter Control Register */ | |
| 252 | #define PMCR1 0x80000070 /* Power management config. 1 */ | |
| 253 | #define PMCR2 0x80000072 /* Power management config. 2 */ | |
| 254 | #define ODCR 0x80000073 /* Output Driver Control Register */ | |
| 255 | #define CLKDCR 0x80000074 /* CLK Driver Control Register */ | |
| 256 | #if defined(CONFIG_MPC8245) || defined(CONFIG_MPC8241) | |
| 257 | #define MIOCR1 0x80000076 /* Miscellaneous I/O Control Register 1 */ | |
| 258 | #define MIOCR2 0x80000077 /* Miscellaneous I/O Control Register 2 */ | |
| 259 | #endif | |
| 260 | #define EUMBBAR 0x80000078 /* Embedded Utilities Memory Block Base Address Register */ | |
| 261 | #define EUMBBAR_VAL 0x80500000 /* PCI Relocation offset for EUMB region */ | |
| 262 | #define EUMBSIZE 0x00100000 /* Size of EUMB region */ | |
| 263 | ||
| 264 | #define MSAR1 0x80000080 /* Memory Starting Address Register 1 */ | |
| 265 | #define MSAR2 0x80000084 /* Memory Starting Address Register 2 */ | |
| 266 | #define EMSAR1 0x80000088 /* Extended Memory Starting Address Register 1*/ | |
| 267 | #define EMSAR2 0x8000008c /* Extended Memory Starting Address Register 2*/ | |
| 268 | #define MEAR1 0x80000090 /* Memory Ending Address Register 1 */ | |
| 269 | #define MEAR2 0x80000094 /* Memory Ending Address Register 2 */ | |
| 270 | #define EMEAR1 0x80000098 /* Extended Memory Ending Address Register 1 */ | |
| 271 | #define EMEAR2 0x8000009c /* Extended Memory Ending Address Register 2 */ | |
| 272 | #define MBER 0x800000a0 /* Memory bank Enable Register*/ | |
| 273 | #define MPMR 0x800000a3 /* Memory Page Mode Register (stores PGMAX) */ | |
| 274 | #define PICR1 0x800000a8 /* Processor Interface Configuration Register 1 */ | |
| 275 | #define PICR2 0x800000ac /* Processor Interface Configuration Register 2 */ | |
| 276 | #define ECCSBECR 0x800000b8 /* ECC Single-Bit Error Counter Register */ | |
| 277 | #define ECCSBETR 0x800000b8 /* ECC Single-Bit Error Trigger Register */ | |
| 278 | #define ERRENR1 0x800000c0 /* Error Enableing Register 1 */ | |
| 279 | #define ERRENR2 0x800000c4 /* Error Enableing Register 2 */ | |
| 280 | #define ERRDR1 0x800000c1 /* Error Detection Register 1 */ | |
| 281 | #define IPBESR 0x800000c3 /* Internal Processor Error Status Register */ | |
| 282 | #define ERRDR2 0x800000c5 /* Error Detection Register 2 */ | |
| 283 | #define PBESR 0x800000c7 /* PCI Bus Error Status Register */ | |
| 284 | #define PBEAR 0x800000c8 /* Processor/PCI Bus Error Status Register */ | |
| 285 | #define AMBOR 0x800000e0 /* Address Map B Options Register */ | |
| 281e00a3 | 286 | #define PCMBCR 0x800000e1 /* PCI/Memory Buffer Configuration */ |
| c609719b WD |
287 | #define MCCR1 0x800000f0 /* Memory Control Configuration Register 1 */ |
| 288 | #define MCCR2 0x800000f4 /* Memory Control Configuration Register 2 */ | |
| 289 | #define MCCR3 0x800000f8 /* Memory Control Configuration Register 3 */ | |
| 290 | #define MCCR4 0x800000fc /* Memory Control Configuration Register 4 */ | |
| 291 | ||
| 292 | /* some values for some of the above */ | |
| 293 | ||
| 294 | #define PICR1_CF_APARK 0x00000008 | |
| 295 | #define PICR1_LE_MODE 0x00000020 | |
| 296 | #define PICR1_ST_GATH_EN 0x00000040 | |
| 297 | #if defined(CONFIG_MPC8240) | |
| 298 | #define PICR1_EN_PCS 0x00000080 /* according to dink code, sets the 8240 to handle pci config space */ | |
| 299 | #elif defined(CONFIG_MPC8245) || defined(CONFIG_MPC8241) | |
| 300 | #define PICR1_NO_BUSW_CK 0x00000080 /* no bus width check for flash writes */ | |
| 301 | #define PICR1_DEC 0x00000100 /* Time Base enable on 8245/8241 */ | |
| 302 | #define ERCR1 0x800000d0 /* Extended ROM Configuration Register 1 */ | |
| 303 | #define ERCR2 0x800000d4 /* Extended ROM Configuration Register 2 */ | |
| 304 | #define ERCR3 0x800000d8 /* Extended ROM Configuration Register 3 */ | |
| 305 | #define ERCR4 0x800000dc /* Extended ROM Configuration Register 4 */ | |
| 306 | #define MIOCR1 0x80000076 /* Miscellaneous I/O Control Register 1 */ | |
| 307 | #define MIOCR1_ADR_X 0x80000074 /* Miscellaneous I/O Control Register 1 */ | |
| 308 | #define MIOCR1_SHIFT 2 | |
| 309 | #define MIOCR2 0x80000077 /* Miscellaneous I/O Control Register 2 */ | |
| 310 | #define MIOCR2_ADR_X 0x80000074 /* Miscellaneous I/O Control Register 1 */ | |
| 311 | #define MIOCR2_SHIFT 3 | |
| 312 | #define ODCR_ADR_X 0x80000070 /* Output Driver Control register */ | |
| 313 | #define ODCR_SHIFT 3 | |
| 314 | #define PMCR2_ADR 0x80000072 /* Power Mgmnt Cfg 2 register */ | |
| 315 | #define PMCR2_ADR_X 0x80000070 | |
| 316 | #define PMCR2_SHIFT 3 | |
| 317 | #define PMCR1_ADR 0x80000070 /* Power Mgmnt Cfg 1 reister */ | |
| 318 | #else | |
| 319 | #error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240) | |
| 320 | #endif | |
| 321 | #define PICR1_CF_DPARK 0x00000200 | |
| 322 | #define PICR1_MCP_EN 0x00000800 | |
| 323 | #define PICR1_FLASH_WR_EN 0x00001000 | |
| 324 | #ifdef CONFIG_MPC8240 | |
| 325 | #define PICR1_ADDRESS_MAP 0x00010000 | |
| 326 | #define PIRC1_MSK 0xff000000 | |
| 327 | #endif | |
| 328 | #define PICR1_PROC_TYPE_MSK 0x00060000 | |
| 329 | #define PICR1_PROC_TYPE_603E 0x00040000 | |
| 330 | #define PICR1_RCS0 0x00100000 | |
| 331 | ||
| 332 | #define PICR2_CF_SNOOP_WS_MASK 0x000c0000 | |
| 333 | #define PICR2_CF_SNOOP_WS_0WS 0x00000000 | |
| 334 | #define PICR2_CF_SNOOP_WS_1WS 0x00040000 | |
| 335 | #define PICR2_CF_SNOOP_WS_2WS 0x00080000 | |
| 336 | #define PICR2_CF_SNOOP_WS_3WS 0x000c0000 | |
| 337 | #define PICR2_CF_APHASE_WS_MASK 0x0000000c | |
| 338 | #define PICR2_CF_APHASE_WS_0WS 0x00000000 | |
| 339 | #define PICR2_CF_APHASE_WS_1WS 0x00000004 | |
| 340 | #define PICR2_CF_APHASE_WS_2WS 0x00000008 | |
| 341 | #define PICR2_CF_APHASE_WS_3WS 0x0000000c | |
| 342 | ||
| 343 | #define MCCR1_ROMNAL_SHIFT 28 | |
| 344 | #define MCCR1_ROMNAL_MSK 0xf0000000 | |
| 345 | #define MCCR1_ROMFAL_SHIFT 23 | |
| 346 | #define MCCR1_ROMFAL_MSK 0x0f800000 | |
| 347 | #define MCCR1_DBUS_SIZE0 0x00400000 | |
| 348 | #define MCCR1_BURST 0x00100000 | |
| 349 | #define MCCR1_MEMGO 0x00080000 | |
| 350 | #define MCCR1_SREN 0x00040000 | |
| 351 | #if defined(CONFIG_MPC8240) | |
| 352 | #define MCCR1_RAM_TYPE 0x00020000 | |
| 353 | #elif defined(CONFIG_MPC8245) || defined(CONFIG_MPC8241) | |
| 354 | #define MCCR1_SDRAM_EN 0x00020000 | |
| 355 | #else | |
| 356 | #error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240) | |
| 357 | #endif | |
| 358 | #define MCCR1_PCKEN 0x00010000 | |
| 359 | #define MCCR1_BANK1ROW_SHIFT 2 | |
| 360 | #define MCCR1_BANK2ROW_SHIFT 4 | |
| 361 | #define MCCR1_BANK3ROW_SHIFT 6 | |
| 362 | #define MCCR1_BANK4ROW_SHIFT 8 | |
| 363 | #define MCCR1_BANK5ROW_SHIFT 10 | |
| 364 | #define MCCR1_BANK6ROW_SHIFT 12 | |
| 365 | #define MCCR1_BANK7ROW_SHIFT 14 | |
| 366 | ||
| 367 | #define MCCR2_TS_WAIT_TIMER_MSK 0xe0000000 | |
| 368 | #define MCCR2_TS_WAIT_TIMER_SHIFT 29 | |
| 369 | #define MCCR2_ASRISE_MSK 0x1e000000 | |
| 370 | #define MCCR2_ASRISE_SHIFT 25 | |
| 371 | #define MCCR2_ASFALL_MSK 0x01e00000 | |
| 372 | #define MCCR2_ASFALL_SHIFT 21 | |
| 373 | ||
| 374 | #define MCCR2_INLINE_PAR_NOT_ECC 0x00100000 | |
| 375 | #define MCCR2_WRITE_PARITY_CHK 0x00080000 | |
| 376 | #define MCCR2_INLFRD_PARECC_CHK_EN 0x00040000 | |
| 377 | #ifdef CONFIG_MPC8240 | |
| 378 | #define MCCR2_ECC_EN 0x00020000 | |
| 379 | #define MCCR2_EDO 0x00010000 | |
| 380 | #endif | |
| 381 | #define MCCR2_REFINT_MSK 0x0000fffc | |
| 382 | #define MCCR2_REFINT_SHIFT 2 | |
| 383 | #define MCCR2_RSV_PG 0x00000002 | |
| 384 | #define MCCR2_PMW_PAR 0x00000001 | |
| 385 | ||
| 386 | #define MCCR3_BSTOPRE2TO5_MSK 0xf0000000 /*BSTOPRE[2-5]*/ | |
| 387 | #define MCCR3_BSTOPRE2TO5_SHIFT 28 | |
| 388 | #define MCCR3_REFREC_MSK 0x0f000000 | |
| 389 | #define MCCR3_REFREC_SHIFT 24 | |
| 390 | #ifdef CONFIG_MPC8240 | |
| 391 | #define MCCR3_RDLAT_MSK 0x00f00000 | |
| 392 | #define MCCR3_RDLAT_SHIFT 20 | |
| 393 | #define MCCR3_CPX 0x00010000 | |
| 394 | #define MCCR3_RAS6P_MSK 0x00078000 | |
| 395 | #define MCCR3_RAS6P_SHIFT 15 | |
| 396 | #define MCCR3_CAS5_MSK 0x00007000 | |
| 397 | #define MCCR3_CAS5_SHIFT 12 | |
| 398 | #define MCCR3_CP4_MSK 0x00000e00 | |
| 399 | #define MCCR3_CP4_SHIFT 9 | |
| 400 | #define MCCR3_CAS3_MSK 0x000001c0 | |
| 401 | #define MCCR3_CAS3_SHIFT 6 | |
| 402 | #define MCCR3_RCD2_MSK 0x00000038 | |
| 403 | #define MCCR3_RCD2_SHIFT 3 | |
| 404 | #define MCCR3_RP1_MSK 0x00000007 | |
| 405 | #define MCCR3_RP1_SHIFT 0 | |
| 406 | #endif | |
| 407 | ||
| 408 | #define MCCR4_PRETOACT_MSK 0xf0000000 | |
| 409 | #define MCCR4_PRETOACT_SHIFT 28 | |
| 410 | #define MCCR4_ACTTOPRE_MSK 0x0f000000 | |
| 411 | #define MCCR4_ACTTOPRE_SHIFT 24 | |
| 412 | #define MCCR4_WMODE 0x00800000 | |
| 413 | #define MCCR4_INLINE 0x00400000 | |
| 414 | #if defined(CONFIG_MPC8240) | |
| 415 | #define MCCR4_BIT21 0x00200000 /* this include cos DINK code sets it- unknown function*/ | |
| 416 | #elif defined(CONFIG_MPC8245) || defined(CONFIG_MPC8241) | |
| 417 | #define MCCR4_EXTROM 0x00200000 /* enables Extended ROM space */ | |
| 418 | #else | |
| 419 | #error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240) | |
| 420 | #endif | |
| 421 | #define MCCR4_REGISTERED 0x00100000 | |
| 422 | #define MCCR4_BSTOPRE0TO1_MSK 0x000c0000 /*BSTOPRE[0-1]*/ | |
| 423 | #define MCCR4_BSTOPRE0TO1_SHIFT 18 | |
| 424 | #define MCCR4_REGDIMM 0x00008000 | |
| 425 | #define MCCR4_SDMODE_MSK 0x00007f00 | |
| 426 | #define MCCR4_SDMODE_SHIFT 8 | |
| 427 | #define MCCR4_ACTTORW_MSK 0x000000f0 | |
| 428 | #define MCCR4_ACTTORW_SHIFT 4 | |
| 429 | #define MCCR4_BSTOPRE6TO9_MSK 0x0000000f /*BSTOPRE[6-9]*/ | |
| 430 | #define MCCR4_BSTOPRE6TO9_SHIFT 0 | |
| 431 | #define MCCR4_DBUS_SIZE2_SHIFT 17 | |
| 432 | ||
| 433 | #define MICR_ADDR_MASK 0x0ff00000 | |
| 434 | #define MICR_ADDR_SHIFT 20 | |
| 435 | #define MICR_EADDR_MASK 0x30000000 | |
| 436 | #define MICR_EADDR_SHIFT 28 | |
| 437 | ||
| c609719b WD |
438 | /*eumb and epic config*/ |
| 439 | ||
| 440 | #define EPIC_FPR 0x00041000 | |
| 441 | #define EPIC_GCR 0x00041020 | |
| 442 | #define EPIC_EICR 0x00041030 | |
| 443 | #define EPIC_EVI 0x00041080 | |
| 444 | #define EPIC_PI 0x00041090 | |
| 445 | #define EPIC_SVR 0x000410E0 | |
| 446 | #define EPIC_TFRR 0x000410F0 | |
| 447 | ||
| 448 | /* | |
| 449 | * Note the information for these is rather mangled in the 8240 manual. | |
| 450 | * These are guesses. | |
| 451 | */ | |
| 452 | ||
| 453 | #define EPIC_GTCCR0 0x00041100 | |
| 454 | #define EPIC_GTCCR1 0x00041140 | |
| 455 | #define EPIC_GTCCR2 0x00041180 | |
| 456 | #define EPIC_GTCCR3 0x000411C0 | |
| 457 | #define EPIC_GTBCR0 0x00041110 | |
| 458 | #define EPIC_GTBCR1 0x00041150 | |
| 459 | #define EPIC_GTBCR2 0x00041190 | |
| 460 | #define EPIC_GTBCR3 0x000411D0 | |
| 461 | #define EPIC_GTVPR0 0x00041120 | |
| 462 | #define EPIC_GTVPR1 0x00041160 | |
| 463 | #define EPIC_GTVPR2 0x000411a0 | |
| 464 | #define EPIC_GTVPR3 0x000411e0 | |
| 465 | #define EPIC_GTDR0 0x00041130 | |
| 466 | #define EPIC_GTDR1 0x00041170 | |
| 467 | #define EPIC_GTDR2 0x000411b0 | |
| 468 | #define EPIC_GTDR3 0x000411f0 | |
| 469 | ||
| 470 | #define EPIC_IVPR0 0x00050200 | |
| 471 | #define EPIC_IVPR1 0x00050220 | |
| 472 | #define EPIC_IVPR2 0x00050240 | |
| 473 | #define EPIC_IVPR3 0x00050260 | |
| 474 | #define EPIC_IVPR4 0x00050280 | |
| 475 | ||
| 476 | #define EPIC_SVPR0 0x00050200 | |
| 477 | #define EPIC_SVPR1 0x00050220 | |
| 478 | #define EPIC_SVPR2 0x00050240 | |
| 479 | #define EPIC_SVPR3 0x00050260 | |
| 480 | #define EPIC_SVPR4 0x00050280 | |
| 481 | #define EPIC_SVPR5 0x000502A0 | |
| 482 | #define EPIC_SVPR6 0x000502C0 | |
| 483 | #define EPIC_SVPR7 0x000502E0 | |
| 484 | #define EPIC_SVPR8 0x00050300 | |
| 485 | #define EPIC_SVPR9 0x00050320 | |
| 486 | #define EPIC_SVPRa 0x00050340 | |
| 487 | #define EPIC_SVPRb 0x00050360 | |
| 488 | #define EPIC_SVPRc 0x00050380 | |
| 489 | #define EPIC_SVPRd 0x000503A0 | |
| 490 | #define EPIC_SVPRe 0x000503C0 | |
| 491 | #define EPIC_SVPRf 0x000503E0 | |
| 492 | ||
| 493 | /* MPC8240 Byte Swap/PCI Support Macros */ | |
| 494 | #define BYTE_SWAP_16_BIT(x) ( (((x) & 0x00ff) << 8) | ( (x) >> 8) ) | |
| 495 | #define LONGSWAP(x) ((((x) & 0x000000ff) << 24) | (((x) & 0x0000ff00) << 8)|\ | |
| 496 | (((x) & 0x00ff0000) >> 8) | (((x) & 0xff000000) >> 24) ) | |
| 497 | #define PCISWAP(x) LONGSWAP(x) | |
| 498 | ||
| 499 | #ifndef __ASSEMBLY__ | |
| 500 | ||
| 501 | /* | |
| 502 | * MPC107 Support | |
| 503 | * | |
| 504 | */ | |
| 505 | unsigned int mpc824x_mpc107_getreg(unsigned int regNum); | |
| 506 | void mpc824x_mpc107_setreg(unsigned int regNum, unsigned int regVal); | |
| 507 | void mpc824x_mpc107_write8(unsigned int address, unsigned char data); | |
| 508 | void mpc824x_mpc107_write16(unsigned int address, unsigned short data); | |
| 509 | void mpc824x_mpc107_write32(unsigned int address, unsigned int data); | |
| 510 | unsigned char mpc824x_mpc107_read8(unsigned int address); | |
| 511 | unsigned short mpc824x_mpc107_read16(unsigned int address); | |
| 512 | unsigned int mpc824x_mpc107_read32(unsigned int address); | |
| 513 | unsigned int mpc824x_eummbar_read(unsigned int regNum); | |
| 514 | void mpc824x_eummbar_write(unsigned int regNum, unsigned int regVal); | |
| 515 | ||
| 516 | #ifdef CONFIG_PCI | |
| 517 | struct pci_controller; | |
| 518 | void pci_cpm824x_init(struct pci_controller* hose); | |
| 519 | #endif | |
| 520 | ||
| 521 | #endif /* __ASSEMBLY__ */ | |
| 522 | ||
| 523 | #endif /* __MPC824X_H__ */ |