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fa36ae79 SR |
1 | /* |
2 | * (C) Copyright 2009 | |
3 | * Stefan Roese, DENX Software Engineering, sr@denx.de. | |
4 | * | |
1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
fa36ae79 SR |
6 | */ |
7 | ||
8 | #ifndef __CFI_FLASH_H__ | |
9 | #define __CFI_FLASH_H__ | |
10 | ||
11 | #define FLASH_CMD_CFI 0x98 | |
12 | #define FLASH_CMD_READ_ID 0x90 | |
13 | #define FLASH_CMD_RESET 0xff | |
14 | #define FLASH_CMD_BLOCK_ERASE 0x20 | |
15 | #define FLASH_CMD_ERASE_CONFIRM 0xD0 | |
16 | #define FLASH_CMD_WRITE 0x40 | |
17 | #define FLASH_CMD_PROTECT 0x60 | |
6f726f95 SR |
18 | #define FLASH_CMD_SETUP 0x60 |
19 | #define FLASH_CMD_SET_CR_CONFIRM 0x03 | |
fa36ae79 SR |
20 | #define FLASH_CMD_PROTECT_SET 0x01 |
21 | #define FLASH_CMD_PROTECT_CLEAR 0xD0 | |
22 | #define FLASH_CMD_CLEAR_STATUS 0x50 | |
23 | #define FLASH_CMD_READ_STATUS 0x70 | |
24 | #define FLASH_CMD_WRITE_TO_BUFFER 0xE8 | |
25 | #define FLASH_CMD_WRITE_BUFFER_PROG 0xE9 | |
26 | #define FLASH_CMD_WRITE_BUFFER_CONFIRM 0xD0 | |
27 | ||
28 | #define FLASH_STATUS_DONE 0x80 | |
29 | #define FLASH_STATUS_ESS 0x40 | |
30 | #define FLASH_STATUS_ECLBS 0x20 | |
31 | #define FLASH_STATUS_PSLBS 0x10 | |
32 | #define FLASH_STATUS_VPENS 0x08 | |
33 | #define FLASH_STATUS_PSS 0x04 | |
34 | #define FLASH_STATUS_DPS 0x02 | |
35 | #define FLASH_STATUS_R 0x01 | |
36 | #define FLASH_STATUS_PROTECT 0x01 | |
37 | ||
38 | #define AMD_CMD_RESET 0xF0 | |
39 | #define AMD_CMD_WRITE 0xA0 | |
40 | #define AMD_CMD_ERASE_START 0x80 | |
41 | #define AMD_CMD_ERASE_SECTOR 0x30 | |
42 | #define AMD_CMD_UNLOCK_START 0xAA | |
43 | #define AMD_CMD_UNLOCK_ACK 0x55 | |
44 | #define AMD_CMD_WRITE_TO_BUFFER 0x25 | |
45 | #define AMD_CMD_WRITE_BUFFER_CONFIRM 0x29 | |
66863b05 AG |
46 | #define AMD_CMD_SET_PPB_ENTRY 0xC0 |
47 | #define AMD_CMD_SET_PPB_EXIT_BC1 0x90 | |
48 | #define AMD_CMD_SET_PPB_EXIT_BC2 0x00 | |
49 | #define AMD_CMD_PPB_UNLOCK_BC1 0x80 | |
50 | #define AMD_CMD_PPB_UNLOCK_BC2 0x30 | |
51 | #define AMD_CMD_PPB_LOCK_BC1 0xA0 | |
52 | #define AMD_CMD_PPB_LOCK_BC2 0x00 | |
fa36ae79 SR |
53 | |
54 | #define AMD_STATUS_TOGGLE 0x40 | |
55 | #define AMD_STATUS_ERROR 0x20 | |
56 | ||
57 | #define ATM_CMD_UNLOCK_SECT 0x70 | |
58 | #define ATM_CMD_SOFTLOCK_START 0x80 | |
59 | #define ATM_CMD_LOCK_SECT 0x40 | |
60 | ||
61 | #define FLASH_CONTINUATION_CODE 0x7F | |
62 | ||
63 | #define FLASH_OFFSET_MANUFACTURER_ID 0x00 | |
e303be2d | 64 | #define FLASH_OFFSET_DEVICE_ID 0x01 |
72443c7f | 65 | #define FLASH_OFFSET_LOWER_SW_BITS 0x0C |
e303be2d SR |
66 | #define FLASH_OFFSET_DEVICE_ID2 0x0E |
67 | #define FLASH_OFFSET_DEVICE_ID3 0x0F | |
68 | #define FLASH_OFFSET_CFI 0x55 | |
fa36ae79 | 69 | #define FLASH_OFFSET_CFI_ALT 0x555 |
e303be2d SR |
70 | #define FLASH_OFFSET_CFI_RESP 0x10 |
71 | #define FLASH_OFFSET_PRIMARY_VENDOR 0x13 | |
fa36ae79 | 72 | /* extended query table primary address */ |
e303be2d | 73 | #define FLASH_OFFSET_EXT_QUERY_T_P_ADDR 0x15 |
fa36ae79 | 74 | #define FLASH_OFFSET_WTOUT 0x1F |
e303be2d SR |
75 | #define FLASH_OFFSET_WBTOUT 0x20 |
76 | #define FLASH_OFFSET_ETOUT 0x21 | |
77 | #define FLASH_OFFSET_CETOUT 0x22 | |
78 | #define FLASH_OFFSET_WMAX_TOUT 0x23 | |
79 | #define FLASH_OFFSET_WBMAX_TOUT 0x24 | |
80 | #define FLASH_OFFSET_EMAX_TOUT 0x25 | |
81 | #define FLASH_OFFSET_CEMAX_TOUT 0x26 | |
82 | #define FLASH_OFFSET_SIZE 0x27 | |
83 | #define FLASH_OFFSET_INTERFACE 0x28 | |
84 | #define FLASH_OFFSET_BUFFER_SIZE 0x2A | |
85 | #define FLASH_OFFSET_NUM_ERASE_REGIONS 0x2C | |
86 | #define FLASH_OFFSET_ERASE_REGIONS 0x2D | |
87 | #define FLASH_OFFSET_PROTECT 0x02 | |
fa36ae79 SR |
88 | #define FLASH_OFFSET_USER_PROTECTION 0x85 |
89 | #define FLASH_OFFSET_INTEL_PROTECTION 0x81 | |
90 | ||
91 | #define CFI_CMDSET_NONE 0 | |
92 | #define CFI_CMDSET_INTEL_EXTENDED 1 | |
93 | #define CFI_CMDSET_AMD_STANDARD 2 | |
94 | #define CFI_CMDSET_INTEL_STANDARD 3 | |
95 | #define CFI_CMDSET_AMD_EXTENDED 4 | |
96 | #define CFI_CMDSET_MITSU_STANDARD 256 | |
97 | #define CFI_CMDSET_MITSU_EXTENDED 257 | |
98 | #define CFI_CMDSET_SST 258 | |
99 | #define CFI_CMDSET_INTEL_PROG_REGIONS 512 | |
100 | ||
101 | #ifdef CONFIG_SYS_FLASH_CFI_AMD_RESET /* needed for STM_ID_29W320DB on UC100 */ | |
102 | # undef FLASH_CMD_RESET | |
103 | # define FLASH_CMD_RESET AMD_CMD_RESET /* use AMD-Reset instead */ | |
104 | #endif | |
105 | ||
106 | #define NUM_ERASE_REGIONS 4 /* max. number of erase regions */ | |
107 | ||
108 | typedef union { | |
622b9527 RH |
109 | u8 w8; |
110 | u16 w16; | |
111 | u32 w32; | |
112 | u64 w64; | |
fa36ae79 SR |
113 | } cfiword_t; |
114 | ||
115 | /* CFI standard query structure */ | |
aedadf10 AG |
116 | /* The offsets and sizes of this packed structure members correspond |
117 | * to the actual layout in CFI Flash chips. Some 16- and 32-bit members | |
118 | * are unaligned and must be accessed with explicit unaligned access macros. | |
119 | */ | |
fa36ae79 SR |
120 | struct cfi_qry { |
121 | u8 qry[3]; | |
aedadf10 AG |
122 | u16 p_id; /* unaligned */ |
123 | u16 p_adr; /* unaligned */ | |
124 | u16 a_id; /* unaligned */ | |
125 | u16 a_adr; /* unaligned */ | |
fa36ae79 SR |
126 | u8 vcc_min; |
127 | u8 vcc_max; | |
128 | u8 vpp_min; | |
129 | u8 vpp_max; | |
130 | u8 word_write_timeout_typ; | |
131 | u8 buf_write_timeout_typ; | |
132 | u8 block_erase_timeout_typ; | |
133 | u8 chip_erase_timeout_typ; | |
134 | u8 word_write_timeout_max; | |
135 | u8 buf_write_timeout_max; | |
136 | u8 block_erase_timeout_max; | |
137 | u8 chip_erase_timeout_max; | |
138 | u8 dev_size; | |
aedadf10 AG |
139 | u16 interface_desc; /* aligned */ |
140 | u16 max_buf_write_size; /* aligned */ | |
fa36ae79 | 141 | u8 num_erase_regions; |
aedadf10 | 142 | u32 erase_region_info[NUM_ERASE_REGIONS]; /* unaligned */ |
fa36ae79 SR |
143 | } __attribute__((packed)); |
144 | ||
145 | struct cfi_pri_hdr { | |
146 | u8 pri[3]; | |
147 | u8 major_version; | |
148 | u8 minor_version; | |
149 | } __attribute__((packed)); | |
150 | ||
ca5def3f SR |
151 | #ifndef CONFIG_SYS_FLASH_BANKS_LIST |
152 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } | |
153 | #endif | |
154 | ||
155 | /* | |
156 | * CFI_MAX_FLASH_BANKS only used for flash_info struct declaration. | |
157 | * | |
158 | * Use CONFIG_SYS_MAX_FLASH_BANKS_DETECT if defined | |
159 | */ | |
160 | #if defined(CONFIG_SYS_MAX_FLASH_BANKS_DETECT) | |
161 | #define CONFIG_SYS_MAX_FLASH_BANKS (cfi_flash_num_flash_banks) | |
162 | #define CFI_MAX_FLASH_BANKS CONFIG_SYS_MAX_FLASH_BANKS_DETECT | |
163 | /* board code can update this variable before CFI detection */ | |
164 | extern int cfi_flash_num_flash_banks; | |
165 | #else | |
166 | #define CFI_MAX_FLASH_BANKS CONFIG_SYS_MAX_FLASH_BANKS | |
167 | #endif | |
168 | ||
6a19cc9d MY |
169 | phys_addr_t cfi_flash_bank_addr(int i); |
170 | unsigned long cfi_flash_bank_size(int i); | |
171 | void flash_cmd_reset(flash_info_t *info); | |
172 | ||
173 | #ifdef CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS | |
174 | void flash_write8(u8 value, void *addr); | |
175 | void flash_write16(u16 value, void *addr); | |
176 | void flash_write32(u32 value, void *addr); | |
177 | void flash_write64(u64 value, void *addr); | |
178 | u8 flash_read8(void *addr); | |
179 | u16 flash_read16(void *addr); | |
180 | u32 flash_read32(void *addr); | |
181 | u64 flash_read64(void *addr); | |
182 | #endif | |
fa36ae79 SR |
183 | |
184 | #endif /* __CFI_FLASH_H__ */ |