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1/*
2 * (C) Copyright 2008
3 * Benjamin Warren, biggerbadderben@gmail.com
4 *
1a459660 5 * SPDX-License-Identifier: GPL-2.0+
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6 */
7
8/*
9 * netdev.h - definitions an prototypes for network devices
10 */
11
12#ifndef _NETDEV_H_
13#define _NETDEV_H_
14
15/*
16 * Board and CPU-specific initialization functions
17 * board_eth_init() has highest priority. cpu_eth_init() only
18 * gets called if board_eth_init() isn't instantiated or fails.
19 * Return values:
20 * 0: success
21 * -1: failure
22 */
23
24int board_eth_init(bd_t *bis);
25int cpu_eth_init(bd_t *bis);
26
27/* Driver initialization prototypes */
c041e9d2 28int at91emac_register(bd_t *bis, unsigned long iobase);
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29int au1x00_enet_initialize(bd_t*);
30int ax88180_initialize(bd_t *bis);
799e125c 31int bcm_sf2_eth_register(bd_t *bis, u8 dev_num);
89973f8a 32int bfin_EMAC_initialize(bd_t *bis);
efdd7319 33int calxedaxgmac_initialize(u32 id, ulong base_addr);
b1c0eaac 34int cs8900_initialize(u8 dev_num, int base_addr);
8453587e 35int davinci_emac_initialize(void);
bd6ce9d1 36int dc21x4x_initialize(bd_t *bis);
92a190aa 37int designware_initialize(ulong base_addr, u32 interface);
bd6ce9d1 38int dm9000_initialize(bd_t *bis);
62cbc408 39int dnet_eth_initialize(int id, void *regs, unsigned int phy_addr);
ad3381cf 40int e1000_initialize(bd_t *bis);
10efa024 41int eepro100_initialize(bd_t *bis);
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42int enc28j60_initialize(unsigned int bus, unsigned int cs,
43 unsigned int max_hz, unsigned int mode);
594d57d0 44int ep93xx_eth_initialize(u8 dev_num, int base_addr);
164846ee 45int eth_3com_initialize (bd_t * bis);
bd6ce9d1 46int ethoc_initialize(u8 dev_num, int base_addr);
3456a148 47int fec_initialize (bd_t *bis);
bd6ce9d1 48int fecmxc_initialize(bd_t *bis);
9e27e9dc 49int fecmxc_initialize_multi(bd_t *bis, int dev_id, int phy_id, uint32_t addr);
b3dbf4a5 50int ftgmac100_initialize(bd_t *bits);
750326e5 51int ftmac100_initialize(bd_t *bits);
c4775476 52int ftmac110_initialize(bd_t *bits);
89973f8a 53int greth_initialize(bd_t *bis);
6aca145e 54void gt6426x_eth_initialize(bd_t *bis);
45a1693a 55int ks8851_mll_initialize(u8 dev_num, int base_addr);
b7ad4109 56int lan91c96_initialize(u8 dev_num, int base_addr);
ac2916a2 57int lpc32xx_eth_initialize(bd_t *bis);
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58int macb_eth_initialize(int id, void *regs, unsigned int phy_addr);
59int mcdmafec_initialize(bd_t *bis);
60int mcffec_initialize(bd_t *bis);
a0aad08f 61int mpc512x_fec_initialize(bd_t *bis);
e1d7480b 62int mpc5xxx_fec_initialize(bd_t *bis);
ba705b5b 63int mpc82xx_scc_enet_initialize(bd_t *bis);
d44265ad 64int mvgbe_initialize(bd_t *bis);
19fc2eae 65int mvneta_initialize(bd_t *bis, int base_addr, int devnum, int phy_addr);
b902b8dd 66int natsemi_initialize(bd_t *bis);
d0201692 67int ne2k_register(void);
cc94074e 68int npe_initialize(bd_t *bis);
19403633 69int ns8382x_initialize(bd_t *bis);
e3090534 70int pcnet_initialize(bd_t *bis);
25a85906 71int ppc_4xx_eth_initialize (bd_t *bis);
0b252f50 72int rtl8139_initialize(bd_t *bis);
02d69891 73int rtl8169_initialize(bd_t *bis);
9eb79bd8 74int scc_initialize(bd_t *bis);
bd6ce9d1 75int sh_eth_initialize(bd_t *bis);
89973f8a 76int skge_initialize(bd_t *bis);
7194ab80 77int smc91111_initialize(u8 dev_num, int base_addr);
bd6ce9d1 78int smc911x_initialize(u8 dev_num, int base_addr);
ccdd12f8 79int tsi108_eth_initialize(bd_t *bis);
2b5243fc 80int uec_standard_init(bd_t *bis);
89973f8a 81int uli526x_initialize(bd_t *bis);
79788bb1 82int armada100_fec_register(unsigned long base_addr);
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83int xilinx_axiemac_initialize(bd_t *bis, unsigned long base_addr,
84 unsigned long dma_addr);
0c9c99a2 85int xilinx_emaclite_of_init(const void *blob);
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86int xilinx_emaclite_initialize(bd_t *bis, unsigned long base_addr,
87 int txpp, int rxpp);
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88int xilinx_ll_temac_eth_init(bd_t *bis, unsigned long base_addr, int flags,
89 unsigned long ctrl_addr);
f88a6869 90int zynq_gem_of_init(const void *blob);
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91int zynq_gem_initialize(bd_t *bis, phys_addr_t base_addr,
92 int phy_addr, u32 emio);
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93/*
94 * As long as the Xilinx xps_ll_temac ethernet driver has not its own interface
95 * exported by a public hader file, we need a global definition at this point.
96 */
97#if defined(CONFIG_XILINX_LL_TEMAC)
98#define XILINX_LL_TEMAC_M_FIFO 0 /* use FIFO Ctrl */
99#define XILINX_LL_TEMAC_M_SDMA_PLB (1 << 0)/* use SDMA Ctrl via PLB */
100#define XILINX_LL_TEMAC_M_SDMA_DCR (1 << 1)/* use SDMA Ctrl via DCR */
101#endif
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102
103/* Boards with PCI network controllers can call this from their board_eth_init()
104 * function to initialize whatever's on board.
105 * Return value is total # of devices found */
106
107static inline int pci_eth_init(bd_t *bis)
108{
109 int num = 0;
e3090534 110
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111#ifdef CONFIG_PCI
112
113#ifdef CONFIG_EEPRO100
114 num += eepro100_initialize(bis);
115#endif
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116#ifdef CONFIG_TULIP
117 num += dc21x4x_initialize(bis);
118#endif
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119#ifdef CONFIG_E1000
120 num += e1000_initialize(bis);
121#endif
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122#ifdef CONFIG_PCNET
123 num += pcnet_initialize(bis);
124#endif
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125#ifdef CONFIG_NATSEMI
126 num += natsemi_initialize(bis);
127#endif
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128#ifdef CONFIG_NS8382X
129 num += ns8382x_initialize(bis);
130#endif
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131#if defined(CONFIG_RTL8139)
132 num += rtl8139_initialize(bis);
133#endif
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134#if defined(CONFIG_RTL8169)
135 num += rtl8169_initialize(bis);
136#endif
b11f664f 137#if defined(CONFIG_ULI526X)
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138 num += uli526x_initialize(bis);
139#endif
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140
141#endif /* CONFIG_PCI */
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142 return num;
143}
144
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145/*
146 * Boards with mv88e61xx switch can use this by defining
147 * CONFIG_MV88E61XX_SWITCH in respective board configheader file
148 * the stuct and enums here are used to specify switch configuration params
149 */
150#if defined(CONFIG_MV88E61XX_SWITCH)
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151
152/* constants for any 88E61xx switch */
153#define MV88E61XX_MAX_PORTS_NUM 6
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154
155enum mv88e61xx_cfg_mdip {
156 MV88E61XX_MDIP_NOCHANGE,
157 MV88E61XX_MDIP_REVERSE
158};
159
160enum mv88e61xx_cfg_ledinit {
161 MV88E61XX_LED_INIT_DIS,
162 MV88E61XX_LED_INIT_EN
163};
164
165enum mv88e61xx_cfg_rgmiid {
166 MV88E61XX_RGMII_DELAY_DIS,
167 MV88E61XX_RGMII_DELAY_EN
168};
169
170enum mv88e61xx_cfg_prtstt {
171 MV88E61XX_PORTSTT_DISABLED,
172 MV88E61XX_PORTSTT_BLOCKING,
173 MV88E61XX_PORTSTT_LEARNING,
174 MV88E61XX_PORTSTT_FORWARDING
175};
176
177struct mv88e61xx_config {
178 char *name;
0a16ea59 179 u8 vlancfg[MV88E61XX_MAX_PORTS_NUM];
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180 enum mv88e61xx_cfg_rgmiid rgmii_delay;
181 enum mv88e61xx_cfg_prtstt portstate;
182 enum mv88e61xx_cfg_ledinit led_init;
183 enum mv88e61xx_cfg_mdip mdip;
184 u32 ports_enabled;
185 u8 cpuport;
186};
187
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188/*
189 * Common mappings for Internal VLANs
190 * These mappings consider that all ports are useable; the driver
191 * will mask inexistent/unused ports.
192 */
193
194/* Switch mode : routes any port to any port */
195#define MV88E61XX_VLANCFG_SWITCH { 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F }
196
197/* Router mode: routes only CPU port 5 to/from non-CPU ports 0-4 */
198#define MV88E61XX_VLANCFG_ROUTER { 0x20, 0x20, 0x20, 0x20, 0x20, 0x1F }
199
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200int mv88e61xx_switch_initialize(struct mv88e61xx_config *swconfig);
201#endif /* CONFIG_MV88E61XX_SWITCH */
202
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203struct mii_dev *fec_get_miibus(uint32_t base_addr, int dev_id);
204#ifdef CONFIG_PHYLIB
205struct phy_device;
206int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr,
207 struct mii_dev *bus, struct phy_device *phydev);
208#else
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209/*
210 * Allow FEC to fine-tune MII configuration on boards which require this.
211 */
212int fecmxc_register_mii_postcall(struct eth_device *dev, int (*cb)(int));
fe428b90 213#endif
2e5f4421 214
89973f8a 215#endif /* _NETDEV_H_ */