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mmc: remove the unnecessary define and fix the wrong bit control
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1/*
2 * (C) Copyright 2008
3 * Benjamin Warren, biggerbadderben@gmail.com
4 *
1a459660 5 * SPDX-License-Identifier: GPL-2.0+
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6 */
7
8/*
9 * netdev.h - definitions an prototypes for network devices
10 */
11
12#ifndef _NETDEV_H_
13#define _NETDEV_H_
14
15/*
16 * Board and CPU-specific initialization functions
17 * board_eth_init() has highest priority. cpu_eth_init() only
18 * gets called if board_eth_init() isn't instantiated or fails.
19 * Return values:
20 * 0: success
21 * -1: failure
22 */
23
24int board_eth_init(bd_t *bis);
25int cpu_eth_init(bd_t *bis);
26
27/* Driver initialization prototypes */
c960b13e 28int altera_tse_initialize(u8 dev_num, int mac_base,
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29 int sgdma_rx_base, int sgdma_tx_base,
30 u32 sgdma_desc_base, u32 sgdma_desc_size);
c041e9d2 31int at91emac_register(bd_t *bis, unsigned long iobase);
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32int au1x00_enet_initialize(bd_t*);
33int ax88180_initialize(bd_t *bis);
89973f8a 34int bfin_EMAC_initialize(bd_t *bis);
efdd7319 35int calxedaxgmac_initialize(u32 id, ulong base_addr);
b1c0eaac 36int cs8900_initialize(u8 dev_num, int base_addr);
8453587e 37int davinci_emac_initialize(void);
bd6ce9d1 38int dc21x4x_initialize(bd_t *bis);
92a190aa 39int designware_initialize(ulong base_addr, u32 interface);
bd6ce9d1 40int dm9000_initialize(bd_t *bis);
62cbc408 41int dnet_eth_initialize(int id, void *regs, unsigned int phy_addr);
ad3381cf 42int e1000_initialize(bd_t *bis);
10efa024 43int eepro100_initialize(bd_t *bis);
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44int enc28j60_initialize(unsigned int bus, unsigned int cs,
45 unsigned int max_hz, unsigned int mode);
594d57d0 46int ep93xx_eth_initialize(u8 dev_num, int base_addr);
164846ee 47int eth_3com_initialize (bd_t * bis);
bd6ce9d1 48int ethoc_initialize(u8 dev_num, int base_addr);
3456a148 49int fec_initialize (bd_t *bis);
bd6ce9d1 50int fecmxc_initialize(bd_t *bis);
9e27e9dc 51int fecmxc_initialize_multi(bd_t *bis, int dev_id, int phy_id, uint32_t addr);
b3dbf4a5 52int ftgmac100_initialize(bd_t *bits);
750326e5 53int ftmac100_initialize(bd_t *bits);
c4775476 54int ftmac110_initialize(bd_t *bits);
89973f8a 55int greth_initialize(bd_t *bis);
6aca145e 56void gt6426x_eth_initialize(bd_t *bis);
bd6ce9d1 57int ks8695_eth_initialize(void);
45a1693a 58int ks8851_mll_initialize(u8 dev_num, int base_addr);
b7ad4109 59int lan91c96_initialize(u8 dev_num, int base_addr);
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60int macb_eth_initialize(int id, void *regs, unsigned int phy_addr);
61int mcdmafec_initialize(bd_t *bis);
62int mcffec_initialize(bd_t *bis);
a0aad08f 63int mpc512x_fec_initialize(bd_t *bis);
e1d7480b 64int mpc5xxx_fec_initialize(bd_t *bis);
ba705b5b 65int mpc82xx_scc_enet_initialize(bd_t *bis);
d44265ad 66int mvgbe_initialize(bd_t *bis);
b902b8dd 67int natsemi_initialize(bd_t *bis);
d0201692 68int ne2k_register(void);
cc94074e 69int npe_initialize(bd_t *bis);
19403633 70int ns8382x_initialize(bd_t *bis);
e3090534 71int pcnet_initialize(bd_t *bis);
4fce2ace 72int plb2800_eth_initialize(bd_t *bis);
25a85906 73int ppc_4xx_eth_initialize (bd_t *bis);
0b252f50 74int rtl8139_initialize(bd_t *bis);
02d69891 75int rtl8169_initialize(bd_t *bis);
9eb79bd8 76int scc_initialize(bd_t *bis);
bd6ce9d1 77int sh_eth_initialize(bd_t *bis);
89973f8a 78int skge_initialize(bd_t *bis);
7194ab80 79int smc91111_initialize(u8 dev_num, int base_addr);
bd6ce9d1 80int smc911x_initialize(u8 dev_num, int base_addr);
518ce472 81int sunxi_wemac_initialize(bd_t *bis);
ccdd12f8 82int tsi108_eth_initialize(bd_t *bis);
2b5243fc 83int uec_standard_init(bd_t *bis);
89973f8a 84int uli526x_initialize(bd_t *bis);
79788bb1 85int armada100_fec_register(unsigned long base_addr);
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86int xilinx_axiemac_initialize(bd_t *bis, unsigned long base_addr,
87 unsigned long dma_addr);
0c9c99a2 88int xilinx_emaclite_of_init(const void *blob);
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89int xilinx_emaclite_initialize(bd_t *bis, unsigned long base_addr,
90 int txpp, int rxpp);
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91int xilinx_ll_temac_eth_init(bd_t *bis, unsigned long base_addr, int flags,
92 unsigned long ctrl_addr);
f88a6869 93int zynq_gem_of_init(const void *blob);
01fbf310 94int zynq_gem_initialize(bd_t *bis, int base_addr, int phy_addr, u32 emio);
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95/*
96 * As long as the Xilinx xps_ll_temac ethernet driver has not its own interface
97 * exported by a public hader file, we need a global definition at this point.
98 */
99#if defined(CONFIG_XILINX_LL_TEMAC)
100#define XILINX_LL_TEMAC_M_FIFO 0 /* use FIFO Ctrl */
101#define XILINX_LL_TEMAC_M_SDMA_PLB (1 << 0)/* use SDMA Ctrl via PLB */
102#define XILINX_LL_TEMAC_M_SDMA_DCR (1 << 1)/* use SDMA Ctrl via DCR */
103#endif
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104
105/* Boards with PCI network controllers can call this from their board_eth_init()
106 * function to initialize whatever's on board.
107 * Return value is total # of devices found */
108
109static inline int pci_eth_init(bd_t *bis)
110{
111 int num = 0;
e3090534 112
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113#ifdef CONFIG_PCI
114
115#ifdef CONFIG_EEPRO100
116 num += eepro100_initialize(bis);
117#endif
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118#ifdef CONFIG_TULIP
119 num += dc21x4x_initialize(bis);
120#endif
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121#ifdef CONFIG_E1000
122 num += e1000_initialize(bis);
123#endif
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124#ifdef CONFIG_PCNET
125 num += pcnet_initialize(bis);
126#endif
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127#ifdef CONFIG_NATSEMI
128 num += natsemi_initialize(bis);
129#endif
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130#ifdef CONFIG_NS8382X
131 num += ns8382x_initialize(bis);
132#endif
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133#if defined(CONFIG_RTL8139)
134 num += rtl8139_initialize(bis);
135#endif
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136#if defined(CONFIG_RTL8169)
137 num += rtl8169_initialize(bis);
138#endif
b11f664f 139#if defined(CONFIG_ULI526X)
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140 num += uli526x_initialize(bis);
141#endif
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142
143#endif /* CONFIG_PCI */
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144 return num;
145}
146
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147/*
148 * Boards with mv88e61xx switch can use this by defining
149 * CONFIG_MV88E61XX_SWITCH in respective board configheader file
150 * the stuct and enums here are used to specify switch configuration params
151 */
152#if defined(CONFIG_MV88E61XX_SWITCH)
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153
154/* constants for any 88E61xx switch */
155#define MV88E61XX_MAX_PORTS_NUM 6
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156
157enum mv88e61xx_cfg_mdip {
158 MV88E61XX_MDIP_NOCHANGE,
159 MV88E61XX_MDIP_REVERSE
160};
161
162enum mv88e61xx_cfg_ledinit {
163 MV88E61XX_LED_INIT_DIS,
164 MV88E61XX_LED_INIT_EN
165};
166
167enum mv88e61xx_cfg_rgmiid {
168 MV88E61XX_RGMII_DELAY_DIS,
169 MV88E61XX_RGMII_DELAY_EN
170};
171
172enum mv88e61xx_cfg_prtstt {
173 MV88E61XX_PORTSTT_DISABLED,
174 MV88E61XX_PORTSTT_BLOCKING,
175 MV88E61XX_PORTSTT_LEARNING,
176 MV88E61XX_PORTSTT_FORWARDING
177};
178
179struct mv88e61xx_config {
180 char *name;
0a16ea59 181 u8 vlancfg[MV88E61XX_MAX_PORTS_NUM];
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182 enum mv88e61xx_cfg_rgmiid rgmii_delay;
183 enum mv88e61xx_cfg_prtstt portstate;
184 enum mv88e61xx_cfg_ledinit led_init;
185 enum mv88e61xx_cfg_mdip mdip;
186 u32 ports_enabled;
187 u8 cpuport;
188};
189
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190/*
191 * Common mappings for Internal VLANs
192 * These mappings consider that all ports are useable; the driver
193 * will mask inexistent/unused ports.
194 */
195
196/* Switch mode : routes any port to any port */
197#define MV88E61XX_VLANCFG_SWITCH { 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F }
198
199/* Router mode: routes only CPU port 5 to/from non-CPU ports 0-4 */
200#define MV88E61XX_VLANCFG_ROUTER { 0x20, 0x20, 0x20, 0x20, 0x20, 0x1F }
201
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202int mv88e61xx_switch_initialize(struct mv88e61xx_config *swconfig);
203#endif /* CONFIG_MV88E61XX_SWITCH */
204
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205struct mii_dev *fec_get_miibus(uint32_t base_addr, int dev_id);
206#ifdef CONFIG_PHYLIB
207struct phy_device;
208int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr,
209 struct mii_dev *bus, struct phy_device *phydev);
210#else
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211/*
212 * Allow FEC to fine-tune MII configuration on boards which require this.
213 */
214int fecmxc_register_mii_postcall(struct eth_device *dev, int (*cb)(int));
fe428b90 215#endif
2e5f4421 216
89973f8a 217#endif /* _NETDEV_H_ */