[people/ms/u-boot.git] / include / ns9750_ser.h

/***********************************************************************
 *
 * Copyright (C) 2004 by FS Forth-Systeme GmbH.
 * All rights reserved.
 *
 * $Id: ns9750_ser.h,v 1.1 2004/02/16 10:37:20 mpietrek Exp $
 * @Author: Markus Pietrek
 * @References: [1] NS9750 Hardware Reference, December 2003
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 *
 ***********************************************************************/

#ifndef FS_NS9750_SER_H
#define FS_NS9750_SER_H

#define NS9750_SER_MODULE_BASE		(0x90200000)

#define get_ser_reg_addr(c) \
	((volatile unsigned int *)(NS9750_SER_MODULE_BASE+(unsigned int) (c)))

#define get_ser_reg_addr_channel(reg,chan) \
	get_ser_reg_addr((reg)+(((chan)<2)?0:0x00100000)+(((chan)&1)?0x40:0))

/* the register addresses */

#define NS9750_SER_CTRL_A		(0x00)
#define NS9750_SER_CTRL_B		(0x04)
#define NS9750_SER_STAT_A		(0x08)
#define NS9750_SER_BITRATE		(0x0C)
#define NS9750_SER_FIFO			(0x10)
#define NS9750_SER_RX_BUF_TIMER		(0x14)
#define NS9750_SER_RX_CHAR_TIMER	(0x18)
#define NS9750_SER_RX_MATCH		(0x1C)
#define NS9750_SER_RX_MATCH_MASK	(0x20)
#define NS9750_SER_FLOW_CTRL		(0x34)
#define NS9750_SER_FLOW_CTRL_FORCE	(0x38)

/* register bit fields */

/* control A register */

#define NS9750_SER_CTRL_A_CE		(0x80000000)
#define NS9750_SER_CTRL_A_BRK		(0x40000000)
#define NS9750_SER_CTRL_A_STICKP	(0x20000000)
#define NS9750_SER_CTRL_A_EPS		(0x10000000)
#define NS9750_SER_CTRL_A_PE		(0x08000000)
#define NS9750_SER_CTRL_A_STOP		(0x04000000)
#define NS9750_SER_CTRL_A_WLS_MA	(0x03000000)
#define NS9750_SER_CTRL_A_WLS_5		(0x00000000)
#define NS9750_SER_CTRL_A_WLS_6		(0x01000000)
#define NS9750_SER_CTRL_A_WLS_7		(0x02000000)
#define NS9750_SER_CTRL_A_WLS_8		(0x03000000)
#define NS9750_SER_CTRL_A_CTSTX		(0x00800000)
#define NS9750_SER_CTRL_A_RTSRX		(0x00400000)
#define NS9750_SER_CTRL_A_RL		(0x00200000)
#define NS9750_SER_CTRL_A_LL		(0x00100000)
#define NS9750_SER_CTRL_A_RES		(0x000CF000)
#define NS9750_SER_CTRL_A_DTR		(0x00020000)
#define NS9750_SER_CTRL_A_RTS		(0x00010000)
#define NS9750_SER_CTRL_A_RIE_MA	(0x00000E00)
#define NS9750_SER_CTRL_A_ERXDMA	(0x00000100)
#define NS9750_SER_CTRL_A_RIC_MA	(0x000000E0)
#define NS9750_SER_CTRL_A_TIC_MA	(0x0000001E)
#define NS9750_SER_CTRL_A_ETXDMA	(0x00000001)

/* control B register */

#define NS9750_SER_CTRL_B_RDM1		(0x80000000)
#define NS9750_SER_CTRL_B_RDM2		(0x40000000)
#define NS9750_SER_CTRL_B_RDM3		(0x20000000)
#define NS9750_SER_CTRL_B_RDM4		(0x10000000)
#define NS9750_SER_CTRL_B_RBGT		(0x08000000)
#define NS9750_SER_CTRL_B_RCGT		(0x04000000)
#define NS9750_SER_CTRL_B_MODE_MA	(0x00300000)
#define NS9750_SER_CTRL_B_MODE_UART	(0x00000000)
#define NS9750_SER_CTRL_B_MODE_HDLC	(0x00100000)
#define NS9750_SER_CTRL_B_MODE_SPI_M	(0x00200000)
#define NS9750_SER_CTRL_B_MODE_SPI_S	(0x00300000)
#define NS9750_SER_CTRL_B_BITORDR	(0x00080000)
#define NS9750_SER_CTRL_B_RES		(0x0007703F)
#define NS9750_SER_CTRL_B_RTSTX		(0x00008000)
#define NS9750_SER_CTRL_B_ENDEC_MA	(0x00000FC0)

/* status A register */

#define NS9750_SER_STAT_A_MATCH1	(0x80000000)
#define NS9750_SER_STAT_A_MATCH2	(0x40000000)
#define NS9750_SER_STAT_A_MATCH3	(0x20000000)
#define NS9750_SER_STAT_A_MATCH4	(0x10000000)
#define NS9750_SER_STAT_A_BGAP		(0x08000000)
#define NS9750_SER_STAT_A_CGAP		(0x04000000)
#define NS9750_SER_STAT_A_RXFDB_MA	(0x00300000)
#define NS9750_SER_STAT_A_RXFDB_FULL	(0x00000000)
#define NS9750_SER_STAT_A_RXFDB_1	(0x00100000)
#define NS9750_SER_STAT_A_RXFDB_2	(0x00200000)
#define NS9750_SER_STAT_A_RXFDB_3	(0x00300000)
#define NS9750_SER_STAT_A_DCD		(0x00080000)
#define NS9750_SER_STAT_A_RI		(0x00040000)
#define NS9750_SER_STAT_A_DSR		(0x00020000)
#define NS9750_SER_STAT_A_CTS		(0x00010000)
#define NS9750_SER_STAT_A_RBRK		(0x00008000)
#define NS9750_SER_STAT_A_RFE		(0x00004000)
#define NS9750_SER_STAT_A_RPE		(0x00002000)
#define NS9750_SER_STAT_A_ROVER		(0x00001000)
#define NS9750_SER_STAT_A_RRDY		(0x00000800)
#define NS9750_SER_STAT_A_RHALF		(0x00000400)
#define NS9750_SER_STAT_A_RBC		(0x00000200)
#define NS9750_SER_STAT_A_RFULL		(0x00000100)
#define NS9750_SER_STAT_A_DCDI		(0x00000080)
#define NS9750_SER_STAT_A_RII		(0x00000040)
#define NS9750_SER_STAT_A_DSRI		(0x00000020)
#define NS9750_SER_STAT_A_CTSI		(0x00000010)
#define NS9750_SER_STAT_A_TRDY		(0x00000008)
#define NS9750_SER_STAT_A_THALF		(0x00000004)
#define NS9750_SER_STAT_A_TBC		(0x00000002)
#define NS9750_SER_STAT_A_TEMPTY	(0x00000001)

#define NS9750_SER_STAT_A_RX_COND_ERR ( NS9750_SER_STAT_A_RFE | \
				        NS9750_SER_STAT_A_ROVER | \
				        NS9750_SER_STAT_A_RPE )
#define NS9750_SER_STAT_A_RX_COND_ALL ( NS9750_SER_STAT_A_RX_COND_ERR | \
				        NS9750_SER_STAT_A_RBRK | \
				        NS9750_SER_STAT_A_RRDY | \
					NS9750_SER_STAT_A_RHALF | \
					NS9750_SER_STAT_A_RBC | \
					NS9750_SER_STAT_A_DCDI | \
					NS9750_SER_STAT_A_RII | \
					NS9750_SER_STAT_A_DSRI | \
					NS9750_SER_STAT_A_CTSI )
#define NS9750_SER_STAT_A_TX_COND_ALL ( NS9750_SER_STAT_A_TRDY | \
				        NS9750_SER_STAT_A_THALF | \
				        NS9750_SER_STAT_A_TBC | \
					NS9750_SER_STAT_A_TEMPTY )
/* bit rate register */

#define NS9750_SER_BITRATE_EBIT		 (0x80000000)
#define NS9750_SER_BITRATE_TMODE	 (0x40000000)
#define NS9750_SER_BITRATE_RXSRC	 (0x20000000)
#define NS9750_SER_BITRATE_TXSRC	 (0x10000000)
#define NS9750_SER_BITRATE_RXEXT	 (0x08000000)
#define NS9750_SER_BITRATE_TXEXT	 (0x04000000)
#define NS9750_SER_BITRATE_CLKMUX_MA	 (0x03000000)
#define NS9750_SER_BITRATE_CLKMUX_XTAL	 (0x00000000)
#define NS9750_SER_BITRATE_CLKMUX_BCLK	 (0x01000000)
#define NS9750_SER_BITRATE_CLKMUX_OUT1	 (0x02000000)
#define NS9750_SER_BITRATE_CLKMUX_OUT2	 (0x03000000)
#define NS9750_SER_BITRATE_TXCINV	 (0x00800000)
#define NS9750_SER_BITRATE_RXCINV	 (0x00400000)
#define NS9750_SER_BITRATE_TCDR_MA	 (0x00180000)
#define NS9750_SER_BITRATE_TCDR_1	 (0x00000000)
#define NS9750_SER_BITRATE_TCDR_8	 (0x00080000)
#define NS9750_SER_BITRATE_TCDR_16	 (0x00100000)
#define NS9750_SER_BITRATE_TCDR_32	 (0x00180000)
#define NS9750_SER_BITRATE_RCDR_MA	 (0x00070000)
#define NS9750_SER_BITRATE_RCDR_1	 (0x00000000)
#define NS9750_SER_BITRATE_RCDR_8	 (0x00020000)
#define NS9750_SER_BITRATE_RCDR_16	 (0x00040000)
#define NS9750_SER_BITRATE_RCDR_32	 (0x00060000)
#define NS9750_SER_BITRATE_TICS		 (0x00010000)
#define NS9750_SER_BITRATE_RICS		 (0x00008000)
#define NS9750_SER_BITRATE_N_MA		 (0x00007FFF)

/* receive buffer gap timer */

#define NS9750_SER_RX_BUF_TIMER_TRUN	 (0x80000000) /* UART and SPI */
#define NS9750_SER_RX_BUF_TIMER_BT_MA	 (0x0000FFFF) /* UART and SPI */
#define NS9750_SER_RX_BUF_TIMER_MAXLEN_MA (0x0000FFFF) /* HDLC only */

/* receive character gap timer */

#define NS9750_SER_RX_CHAR_TIMER_TRUN	 (0x80000000)
#define NS9750_SER_RX_CHAR_TIMER_CT_MA	 (0x000FFFFF)

/* receive match */

#define NS9750_SER_RX_MATCH_RDMB1_MA	 (0xFF000000)
#define NS9750_SER_RX_MATCH_RDMB2_MA	 (0x00FF0000)
#define NS9750_SER_RX_MATCH_RDMB3_MA	 (0x0000FF00)
#define NS9750_SER_RX_MATCH_RDMB4_MA	 (0x000000FF)

/* receive match mask */

#define NS9750_SER_RX_MATCH_MASK_RDMB1_MA (0xFF000000)
#define NS9750_SER_RX_MATCH_MASK_RDMB2_MA (0x00FF0000)
#define NS9750_SER_RX_MATCH_MASK_RDMB3_MA (0x0000FF00)
#define NS9750_SER_RX_MATCH_MASK_RDMB4_MA (0x000000FF)

#endif /* FS_NS9750_SER_H */
Commit	Line	Data
80885a9d WD	1	/***********************************************************************
	2	*
	3	* Copyright (C) 2004 by FS Forth-Systeme GmbH.
	4	* All rights reserved.
	5	*
	6	* $Id: ns9750_ser.h,v 1.1 2004/02/16 10:37:20 mpietrek Exp $
	7	* @Author: Markus Pietrek
	8	* @References: [1] NS9750 Hardware Reference, December 2003
	9	*
	10	* This program is free software; you can redistribute it and/or
	11	* modify it under the terms of the GNU General Public License as
	12	* published by the Free Software Foundation; either version 2 of
	13	* the License, or (at your option) any later version.
	14	*
	15	* This program is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	* GNU General Public License for more details.
	19	*
	20	* You should have received a copy of the GNU General Public License
	21	* along with this program; if not, write to the Free Software
	22	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	23	* MA 02111-1307 USA
	24	*
	25	***********************************************************************/
	26
	27	#ifndef FS_NS9750_SER_H
	28	#define FS_NS9750_SER_H
	29
	30	#define NS9750_SER_MODULE_BASE (0x90200000)
	31
	32	#define get_ser_reg_addr(c) \
	33	((volatile unsigned int *)(NS9750_SER_MODULE_BASE+(unsigned int) (c)))
	34
	35	#define get_ser_reg_addr_channel(reg,chan) \
	36	get_ser_reg_addr((reg)+(((chan)<2)?0:0x00100000)+(((chan)&1)?0x40:0))
	37
	38	/* the register addresses */
	39
	40	#define NS9750_SER_CTRL_A (0x00)
	41	#define NS9750_SER_CTRL_B (0x04)
	42	#define NS9750_SER_STAT_A (0x08)
	43	#define NS9750_SER_BITRATE (0x0C)
	44	#define NS9750_SER_FIFO (0x10)
	45	#define NS9750_SER_RX_BUF_TIMER (0x14)
	46	#define NS9750_SER_RX_CHAR_TIMER (0x18)
	47	#define NS9750_SER_RX_MATCH (0x1C)
	48	#define NS9750_SER_RX_MATCH_MASK (0x20)
	49	#define NS9750_SER_FLOW_CTRL (0x34)
	50	#define NS9750_SER_FLOW_CTRL_FORCE (0x38)
	51
	52	/* register bit fields */
	53
	54	/* control A register */
	55
	56	#define NS9750_SER_CTRL_A_CE (0x80000000)
	57	#define NS9750_SER_CTRL_A_BRK (0x40000000)
	58	#define NS9750_SER_CTRL_A_STICKP (0x20000000)
	59	#define NS9750_SER_CTRL_A_EPS (0x10000000)
	60	#define NS9750_SER_CTRL_A_PE (0x08000000)
	61	#define NS9750_SER_CTRL_A_STOP (0x04000000)
	62	#define NS9750_SER_CTRL_A_WLS_MA (0x03000000)
	63	#define NS9750_SER_CTRL_A_WLS_5 (0x00000000)
	64	#define NS9750_SER_CTRL_A_WLS_6 (0x01000000)
65	#define NS9750_SER_CTRL_A_WLS_7 (0x02000000)
66	#define NS9750_SER_CTRL_A_WLS_8 (0x03000000)
67	#define NS9750_SER_CTRL_A_CTSTX (0x00800000)
68	#define NS9750_SER_CTRL_A_RTSRX (0x00400000)
69	#define NS9750_SER_CTRL_A_RL (0x00200000)
70	#define NS9750_SER_CTRL_A_LL (0x00100000)
71	#define NS9750_SER_CTRL_A_RES (0x000CF000)
72	#define NS9750_SER_CTRL_A_DTR (0x00020000)
73	#define NS9750_SER_CTRL_A_RTS (0x00010000)
74	#define NS9750_SER_CTRL_A_RIE_MA (0x00000E00)
75	#define NS9750_SER_CTRL_A_ERXDMA (0x00000100)
76	#define NS9750_SER_CTRL_A_RIC_MA (0x000000E0)
77	#define NS9750_SER_CTRL_A_TIC_MA (0x0000001E)
53677ef1	78	#define NS9750_SER_CTRL_A_ETXDMA (0x00000001)
80885a9d WD	79
	80	/* control B register */
	81
	82	#define NS9750_SER_CTRL_B_RDM1 (0x80000000)
	83	#define NS9750_SER_CTRL_B_RDM2 (0x40000000)
	84	#define NS9750_SER_CTRL_B_RDM3 (0x20000000)
	85	#define NS9750_SER_CTRL_B_RDM4 (0x10000000)
	86	#define NS9750_SER_CTRL_B_RBGT (0x08000000)
	87	#define NS9750_SER_CTRL_B_RCGT (0x04000000)
	88	#define NS9750_SER_CTRL_B_MODE_MA (0x00300000)
	89	#define NS9750_SER_CTRL_B_MODE_UART (0x00000000)
	90	#define NS9750_SER_CTRL_B_MODE_HDLC (0x00100000)
	91	#define NS9750_SER_CTRL_B_MODE_SPI_M (0x00200000)
	92	#define NS9750_SER_CTRL_B_MODE_SPI_S (0x00300000)
	93	#define NS9750_SER_CTRL_B_BITORDR (0x00080000)
	94	#define NS9750_SER_CTRL_B_RES (0x0007703F)
	95	#define NS9750_SER_CTRL_B_RTSTX (0x00008000)
	96	#define NS9750_SER_CTRL_B_ENDEC_MA (0x00000FC0)
	97
	98	/* status A register */
	99
	100	#define NS9750_SER_STAT_A_MATCH1 (0x80000000)
	101	#define NS9750_SER_STAT_A_MATCH2 (0x40000000)
	102	#define NS9750_SER_STAT_A_MATCH3 (0x20000000)
	103	#define NS9750_SER_STAT_A_MATCH4 (0x10000000)
	104	#define NS9750_SER_STAT_A_BGAP (0x08000000)
	105	#define NS9750_SER_STAT_A_CGAP (0x04000000)
	106	#define NS9750_SER_STAT_A_RXFDB_MA (0x00300000)
	107	#define NS9750_SER_STAT_A_RXFDB_FULL (0x00000000)
	108	#define NS9750_SER_STAT_A_RXFDB_1 (0x00100000)
	109	#define NS9750_SER_STAT_A_RXFDB_2 (0x00200000)
	110	#define NS9750_SER_STAT_A_RXFDB_3 (0x00300000)
	111	#define NS9750_SER_STAT_A_DCD (0x00080000)
	112	#define NS9750_SER_STAT_A_RI (0x00040000)
	113	#define NS9750_SER_STAT_A_DSR (0x00020000)
	114	#define NS9750_SER_STAT_A_CTS (0x00010000)
	115	#define NS9750_SER_STAT_A_RBRK (0x00008000)
	116	#define NS9750_SER_STAT_A_RFE (0x00004000)
	117	#define NS9750_SER_STAT_A_RPE (0x00002000)
	118	#define NS9750_SER_STAT_A_ROVER (0x00001000)
	119	#define NS9750_SER_STAT_A_RRDY (0x00000800)
	120	#define NS9750_SER_STAT_A_RHALF (0x00000400)
	121	#define NS9750_SER_STAT_A_RBC (0x00000200)
	122	#define NS9750_SER_STAT_A_RFULL (0x00000100)
	123	#define NS9750_SER_STAT_A_DCDI (0x00000080)
	124	#define NS9750_SER_STAT_A_RII (0x00000040)
	125	#define NS9750_SER_STAT_A_DSRI (0x00000020)
	126	#define NS9750_SER_STAT_A_CTSI (0x00000010)
	127	#define NS9750_SER_STAT_A_TRDY (0x00000008)
	128	#define NS9750_SER_STAT_A_THALF (0x00000004)
	129	#define NS9750_SER_STAT_A_TBC (0x00000002)
	130	#define NS9750_SER_STAT_A_TEMPTY (0x00000001)
	131
	132	#define NS9750_SER_STAT_A_RX_COND_ERR ( NS9750_SER_STAT_A_RFE \| \
53677ef1	133	NS9750_SER_STAT_A_ROVER \| \
80885a9d WD	134	NS9750_SER_STAT_A_RPE )
	135	#define NS9750_SER_STAT_A_RX_COND_ALL ( NS9750_SER_STAT_A_RX_COND_ERR \| \
	136	NS9750_SER_STAT_A_RBRK \| \
	137	NS9750_SER_STAT_A_RRDY \| \
53677ef1 WD	138	NS9750_SER_STAT_A_RHALF \| \
	139	NS9750_SER_STAT_A_RBC \| \
	140	NS9750_SER_STAT_A_DCDI \| \
	141	NS9750_SER_STAT_A_RII \| \
	142	NS9750_SER_STAT_A_DSRI \| \
	143	NS9750_SER_STAT_A_CTSI )
80885a9d WD	144	#define NS9750_SER_STAT_A_TX_COND_ALL ( NS9750_SER_STAT_A_TRDY \| \
	145	NS9750_SER_STAT_A_THALF \| \
	146	NS9750_SER_STAT_A_TBC \| \
53677ef1	147	NS9750_SER_STAT_A_TEMPTY )
80885a9d WD	148	/* bit rate register */
	149
	150	#define NS9750_SER_BITRATE_EBIT (0x80000000)
	151	#define NS9750_SER_BITRATE_TMODE (0x40000000)
	152	#define NS9750_SER_BITRATE_RXSRC (0x20000000)
	153	#define NS9750_SER_BITRATE_TXSRC (0x10000000)
	154	#define NS9750_SER_BITRATE_RXEXT (0x08000000)
	155	#define NS9750_SER_BITRATE_TXEXT (0x04000000)
	156	#define NS9750_SER_BITRATE_CLKMUX_MA (0x03000000)
	157	#define NS9750_SER_BITRATE_CLKMUX_XTAL (0x00000000)
	158	#define NS9750_SER_BITRATE_CLKMUX_BCLK (0x01000000)
	159	#define NS9750_SER_BITRATE_CLKMUX_OUT1 (0x02000000)
	160	#define NS9750_SER_BITRATE_CLKMUX_OUT2 (0x03000000)
	161	#define NS9750_SER_BITRATE_TXCINV (0x00800000)
	162	#define NS9750_SER_BITRATE_RXCINV (0x00400000)
	163	#define NS9750_SER_BITRATE_TCDR_MA (0x00180000)
53677ef1 WD	164	#define NS9750_SER_BITRATE_TCDR_1 (0x00000000)
53677ef1 WD	165	#define NS9750_SER_BITRATE_TCDR_8 (0x00080000)
80885a9d WD	166	#define NS9750_SER_BITRATE_TCDR_16 (0x00100000)
	167	#define NS9750_SER_BITRATE_TCDR_32 (0x00180000)
	168	#define NS9750_SER_BITRATE_RCDR_MA (0x00070000)
53677ef1 WD	169	#define NS9750_SER_BITRATE_RCDR_1 (0x00000000)
53677ef1 WD	170	#define NS9750_SER_BITRATE_RCDR_8 (0x00020000)
80885a9d WD	171	#define NS9750_SER_BITRATE_RCDR_16 (0x00040000)
	172	#define NS9750_SER_BITRATE_RCDR_32 (0x00060000)
	173	#define NS9750_SER_BITRATE_TICS (0x00010000)
	174	#define NS9750_SER_BITRATE_RICS (0x00008000)
	175	#define NS9750_SER_BITRATE_N_MA (0x00007FFF)
	176
	177	/* receive buffer gap timer */
	178
	179	#define NS9750_SER_RX_BUF_TIMER_TRUN (0x80000000) /* UART and SPI */
	180	#define NS9750_SER_RX_BUF_TIMER_BT_MA (0x0000FFFF) /* UART and SPI */
	181	#define NS9750_SER_RX_BUF_TIMER_MAXLEN_MA (0x0000FFFF) /* HDLC only */
	182
	183	/* receive character gap timer */
	184
	185	#define NS9750_SER_RX_CHAR_TIMER_TRUN (0x80000000)
	186	#define NS9750_SER_RX_CHAR_TIMER_CT_MA (0x000FFFFF)
	187
	188	/* receive match */
	189
	190	#define NS9750_SER_RX_MATCH_RDMB1_MA (0xFF000000)
	191	#define NS9750_SER_RX_MATCH_RDMB2_MA (0x00FF0000)
	192	#define NS9750_SER_RX_MATCH_RDMB3_MA (0x0000FF00)
	193	#define NS9750_SER_RX_MATCH_RDMB4_MA (0x000000FF)
	194
	195	/* receive match mask */
	196
	197	#define NS9750_SER_RX_MATCH_MASK_RDMB1_MA (0xFF000000)
	198	#define NS9750_SER_RX_MATCH_MASK_RDMB2_MA (0x00FF0000)
	199	#define NS9750_SER_RX_MATCH_MASK_RDMB3_MA (0x0000FF00)
	200	#define NS9750_SER_RX_MATCH_MASK_RDMB4_MA (0x000000FF)
	201
	202	#endif /* FS_NS9750_SER_H */