]> git.ipfire.org Git - people/ms/u-boot.git/blame - include/pci.h
projects / people / ms / u-boot.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
NAND: Fix integer overflow in ONFI detection of chips >= 4GiB
[people/ms/u-boot.git] / include / pci.h
CommitLineData
c609719b
WD		 1/*
2 * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
3 * Andreas Heppel <aheppel@sysgo.de>
4 *
5 * (C) Copyright 2002
6 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * aloong with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27#ifndef _PCI_H
28#define _PCI_H
29
30/*
31 * Under PCI, each device has 256 bytes of configuration address space,
32 * of which the first 64 bytes are standardized as follows:
33 */
34#define PCI_VENDOR_ID 0x00 /* 16 bits */
35#define PCI_DEVICE_ID 0x02 /* 16 bits */
36#define PCI_COMMAND 0x04 /* 16 bits */
37#define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
38#define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
39#define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */
40#define PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */
41#define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */
42#define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */
43#define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */
44#define PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */
45#define PCI_COMMAND_SERR 0x100 /* Enable SERR */
46#define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */
47
48#define PCI_STATUS 0x06 /* 16 bits */
49#define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */
50#define PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */
51#define PCI_STATUS_UDF 0x40 /* Support User Definable Features [obsolete] */
52#define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */
53#define PCI_STATUS_PARITY 0x100 /* Detected parity error */
54#define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */
55#define PCI_STATUS_DEVSEL_FAST 0x000
56#define PCI_STATUS_DEVSEL_MEDIUM 0x200
57#define PCI_STATUS_DEVSEL_SLOW 0x400
58#define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */
59#define PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */
60#define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */
61#define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */
62#define PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */
63
64#define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8
65 revision */
66#define PCI_REVISION_ID 0x08 /* Revision ID */
67#define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */
68#define PCI_CLASS_DEVICE 0x0a /* Device class */
69#define PCI_CLASS_CODE 0x0b /* Device class code */
70#define PCI_CLASS_SUB_CODE 0x0a /* Device sub-class code */
71
72#define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */
73#define PCI_LATENCY_TIMER 0x0d /* 8 bits */
74#define PCI_HEADER_TYPE 0x0e /* 8 bits */
75#define PCI_HEADER_TYPE_NORMAL 0
76#define PCI_HEADER_TYPE_BRIDGE 1
77#define PCI_HEADER_TYPE_CARDBUS 2
78
79#define PCI_BIST 0x0f /* 8 bits */
80#define PCI_BIST_CODE_MASK 0x0f /* Return result */
81#define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */
82#define PCI_BIST_CAPABLE 0x80 /* 1 if BIST capable */
83
84/*
85 * Base addresses specify locations in memory or I/O space.
86 * Decoded size can be determined by writing a value of
87 * 0xffffffff to the register, and reading it back. Only
88 * 1 bits are decoded.
89 */
90#define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */
91#define PCI_BASE_ADDRESS_1 0x14 /* 32 bits [htype 0,1 only] */
92#define PCI_BASE_ADDRESS_2 0x18 /* 32 bits [htype 0 only] */
93#define PCI_BASE_ADDRESS_3 0x1c /* 32 bits */
94#define PCI_BASE_ADDRESS_4 0x20 /* 32 bits */
95#define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */
96#define PCI_BASE_ADDRESS_SPACE 0x01 /* 0 = memory, 1 = I/O */
97#define PCI_BASE_ADDRESS_SPACE_IO 0x01
98#define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00
99#define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06
100#define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00 /* 32 bit address */
101#define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 /* Below 1M [obsolete] */
102#define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */
103#define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 /* prefetchable? */
30e76d5e
KG		 104#define PCI_BASE_ADDRESS_MEM_MASK (~0x0fULL)
105#define PCI_BASE_ADDRESS_IO_MASK (~0x03ULL)
c609719b
WD		 106/* bit 1 is reserved if address_space = 1 */
107
108/* Header type 0 (normal devices) */
109#define PCI_CARDBUS_CIS 0x28
110#define PCI_SUBSYSTEM_VENDOR_ID 0x2c
111#define PCI_SUBSYSTEM_ID 0x2e
112#define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */
113#define PCI_ROM_ADDRESS_ENABLE 0x01
30e76d5e 114#define PCI_ROM_ADDRESS_MASK (~0x7ffULL)
c609719b
WD		 115
116#define PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */
117
118/* 0x35-0x3b are reserved */
119#define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
120#define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
121#define PCI_MIN_GNT 0x3e /* 8 bits */
122#define PCI_MAX_LAT 0x3f /* 8 bits */
123
124/* Header type 1 (PCI-to-PCI bridges) */
125#define PCI_PRIMARY_BUS 0x18 /* Primary bus number */
126#define PCI_SECONDARY_BUS 0x19 /* Secondary bus number */
127#define PCI_SUBORDINATE_BUS 0x1a /* Highest bus number behind the bridge */
128#define PCI_SEC_LATENCY_TIMER 0x1b /* Latency timer for secondary interface */
129#define PCI_IO_BASE 0x1c /* I/O range behind the bridge */
130#define PCI_IO_LIMIT 0x1d
131#define PCI_IO_RANGE_TYPE_MASK 0x0f /* I/O bridging type */
132#define PCI_IO_RANGE_TYPE_16 0x00
133#define PCI_IO_RANGE_TYPE_32 0x01
134#define PCI_IO_RANGE_MASK ~0x0f
135#define PCI_SEC_STATUS 0x1e /* Secondary status register, only bit 14 used */
136#define PCI_MEMORY_BASE 0x20 /* Memory range behind */
137#define PCI_MEMORY_LIMIT 0x22
138#define PCI_MEMORY_RANGE_TYPE_MASK 0x0f
139#define PCI_MEMORY_RANGE_MASK ~0x0f
140#define PCI_PREF_MEMORY_BASE 0x24 /* Prefetchable memory range behind */
141#define PCI_PREF_MEMORY_LIMIT 0x26
142#define PCI_PREF_RANGE_TYPE_MASK 0x0f
143#define PCI_PREF_RANGE_TYPE_32 0x00
144#define PCI_PREF_RANGE_TYPE_64 0x01
145#define PCI_PREF_RANGE_MASK ~0x0f
146#define PCI_PREF_BASE_UPPER32 0x28 /* Upper half of prefetchable memory range */
147#define PCI_PREF_LIMIT_UPPER32 0x2c
148#define PCI_IO_BASE_UPPER16 0x30 /* Upper half of I/O addresses */
149#define PCI_IO_LIMIT_UPPER16 0x32
150/* 0x34 same as for htype 0 */
151/* 0x35-0x3b is reserved */
152#define PCI_ROM_ADDRESS1 0x38 /* Same as PCI_ROM_ADDRESS, but for htype 1 */
153/* 0x3c-0x3d are same as for htype 0 */
154#define PCI_BRIDGE_CONTROL 0x3e
155#define PCI_BRIDGE_CTL_PARITY 0x01 /* Enable parity detection on secondary interface */
156#define PCI_BRIDGE_CTL_SERR 0x02 /* The same for SERR forwarding */
157#define PCI_BRIDGE_CTL_NO_ISA 0x04 /* Disable bridging of ISA ports */
158#define PCI_BRIDGE_CTL_VGA 0x08 /* Forward VGA addresses */
159#define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */
160#define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */
161#define PCI_BRIDGE_CTL_FAST_BACK 0x80 /* Fast Back2Back enabled on secondary interface */
162
c157d8e2
SR		 163/* From 440ep */
164#define PCI_ERREN 0x48 /* Error Enable */
165#define PCI_ERRSTS 0x49 /* Error Status */
166#define PCI_BRDGOPT1 0x4A /* PCI Bridge Options 1 */
167#define PCI_PLBSESR0 0x4C /* PCI PLB Slave Error Syndrome 0 */
168#define PCI_PLBSESR1 0x50 /* PCI PLB Slave Error Syndrome 1 */
169#define PCI_PLBSEAR 0x54 /* PCI PLB Slave Error Address */
170#define PCI_CAPID 0x58 /* Capability Identifier */
171#define PCI_NEXTITEMPTR 0x59 /* Next Item Pointer */
172#define PCI_PMC 0x5A /* Power Management Capabilities */
173#define PCI_PMCSR 0x5C /* Power Management Control Status */
174#define PCI_PMCSRBSE 0x5E /* PMCSR PCI to PCI Bridge Support Extensions */
175#define PCI_BRDGOPT2 0x60 /* PCI Bridge Options 2 */
176#define PCI_PMSCRR 0x64 /* Power Management State Change Request Re. */
177
c609719b
WD		 178/* Header type 2 (CardBus bridges) */
179#define PCI_CB_CAPABILITY_LIST 0x14
180/* 0x15 reserved */
181#define PCI_CB_SEC_STATUS 0x16 /* Secondary status */
182#define PCI_CB_PRIMARY_BUS 0x18 /* PCI bus number */
183#define PCI_CB_CARD_BUS 0x19 /* CardBus bus number */
184#define PCI_CB_SUBORDINATE_BUS 0x1a /* Subordinate bus number */
185#define PCI_CB_LATENCY_TIMER 0x1b /* CardBus latency timer */
186#define PCI_CB_MEMORY_BASE_0 0x1c
187#define PCI_CB_MEMORY_LIMIT_0 0x20
188#define PCI_CB_MEMORY_BASE_1 0x24
189#define PCI_CB_MEMORY_LIMIT_1 0x28
190#define PCI_CB_IO_BASE_0 0x2c
191#define PCI_CB_IO_BASE_0_HI 0x2e
192#define PCI_CB_IO_LIMIT_0 0x30
193#define PCI_CB_IO_LIMIT_0_HI 0x32
194#define PCI_CB_IO_BASE_1 0x34
195#define PCI_CB_IO_BASE_1_HI 0x36
196#define PCI_CB_IO_LIMIT_1 0x38
197#define PCI_CB_IO_LIMIT_1_HI 0x3a
198#define PCI_CB_IO_RANGE_MASK ~0x03
199/* 0x3c-0x3d are same as for htype 0 */
200#define PCI_CB_BRIDGE_CONTROL 0x3e
201#define PCI_CB_BRIDGE_CTL_PARITY 0x01 /* Similar to standard bridge control register */
202#define PCI_CB_BRIDGE_CTL_SERR 0x02
203#define PCI_CB_BRIDGE_CTL_ISA 0x04
204#define PCI_CB_BRIDGE_CTL_VGA 0x08
205#define PCI_CB_BRIDGE_CTL_MASTER_ABORT 0x20
206#define PCI_CB_BRIDGE_CTL_CB_RESET 0x40 /* CardBus reset */
207#define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80 /* Enable interrupt for 16-bit cards */
208#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100 /* Prefetch enable for both memory regions */
209#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200
210#define PCI_CB_BRIDGE_CTL_POST_WRITES 0x400
211#define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40
212#define PCI_CB_SUBSYSTEM_ID 0x42
213#define PCI_CB_LEGACY_MODE_BASE 0x44 /* 16-bit PC Card legacy mode base address (ExCa) */
214/* 0x48-0x7f reserved */
215
216/* Capability lists */
217
218#define PCI_CAP_LIST_ID 0 /* Capability ID */
219#define PCI_CAP_ID_PM 0x01 /* Power Management */
220#define PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */
221#define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */
222#define PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */
223#define PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */
224#define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */
8295b944 225#define PCI_CAP_ID_EXP 0x10 /* PCI Express */
c609719b
WD		 226#define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */
227#define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits) */
228#define PCI_CAP_SIZEOF 4
229
230/* Power Management Registers */
231
232#define PCI_PM_CAP_VER_MASK 0x0007 /* Version */
233#define PCI_PM_CAP_PME_CLOCK 0x0008 /* PME clock required */
234#define PCI_PM_CAP_AUX_POWER 0x0010 /* Auxilliary power support */
235#define PCI_PM_CAP_DSI 0x0020 /* Device specific initialization */
236#define PCI_PM_CAP_D1 0x0200 /* D1 power state support */
237#define PCI_PM_CAP_D2 0x0400 /* D2 power state support */
238#define PCI_PM_CAP_PME 0x0800 /* PME pin supported */
239#define PCI_PM_CTRL 4 /* PM control and status register */
240#define PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */
241#define PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */
242#define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (??) */
243#define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* Data scale (??) */
244#define PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */
245#define PCI_PM_PPB_EXTENSIONS 6 /* PPB support extensions (??) */
246#define PCI_PM_PPB_B2_B3 0x40 /* Stop clock when in D3hot (??) */
247#define PCI_PM_BPCC_ENABLE 0x80 /* Bus power/clock control enable (??) */
248#define PCI_PM_DATA_REGISTER 7 /* (??) */
249#define PCI_PM_SIZEOF 8
250
251/* AGP registers */
252
253#define PCI_AGP_VERSION 2 /* BCD version number */
254#define PCI_AGP_RFU 3 /* Rest of capability flags */
255#define PCI_AGP_STATUS 4 /* Status register */
256#define PCI_AGP_STATUS_RQ_MASK 0xff000000 /* Maximum number of requests - 1 */
257#define PCI_AGP_STATUS_SBA 0x0200 /* Sideband addressing supported */
258#define PCI_AGP_STATUS_64BIT 0x0020 /* 64-bit addressing supported */
259#define PCI_AGP_STATUS_FW 0x0010 /* FW transfers supported */
260#define PCI_AGP_STATUS_RATE4 0x0004 /* 4x transfer rate supported */
261#define PCI_AGP_STATUS_RATE2 0x0002 /* 2x transfer rate supported */
262#define PCI_AGP_STATUS_RATE1 0x0001 /* 1x transfer rate supported */
263#define PCI_AGP_COMMAND 8 /* Control register */
264#define PCI_AGP_COMMAND_RQ_MASK 0xff000000 /* Master: Maximum number of requests */
265#define PCI_AGP_COMMAND_SBA 0x0200 /* Sideband addressing enabled */
266#define PCI_AGP_COMMAND_AGP 0x0100 /* Allow processing of AGP transactions */
267#define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow processing of 64-bit addresses */
268#define PCI_AGP_COMMAND_FW 0x0010 /* Force FW transfers */
269#define PCI_AGP_COMMAND_RATE4 0x0004 /* Use 4x rate */
270#define PCI_AGP_COMMAND_RATE2 0x0002 /* Use 4x rate */
271#define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 4x rate */
272#define PCI_AGP_SIZEOF 12
273
f0e6f57f
MM		 274/* PCI-X registers */
275
276#define PCI_X_CMD_DPERR_E 0x0001 /* Data Parity Error Recovery Enable */
277#define PCI_X_CMD_ERO 0x0002 /* Enable Relaxed Ordering */
278#define PCI_X_CMD_MAX_READ 0x0000 /* Max Memory Read Byte Count */
279#define PCI_X_CMD_MAX_SPLIT 0x0030 /* Max Outstanding Split Transactions */
280#define PCI_X_CMD_VERSION(x) (((x) >> 12) & 3) /* Version */
281
282
c609719b
WD		 283/* Slot Identification */
284
285#define PCI_SID_ESR 2 /* Expansion Slot Register */
286#define PCI_SID_ESR_NSLOTS 0x1f /* Number of expansion slots available */
287#define PCI_SID_ESR_FIC 0x20 /* First In Chassis Flag */
288#define PCI_SID_CHASSIS_NR 3 /* Chassis Number */
289
290/* Message Signalled Interrupts registers */
291
292#define PCI_MSI_FLAGS 2 /* Various flags */
293#define PCI_MSI_FLAGS_64BIT 0x80 /* 64-bit addresses allowed */
294#define PCI_MSI_FLAGS_QSIZE 0x70 /* Message queue size configured */
295#define PCI_MSI_FLAGS_QMASK 0x0e /* Maximum queue size available */
296#define PCI_MSI_FLAGS_ENABLE 0x01 /* MSI feature enabled */
297#define PCI_MSI_RFU 3 /* Rest of capability flags */
298#define PCI_MSI_ADDRESS_LO 4 /* Lower 32 bits */
299#define PCI_MSI_ADDRESS_HI 8 /* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */
300#define PCI_MSI_DATA_32 8 /* 16 bits of data for 32-bit devices */
301#define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit devices */
302
303#define PCI_MAX_PCI_DEVICES 32
304#define PCI_MAX_PCI_FUNCTIONS 8
305
63cec581
ES		 306#define PCI_DCR 0x54 /* PCIe Device Control Register */
307#define PCI_DSR 0x56 /* PCIe Device Status Register */
308#define PCI_LSR 0x5e /* PCIe Link Status Register */
b03a466d 309#define PCI_LCR 0x5c /* PCIe Link Control Register */
63cec581
ES		 310#define PCI_LTSSM 0x404 /* PCIe Link Training, Status State Machine */
311#define PCI_LTSSM_L0 0x16 /* L0 state */
312
c609719b
WD		 313/* Include the ID list */
314
315#include <pci_ids.h>
316
30e76d5e
KG		 317#ifdef CONFIG_SYS_PCI_64BIT
318typedef u64 pci_addr_t;
319typedef u64 pci_size_t;
320#else
321typedef u32 pci_addr_t;
322typedef u32 pci_size_t;
323#endif
324
c609719b 325struct pci_region {
30e76d5e
KG		 326 pci_addr_t bus_start; /* Start on the bus */
327 phys_addr_t phys_start; /* Start in physical address space */
328 pci_size_t size; /* Size */
329 unsigned long flags; /* Resource flags */
c609719b 330
30e76d5e 331 pci_addr_t bus_lower;
c609719b
WD		 332};
333
334#define PCI_REGION_MEM 0x00000000 /* PCI memory space */
335#define PCI_REGION_IO 0x00000001 /* PCI IO space */
336#define PCI_REGION_TYPE 0x00000001
a179012e 337#define PCI_REGION_PREFETCH 0x00000008 /* prefetchable PCI memory */
c609719b 338
ff4e66e9 339#define PCI_REGION_SYS_MEMORY 0x00000100 /* System memory */
c609719b
WD		 340#define PCI_REGION_RO 0x00000200 /* Read-only memory */
341
342extern __inline__ void pci_set_region(struct pci_region *reg,
30e76d5e 343 pci_addr_t bus_start,
36f32675 344 phys_addr_t phys_start,
30e76d5e 345 pci_size_t size,
c609719b
WD		 346 unsigned long flags) {
347 reg->bus_start = bus_start;
348 reg->phys_start = phys_start;
349 reg->size = size;
350 reg->flags = flags;
351}
352
353typedef int pci_dev_t;
354
355#define PCI_BUS(d) (((d) >> 16) & 0xff)
356#define PCI_DEV(d) (((d) >> 11) & 0x1f)
357#define PCI_FUNC(d) (((d) >> 8) & 0x7)
358#define PCI_BDF(b,d,f) ((b) << 16 | (d) << 11 | (f) << 8)
359
360#define PCI_ANY_ID (~0)
361
362struct pci_device_id {
363 unsigned int vendor, device; /* Vendor and device ID or PCI_ANY_ID */
364};
365
366struct pci_controller;
367
368struct pci_config_table {
369 unsigned int vendor, device; /* Vendor and device ID or PCI_ANY_ID */
370 unsigned int class; /* Class ID, or PCI_ANY_ID */
371 unsigned int bus; /* Bus number, or PCI_ANY_ID */
372 unsigned int dev; /* Device number, or PCI_ANY_ID */
373 unsigned int func; /* Function number, or PCI_ANY_ID */
374
375 void (*config_device)(struct pci_controller* hose, pci_dev_t dev,
376 struct pci_config_table *);
377 unsigned long priv[3];
378};
379
993a2275
WD		 380extern void pci_cfgfunc_do_nothing(struct pci_controller* hose, pci_dev_t dev,
381 struct pci_config_table *);
c609719b
WD		 382extern void pci_cfgfunc_config_device(struct pci_controller* hose, pci_dev_t dev,
383 struct pci_config_table *);
384
385#define MAX_PCI_REGIONS 7
386
fd6646c0
AV		 387#define INDIRECT_TYPE_NO_PCIE_LINK 1
388
c609719b
WD		 389/*
390 * Structure of a PCI controller (host bridge)
391 */
392struct pci_controller {
393 struct pci_controller *next;
394
395 int first_busno;
396 int last_busno;
397
398 volatile unsigned int *cfg_addr;
399 volatile unsigned char *cfg_data;
400
fd6646c0
AV		 401 int indirect_type;
402
c609719b
WD		 403 struct pci_region regions[MAX_PCI_REGIONS];
404 int region_count;
405
406 struct pci_config_table *config_table;
407
408 void (*fixup_irq)(struct pci_controller *, pci_dev_t);
409
410 /* Low-level architecture-dependent routines */
411 int (*read_byte)(struct pci_controller*, pci_dev_t, int where, u8 *);
412 int (*read_word)(struct pci_controller*, pci_dev_t, int where, u16 *);
413 int (*read_dword)(struct pci_controller*, pci_dev_t, int where, u32 *);
414 int (*write_byte)(struct pci_controller*, pci_dev_t, int where, u8);
415 int (*write_word)(struct pci_controller*, pci_dev_t, int where, u16);
416 int (*write_dword)(struct pci_controller*, pci_dev_t, int where, u32);
417
418 /* Used by auto config */
a179012e 419 struct pci_region *pci_mem, *pci_io, *pci_prefetch;
c609719b
WD		 420
421 /* Used by ppc405 autoconfig*/
422 struct pci_region *pci_fb;
c7de829c 423 int current_busno;
10fa8d7c
LL		 424
425 void *priv_data;
c609719b
WD		 426};
427
428extern __inline__ void pci_set_ops(struct pci_controller *hose,
429 int (*read_byte)(struct pci_controller*,
430 pci_dev_t, int where, u8 *),
431 int (*read_word)(struct pci_controller*,
432 pci_dev_t, int where, u16 *),
433 int (*read_dword)(struct pci_controller*,
434 pci_dev_t, int where, u32 *),
435 int (*write_byte)(struct pci_controller*,
436 pci_dev_t, int where, u8),
437 int (*write_word)(struct pci_controller*,
438 pci_dev_t, int where, u16),
439 int (*write_dword)(struct pci_controller*,
440 pci_dev_t, int where, u32)) {
441 hose->read_byte = read_byte;
442 hose->read_word = read_word;
443 hose->read_dword = read_dword;
444 hose->write_byte = write_byte;
445 hose->write_word = write_word;
446 hose->write_dword = write_dword;
447}
448
449extern void pci_setup_indirect(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data);
450
36f32675 451extern phys_addr_t pci_hose_bus_to_phys(struct pci_controller* hose,
30e76d5e
KG		 452 pci_addr_t addr, unsigned long flags);
453extern pci_addr_t pci_hose_phys_to_bus(struct pci_controller* hose,
454 phys_addr_t addr, unsigned long flags);
c609719b
WD		 455
456#define pci_phys_to_bus(dev, addr, flags) \
457 pci_hose_phys_to_bus(pci_bus_to_hose(PCI_BUS(dev)), (addr), (flags))
458#define pci_bus_to_phys(dev, addr, flags) \
459 pci_hose_bus_to_phys(pci_bus_to_hose(PCI_BUS(dev)), (addr), (flags))
460
6e61fae4
BB		 461#define pci_virt_to_bus(dev, addr, flags) \
462 pci_hose_phys_to_bus(pci_bus_to_hose(PCI_BUS(dev)), \
463 (virt_to_phys(addr)), (flags))
464#define pci_bus_to_virt(dev, addr, flags, len, map_flags) \
465 map_physmem(pci_hose_bus_to_phys(pci_bus_to_hose(PCI_BUS(dev)), \
466 (addr), (flags)), \
467 (len), (map_flags))
468
469#define pci_phys_to_mem(dev, addr) \
470 pci_phys_to_bus((dev), (addr), PCI_REGION_MEM)
471#define pci_mem_to_phys(dev, addr) \
472 pci_bus_to_phys((dev), (addr), PCI_REGION_MEM)
473#define pci_phys_to_io(dev, addr) pci_phys_to_bus((dev), (addr), PCI_REGION_IO)
474#define pci_io_to_phys(dev, addr) pci_bus_to_phys((dev), (addr), PCI_REGION_IO)
475
476#define pci_virt_to_mem(dev, addr) \
477 pci_virt_to_bus((dev), (addr), PCI_REGION_MEM)
478#define pci_mem_to_virt(dev, addr, len, map_flags) \
479 pci_bus_to_virt((dev), (addr), PCI_REGION_MEM, (len), (map_flags))
480#define pci_virt_to_io(dev, addr) \
481 pci_virt_to_bus((dev), (addr), PCI_REGION_IO)
482#define pci_io_to_virt(dev, addr, len, map_flags) \
483 pci_bus_to_virt((dev), (addr), PCI_REGION_IO, (len), (map_flags))
c609719b
WD		 484
485extern int pci_hose_read_config_byte(struct pci_controller *hose,
486 pci_dev_t dev, int where, u8 *val);
487extern int pci_hose_read_config_word(struct pci_controller *hose,
488 pci_dev_t dev, int where, u16 *val);
489extern int pci_hose_read_config_dword(struct pci_controller *hose,
490 pci_dev_t dev, int where, u32 *val);
491extern int pci_hose_write_config_byte(struct pci_controller *hose,
492 pci_dev_t dev, int where, u8 val);
493extern int pci_hose_write_config_word(struct pci_controller *hose,
494 pci_dev_t dev, int where, u16 val);
495extern int pci_hose_write_config_dword(struct pci_controller *hose,
496 pci_dev_t dev, int where, u32 val);
497
498extern int pci_read_config_byte(pci_dev_t dev, int where, u8 *val);
499extern int pci_read_config_word(pci_dev_t dev, int where, u16 *val);
500extern int pci_read_config_dword(pci_dev_t dev, int where, u32 *val);
501extern int pci_write_config_byte(pci_dev_t dev, int where, u8 val);
502extern int pci_write_config_word(pci_dev_t dev, int where, u16 val);
503extern int pci_write_config_dword(pci_dev_t dev, int where, u32 val);
504
505extern int pci_hose_read_config_byte_via_dword(struct pci_controller *hose,
506 pci_dev_t dev, int where, u8 *val);
507extern int pci_hose_read_config_word_via_dword(struct pci_controller *hose,
508 pci_dev_t dev, int where, u16 *val);
509extern int pci_hose_write_config_byte_via_dword(struct pci_controller *hose,
510 pci_dev_t dev, int where, u8 val);
511extern int pci_hose_write_config_word_via_dword(struct pci_controller *hose,
512 pci_dev_t dev, int where, u16 val);
513
6e61fae4 514extern void *pci_map_bar(pci_dev_t pdev, int bar, int flags);
c609719b
WD		 515extern void pci_register_hose(struct pci_controller* hose);
516extern struct pci_controller* pci_bus_to_hose(int bus);
3a0e3c27 517extern struct pci_controller *find_hose_by_cfg_addr(void *cfg_addr);
c609719b
WD		 518
519extern int pci_hose_scan(struct pci_controller *hose);
520extern int pci_hose_scan_bus(struct pci_controller *hose, int bus);
521
522extern void pciauto_region_init(struct pci_region* res);
30e76d5e
KG		 523extern void pciauto_region_align(struct pci_region *res, pci_size_t size);
524extern int pciauto_region_allocate(struct pci_region* res, pci_size_t size, pci_addr_t *bar);
c609719b
WD		 525extern void pciauto_setup_device(struct pci_controller *hose,
526 pci_dev_t dev, int bars_num,
527 struct pci_region *mem,
a179012e 528 struct pci_region *prefetch,
c609719b 529 struct pci_region *io);
c7de829c 530int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev);
c609719b
WD		 531
532extern pci_dev_t pci_find_device (unsigned int vendor, unsigned int device, int index);
533extern pci_dev_t pci_find_devices (struct pci_device_id *ids, int index);
7a8e9bed
WD		 534extern pci_dev_t pci_find_class(int wanted_class, int wanted_sub_code,
535 int wanted_prog_if, int index);
c609719b
WD		 536
537extern int pci_hose_config_device(struct pci_controller *hose,
538 pci_dev_t dev,
539 unsigned long io,
30e76d5e 540 pci_addr_t mem,
c609719b
WD		 541 unsigned long command);
542
983eb9d1 543const char * pci_class_str(u8 class);
cc2a8c77
AV		 544int pci_last_busno(void);
545
c609719b
WD		 546#ifdef CONFIG_MPC824X
547extern void pci_mpc824x_init (struct pci_controller *hose);
548#endif
549
13a7fcdf
JL		 550#ifdef CONFIG_MPC85xx
551extern void pci_mpc85xx_init (struct pci_controller *hose);
552#endif
c609719b 553#endif /* _PCI_H */
"Das U-Boot" Source Tree