projects / people / ms / u-boot.git / blame
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| 66fd3d1c WD |
1 | /* |
| 2 | * ti113x.h 1.31 2002/05/12 18:19:47 | |
| 3 | * | |
| 4 | * The contents of this file are subject to the Mozilla Public License | |
| 5 | * Version 1.1 (the "License"); you may not use this file except in | |
| 6 | * compliance with the License. You may obtain a copy of the License | |
| 7 | * at http://www.mozilla.org/MPL/ | |
| 8 | * | |
| 9 | * Software distributed under the License is distributed on an "AS IS" | |
| 10 | * basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See | |
| 11 | * the License for the specific language governing rights and | |
| 8bde7f77 | 12 | * limitations under the License. |
| 66fd3d1c WD |
13 | * |
| 14 | * The initial developer of the original code is David A. Hinds | |
| 15 | * <dahinds@users.sourceforge.net>. Portions created by David A. Hinds | |
| 16 | * are Copyright (C) 1999 David A. Hinds. All Rights Reserved. | |
| 17 | * | |
| 18 | * Alternatively, the contents of this file may be used under the | |
| 19 | * terms of the GNU General Public License version 2 (the "GPL"), in | |
| 20 | * which case the provisions of the GPL are applicable instead of the | |
| 21 | * above. If you wish to allow the use of your version of this file | |
| 22 | * only under the terms of the GPL and not to allow others to use | |
| 23 | * your version of this file under the MPL, indicate your decision by | |
| 24 | * deleting the provisions above and replace them with the notice and | |
| 25 | * other provisions required by the GPL. If you do not delete the | |
| 26 | * provisions above, a recipient may use your version of this file | |
| 27 | * under either the MPL or the GPL. | |
| 28 | */ | |
| 29 | ||
| 30 | #ifndef _LINUX_TI113X_H | |
| 31 | #define _LINUX_TI113X_H | |
| 32 | ||
| 33 | #ifndef PCI_VENDOR_ID_TI | |
| 34 | #define PCI_VENDOR_ID_TI 0x104c | |
| 35 | #endif | |
| 36 | ||
| 37 | #ifndef PCI_DEVICE_ID_TI_1130 | |
| 38 | #define PCI_DEVICE_ID_TI_1130 0xac12 | |
| 39 | #endif | |
| 40 | #ifndef PCI_DEVICE_ID_TI_1031 | |
| 41 | #define PCI_DEVICE_ID_TI_1031 0xac13 | |
| 42 | #endif | |
| 43 | #ifndef PCI_DEVICE_ID_TI_1131 | |
| 44 | #define PCI_DEVICE_ID_TI_1131 0xac15 | |
| 45 | #endif | |
| 46 | #ifndef PCI_DEVICE_ID_TI_1210 | |
| 47 | #define PCI_DEVICE_ID_TI_1210 0xac1a | |
| 48 | #endif | |
| 49 | #ifndef PCI_DEVICE_ID_TI_1211 | |
| 50 | #define PCI_DEVICE_ID_TI_1211 0xac1e | |
| 51 | #endif | |
| 52 | #ifndef PCI_DEVICE_ID_TI_1220 | |
| 53 | #define PCI_DEVICE_ID_TI_1220 0xac17 | |
| 54 | #endif | |
| 55 | #ifndef PCI_DEVICE_ID_TI_1221 | |
| 56 | #define PCI_DEVICE_ID_TI_1221 0xac19 | |
| 57 | #endif | |
| 58 | #ifndef PCI_DEVICE_ID_TI_1250A | |
| 59 | #define PCI_DEVICE_ID_TI_1250A 0xac16 | |
| 60 | #endif | |
| 61 | #ifndef PCI_DEVICE_ID_TI_1225 | |
| 62 | #define PCI_DEVICE_ID_TI_1225 0xac1c | |
| 63 | #endif | |
| 64 | #ifndef PCI_DEVICE_ID_TI_1251A | |
| 65 | #define PCI_DEVICE_ID_TI_1251A 0xac1d | |
| 66 | #endif | |
| 67 | #ifndef PCI_DEVICE_ID_TI_1251B | |
| 68 | #define PCI_DEVICE_ID_TI_1251B 0xac1f | |
| 69 | #endif | |
| 70 | #ifndef PCI_DEVICE_ID_TI_1410 | |
| 71 | #define PCI_DEVICE_ID_TI_1410 0xac50 | |
| 72 | #endif | |
| 73 | #ifndef PCI_DEVICE_ID_TI_1420 | |
| 74 | #define PCI_DEVICE_ID_TI_1420 0xac51 | |
| 75 | #endif | |
| 76 | #ifndef PCI_DEVICE_ID_TI_1450 | |
| 77 | #define PCI_DEVICE_ID_TI_1450 0xac1b | |
| 78 | #endif | |
| 79 | #ifndef PCI_DEVICE_ID_TI_1451 | |
| 80 | #define PCI_DEVICE_ID_TI_1451 0xac52 | |
| 81 | #endif | |
| 82 | #ifndef PCI_DEVICE_ID_TI_1510 | |
| 83 | #define PCI_DEVICE_ID_TI_1510 0xac56 | |
| 84 | #endif | |
| 85 | #ifndef PCI_DEVICE_ID_TI_4410 | |
| 86 | #define PCI_DEVICE_ID_TI_4410 0xac41 | |
| 87 | #endif | |
| 88 | #ifndef PCI_DEVICE_ID_TI_4450 | |
| 89 | #define PCI_DEVICE_ID_TI_4450 0xac40 | |
| 90 | #endif | |
| 91 | #ifndef PCI_DEVICE_ID_TI_4451 | |
| 92 | #define PCI_DEVICE_ID_TI_4451 0xac42 | |
| 93 | #endif | |
| 94 | ||
| 95 | /* Register definitions for TI 113X PCI-to-CardBus bridges */ | |
| 96 | ||
| 97 | /* System Control Register */ | |
| 98 | #define TI113X_SYSTEM_CONTROL 0x80 /* 32 bit */ | |
| 99 | #define TI113X_SCR_SMIROUTE 0x04000000 | |
| 100 | #define TI113X_SCR_SMISTATUS 0x02000000 | |
| 101 | #define TI113X_SCR_SMIENB 0x01000000 | |
| 102 | #define TI113X_SCR_VCCPROT 0x00200000 | |
| 103 | #define TI113X_SCR_REDUCEZV 0x00100000 | |
| 104 | #define TI113X_SCR_CDREQEN 0x00080000 | |
| 105 | #define TI113X_SCR_CDMACHAN 0x00070000 | |
| 106 | #define TI113X_SCR_SOCACTIVE 0x00002000 | |
| 107 | #define TI113X_SCR_PWRSTREAM 0x00000800 | |
| 108 | #define TI113X_SCR_DELAYUP 0x00000400 | |
| 109 | #define TI113X_SCR_DELAYDOWN 0x00000200 | |
| 110 | #define TI113X_SCR_INTERROGATE 0x00000100 | |
| 111 | #define TI113X_SCR_CLKRUN_SEL 0x00000080 | |
| 112 | #define TI113X_SCR_PWRSAVINGS 0x00000040 | |
| 113 | #define TI113X_SCR_SUBSYSRW 0x00000020 | |
| 114 | #define TI113X_SCR_CB_DPAR 0x00000010 | |
| 115 | #define TI113X_SCR_CDMA_EN 0x00000008 | |
| 116 | #define TI113X_SCR_ASYNC_IRQ 0x00000004 | |
| 117 | #define TI113X_SCR_KEEPCLK 0x00000002 | |
| 8bde7f77 | 118 | #define TI113X_SCR_CLKRUN_ENA 0x00000001 |
| 66fd3d1c WD |
119 | |
| 120 | #define TI122X_SCR_SER_STEP 0xc0000000 | |
| 121 | #define TI122X_SCR_INTRTIE 0x20000000 | |
| 122 | #define TI122X_SCR_P2CCLK 0x08000000 | |
| 123 | #define TI122X_SCR_CBRSVD 0x00400000 | |
| 124 | #define TI122X_SCR_MRBURSTDN 0x00008000 | |
| 125 | #define TI122X_SCR_MRBURSTUP 0x00004000 | |
| 126 | #define TI122X_SCR_RIMUX 0x00000001 | |
| 127 | ||
| 128 | /* Multimedia Control Register */ | |
| 129 | #define TI1250_MULTIMEDIA_CTL 0x84 /* 8 bit */ | |
| 130 | #define TI1250_MMC_ZVOUTEN 0x80 | |
| 131 | #define TI1250_MMC_PORTSEL 0x40 | |
| 132 | #define TI1250_MMC_ZVEN1 0x02 | |
| 133 | #define TI1250_MMC_ZVEN0 0x01 | |
| 134 | ||
| 135 | #define TI1250_GENERAL_STATUS 0x85 /* 8 bit */ | |
| 136 | #define TI1250_GPIO0_CONTROL 0x88 /* 8 bit */ | |
| 137 | #define TI1250_GPIO1_CONTROL 0x89 /* 8 bit */ | |
| 138 | #define TI1250_GPIO2_CONTROL 0x8a /* 8 bit */ | |
| 139 | #define TI1250_GPIO3_CONTROL 0x8b /* 8 bit */ | |
| 140 | #define TI12XX_IRQMUX 0x8c /* 32 bit */ | |
| 141 | ||
| 142 | /* Retry Status Register */ | |
| 143 | #define TI113X_RETRY_STATUS 0x90 /* 8 bit */ | |
| 144 | #define TI113X_RSR_PCIRETRY 0x80 | |
| 145 | #define TI113X_RSR_CBRETRY 0x40 | |
| 146 | #define TI113X_RSR_TEXP_CBB 0x20 | |
| 147 | #define TI113X_RSR_MEXP_CBB 0x10 | |
| 148 | #define TI113X_RSR_TEXP_CBA 0x08 | |
| 149 | #define TI113X_RSR_MEXP_CBA 0x04 | |
| 150 | #define TI113X_RSR_TEXP_PCI 0x02 | |
| 151 | #define TI113X_RSR_MEXP_PCI 0x01 | |
| 152 | ||
| 153 | /* Card Control Register */ | |
| 154 | #define TI113X_CARD_CONTROL 0x91 /* 8 bit */ | |
| 155 | #define TI113X_CCR_RIENB 0x80 | |
| 156 | #define TI113X_CCR_ZVENABLE 0x40 | |
| 157 | #define TI113X_CCR_PCI_IRQ_ENA 0x20 | |
| 158 | #define TI113X_CCR_PCI_IREQ 0x10 | |
| 159 | #define TI113X_CCR_PCI_CSC 0x08 | |
| 160 | #define TI113X_CCR_SPKROUTEN 0x02 | |
| 161 | #define TI113X_CCR_IFG 0x01 | |
| 162 | ||
| 163 | #define TI1220_CCR_PORT_SEL 0x20 | |
| 164 | #define TI122X_CCR_AUD2MUX 0x04 | |
| 165 | ||
| 166 | /* Device Control Register */ | |
| 167 | #define TI113X_DEVICE_CONTROL 0x92 /* 8 bit */ | |
| 168 | #define TI113X_DCR_5V_FORCE 0x40 | |
| 169 | #define TI113X_DCR_3V_FORCE 0x20 | |
| 170 | #define TI113X_DCR_IMODE_MASK 0x06 | |
| 171 | #define TI113X_DCR_IMODE_ISA 0x02 | |
| 172 | #define TI113X_DCR_IMODE_SERIAL 0x04 | |
| 173 | ||
| 174 | #define TI12XX_DCR_IMODE_PCI_ONLY 0x00 | |
| 175 | #define TI12XX_DCR_IMODE_ALL_SERIAL 0x06 | |
| 176 | ||
| 177 | /* Buffer Control Register */ | |
| 178 | #define TI113X_BUFFER_CONTROL 0x93 /* 8 bit */ | |
| 179 | #define TI113X_BCR_CB_READ_DEPTH 0x08 | |
| 180 | #define TI113X_BCR_CB_WRITE_DEPTH 0x04 | |
| 181 | #define TI113X_BCR_PCI_READ_DEPTH 0x02 | |
| 182 | #define TI113X_BCR_PCI_WRITE_DEPTH 0x01 | |
| 183 | ||
| 184 | /* Diagnostic Register */ | |
| 185 | #define TI1250_DIAGNOSTIC 0x93 /* 8 bit */ | |
| 186 | #define TI1250_DIAG_TRUE_VALUE 0x80 | |
| 187 | #define TI1250_DIAG_PCI_IREQ 0x40 | |
| 188 | #define TI1250_DIAG_PCI_CSC 0x20 | |
| 189 | #define TI1250_DIAG_ASYNC_CSC 0x01 | |
| 190 | ||
| 191 | /* DMA Registers */ | |
| 192 | #define TI113X_DMA_0 0x94 /* 32 bit */ | |
| 193 | #define TI113X_DMA_1 0x98 /* 32 bit */ | |
| 194 | ||
| 195 | /* ExCA IO offset registers */ | |
| 196 | #define TI113X_IO_OFFSET(map) (0x36+((map)<<1)) | |
| 197 | ||
| 198 | /* Data structure for tracking vendor-specific state */ | |
| 199 | typedef struct ti113x_state_t { | |
| 200 | u32 sysctl; /* TI113X_SYSTEM_CONTROL */ | |
| 201 | u8 cardctl; /* TI113X_CARD_CONTROL */ | |
| 202 | u8 devctl; /* TI113X_DEVICE_CONTROL */ | |
| 203 | u8 diag; /* TI1250_DIAGNOSTIC */ | |
| 204 | u32 irqmux; /* TI12XX_IRQMUX */ | |
| 205 | } ti113x_state_t; | |
| 206 | ||
| 207 | #define TI_PCIC_ID \ | |
| 208 | IS_TI1130, IS_TI1131, IS_TI1031, IS_TI1210, IS_TI1211, \ | |
| 209 | IS_TI1220, IS_TI1221, IS_TI1225, IS_TI1250A, IS_TI1251A, \ | |
| 210 | IS_TI1251B, IS_TI1410, IS_TI1420, IS_TI1450, IS_TI1451, \ | |
| 211 | IS_TI1510, IS_TI4410, IS_TI4450, IS_TI4451 | |
| 212 | ||
| 213 | #define TI_PCIC_INFO \ | |
| 214 | { "TI 1130", IS_TI|IS_CARDBUS, ID(TI, 1130) }, \ | |
| 215 | { "TI 1131", IS_TI|IS_CARDBUS, ID(TI, 1131) }, \ | |
| 216 | { "TI 1031", IS_TI|IS_CARDBUS, ID(TI, 1031) }, \ | |
| 217 | { "TI 1210", IS_TI|IS_CARDBUS, ID(TI, 1210) }, \ | |
| 218 | { "TI 1211", IS_TI|IS_CARDBUS, ID(TI, 1211) }, \ | |
| 219 | { "TI 1220", IS_TI|IS_CARDBUS, ID(TI, 1220) }, \ | |
| 220 | { "TI 1221", IS_TI|IS_CARDBUS, ID(TI, 1221) }, \ | |
| 221 | { "TI 1225", IS_TI|IS_CARDBUS, ID(TI, 1225) }, \ | |
| 222 | { "TI 1250A", IS_TI|IS_CARDBUS, ID(TI, 1250A) }, \ | |
| 223 | { "TI 1251A", IS_TI|IS_CARDBUS, ID(TI, 1251A) }, \ | |
| 224 | { "TI 1251B", IS_TI|IS_CARDBUS, ID(TI, 1251B) }, \ | |
| 225 | { "TI 1410", IS_TI|IS_CARDBUS, ID(TI, 1410) }, \ | |
| 226 | { "TI 1420", IS_TI|IS_CARDBUS, ID(TI, 1420) }, \ | |
| 227 | { "TI 1450", IS_TI|IS_CARDBUS, ID(TI, 1450) }, \ | |
| 228 | { "TI 1451", IS_TI|IS_CARDBUS, ID(TI, 1451) }, \ | |
| 229 | { "TI 1510", IS_TI|IS_CARDBUS, ID(TI, 1510) }, \ | |
| 230 | { "TI 4410", IS_TI|IS_CARDBUS, ID(TI, 4410) }, \ | |
| 231 | { "TI 4450", IS_TI|IS_CARDBUS, ID(TI, 4450) }, \ | |
| 232 | { "TI 4451", IS_TI|IS_CARDBUS, ID(TI, 4451) } | |
| 233 | ||
| 234 | #endif /* _LINUX_TI113X_H */ |