[people/ms/u-boot.git] / include / phy.h

/*
 * Copyright 2011 Freescale Semiconductor, Inc.
 *	Andy Fleming <afleming@gmail.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 *
 * This file pretty much stolen from Linux's mii.h/ethtool.h/phy.h
 */

#ifndef _PHY_H
#define _PHY_H

#include <linux/list.h>
#include <linux/mii.h>
#include <linux/ethtool.h>
#include <linux/mdio.h>

#define PHY_MAX_ADDR 32

#define PHY_DEFAULT_FEATURES	(SUPPORTED_Autoneg | \
				 SUPPORTED_TP | \
				 SUPPORTED_MII)

#define PHY_10BT_FEATURES	(SUPPORTED_10baseT_Half | \
				 SUPPORTED_10baseT_Full)

#define PHY_100BT_FEATURES	(SUPPORTED_100baseT_Half | \
				 SUPPORTED_100baseT_Full)

#define PHY_1000BT_FEATURES	(SUPPORTED_1000baseT_Half | \
				 SUPPORTED_1000baseT_Full)

#define PHY_BASIC_FEATURES	(PHY_10BT_FEATURES | \
				 PHY_100BT_FEATURES | \
				 PHY_DEFAULT_FEATURES)

#define PHY_GBIT_FEATURES	(PHY_BASIC_FEATURES | \
				 PHY_1000BT_FEATURES)

#define PHY_10G_FEATURES	(PHY_GBIT_FEATURES | \
				SUPPORTED_10000baseT_Full)

#ifndef PHY_ANEG_TIMEOUT
#define PHY_ANEG_TIMEOUT	4000
#endif


typedef enum {
	PHY_INTERFACE_MODE_MII,
	PHY_INTERFACE_MODE_GMII,
	PHY_INTERFACE_MODE_SGMII,
	PHY_INTERFACE_MODE_SGMII_2500,
	PHY_INTERFACE_MODE_QSGMII,
	PHY_INTERFACE_MODE_TBI,
	PHY_INTERFACE_MODE_RMII,
	PHY_INTERFACE_MODE_RGMII,
	PHY_INTERFACE_MODE_RGMII_ID,
	PHY_INTERFACE_MODE_RGMII_RXID,
	PHY_INTERFACE_MODE_RGMII_TXID,
	PHY_INTERFACE_MODE_RTBI,
	PHY_INTERFACE_MODE_XGMII,
	PHY_INTERFACE_MODE_NONE,	/* Must be last */

	PHY_INTERFACE_MODE_COUNT,
} phy_interface_t;

static const char *phy_interface_strings[] = {
	[PHY_INTERFACE_MODE_MII]		= "mii",
	[PHY_INTERFACE_MODE_GMII]		= "gmii",
	[PHY_INTERFACE_MODE_SGMII]		= "sgmii",
	[PHY_INTERFACE_MODE_SGMII_2500]		= "sgmii-2500",
	[PHY_INTERFACE_MODE_QSGMII]		= "qsgmii",
	[PHY_INTERFACE_MODE_TBI]		= "tbi",
	[PHY_INTERFACE_MODE_RMII]		= "rmii",
	[PHY_INTERFACE_MODE_RGMII]		= "rgmii",
	[PHY_INTERFACE_MODE_RGMII_ID]		= "rgmii-id",
	[PHY_INTERFACE_MODE_RGMII_RXID]		= "rgmii-rxid",
	[PHY_INTERFACE_MODE_RGMII_TXID]		= "rgmii-txid",
	[PHY_INTERFACE_MODE_RTBI]		= "rtbi",
	[PHY_INTERFACE_MODE_XGMII]		= "xgmii",
	[PHY_INTERFACE_MODE_NONE]		= "",
};

static inline const char *phy_string_for_interface(phy_interface_t i)
{
	/* Default to unknown */
	if (i > PHY_INTERFACE_MODE_NONE)
		i = PHY_INTERFACE_MODE_NONE;

	return phy_interface_strings[i];
}


struct phy_device;

#define MDIO_NAME_LEN 32

struct mii_dev {
	struct list_head link;
	char name[MDIO_NAME_LEN];
	void *priv;
	int (*read)(struct mii_dev *bus, int addr, int devad, int reg);
	int (*write)(struct mii_dev *bus, int addr, int devad, int reg,
			u16 val);
	int (*reset)(struct mii_dev *bus);
	struct phy_device *phymap[PHY_MAX_ADDR];
	u32 phy_mask;
};

/* struct phy_driver: a structure which defines PHY behavior
 *
 * uid will contain a number which represents the PHY.  During
 * startup, the driver will poll the PHY to find out what its
 * UID--as defined by registers 2 and 3--is.  The 32-bit result
 * gotten from the PHY will be masked to
 * discard any bits which may change based on revision numbers
 * unimportant to functionality
 *
 */
struct phy_driver {
	char *name;
	unsigned int uid;
	unsigned int mask;
	unsigned int mmds;

	u32 features;

	/* Called to do any driver startup necessities */
	/* Will be called during phy_connect */
	int (*probe)(struct phy_device *phydev);

	/* Called to configure the PHY, and modify the controller
	 * based on the results.  Should be called after phy_connect */
	int (*config)(struct phy_device *phydev);

	/* Called when starting up the controller */
	int (*startup)(struct phy_device *phydev);

	/* Called when bringing down the controller */
	int (*shutdown)(struct phy_device *phydev);

	int (*readext)(struct phy_device *phydev, int addr, int devad, int reg);
	int (*writeext)(struct phy_device *phydev, int addr, int devad, int reg,
			u16 val);
	struct list_head list;
};

struct phy_device {
	/* Information about the PHY type */
	/* And management functions */
	struct mii_dev *bus;
	struct phy_driver *drv;
	void *priv;

#ifdef CONFIG_DM_ETH
	struct udevice *dev;
#else
	struct eth_device *dev;
#endif

	/* forced speed & duplex (no autoneg)
	 * partner speed & duplex & pause (autoneg)
	 */
	int speed;
	int duplex;

	/* The most recently read link state */
	int link;
	int port;
	phy_interface_t interface;

	u32 advertising;
	u32 supported;
	u32 mmds;

	int autoneg;
	int addr;
	int pause;
	int asym_pause;
	u32 phy_id;
	u32 flags;
};

struct fixed_link {
	int phy_id;
	int duplex;
	int link_speed;
	int pause;
	int asym_pause;
};

static inline int phy_read(struct phy_device *phydev, int devad, int regnum)
{
	struct mii_dev *bus = phydev->bus;

	return bus->read(bus, phydev->addr, devad, regnum);
}

static inline int phy_write(struct phy_device *phydev, int devad, int regnum,
			u16 val)
{
	struct mii_dev *bus = phydev->bus;

	return bus->write(bus, phydev->addr, devad, regnum, val);
}

#ifdef CONFIG_PHYLIB_10G
extern struct phy_driver gen10g_driver;

/* For now, XGMII is the only 10G interface */
static inline int is_10g_interface(phy_interface_t interface)
{
	return interface == PHY_INTERFACE_MODE_XGMII;
}

#endif

int phy_init(void);
int phy_reset(struct phy_device *phydev);
struct phy_device *phy_find_by_mask(struct mii_dev *bus, unsigned phy_mask,
		phy_interface_t interface);
#ifdef CONFIG_DM_ETH
void phy_connect_dev(struct phy_device *phydev, struct udevice *dev);
struct phy_device *phy_connect(struct mii_dev *bus, int addr,
				struct udevice *dev,
				phy_interface_t interface);
#else
void phy_connect_dev(struct phy_device *phydev, struct eth_device *dev);
struct phy_device *phy_connect(struct mii_dev *bus, int addr,
				struct eth_device *dev,
				phy_interface_t interface);
#endif
int phy_startup(struct phy_device *phydev);
int phy_config(struct phy_device *phydev);
int phy_shutdown(struct phy_device *phydev);
int phy_register(struct phy_driver *drv);
int genphy_config_aneg(struct phy_device *phydev);
int genphy_restart_aneg(struct phy_device *phydev);
int genphy_update_link(struct phy_device *phydev);
int genphy_parse_link(struct phy_device *phydev);
int genphy_config(struct phy_device *phydev);
int genphy_startup(struct phy_device *phydev);
int genphy_shutdown(struct phy_device *phydev);
int gen10g_config(struct phy_device *phydev);
int gen10g_startup(struct phy_device *phydev);
int gen10g_shutdown(struct phy_device *phydev);
int gen10g_discover_mmds(struct phy_device *phydev);

int phy_aquantia_init(void);
int phy_atheros_init(void);
int phy_broadcom_init(void);
int phy_cortina_init(void);
int phy_davicom_init(void);
int phy_et1011c_init(void);
int phy_lxt_init(void);
int phy_marvell_init(void);
int phy_micrel_init(void);
int phy_natsemi_init(void);
int phy_realtek_init(void);
int phy_smsc_init(void);
int phy_teranetics_init(void);
int phy_ti_init(void);
int phy_vitesse_init(void);

int board_phy_config(struct phy_device *phydev);
int get_phy_id(struct mii_dev *bus, int addr, int devad, u32 *phy_id);

/**
 * phy_get_interface_by_name() - Look up a PHY interface name
 *
 * @str:	PHY interface name, e.g. "mii"
 * @return PHY_INTERFACE_MODE_... value, or -1 if not found
 */
int phy_get_interface_by_name(const char *str);

/* PHY UIDs for various PHYs that are referenced in external code */
#define PHY_UID_CS4340  0x13e51002
#define PHY_UID_TN2020	0x00a19410

#endif
Commit	Line	Data
5f184715 AF	1	/*
5f184715 AF	2	* Copyright 2011 Freescale Semiconductor, Inc.
b21f87a3	3	* Andy Fleming <afleming@gmail.com>
5f184715	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
5f184715 AF	6	*
	7	* This file pretty much stolen from Linux's mii.h/ethtool.h/phy.h
	8	*/
	9
	10	#ifndef _PHY_H
	11	#define _PHY_H
	12
	13	#include <linux/list.h>
	14	#include <linux/mii.h>
	15	#include <linux/ethtool.h>
	16	#include <linux/mdio.h>
	17
	18	#define PHY_MAX_ADDR 32
	19
4dae610b	20	#define PHY_DEFAULT_FEATURES (SUPPORTED_Autoneg \| \
5f184715 AF	21	SUPPORTED_TP \| \
	22	SUPPORTED_MII)
	23
4dae610b FF	24	#define PHY_10BT_FEATURES (SUPPORTED_10baseT_Half \| \
	25	SUPPORTED_10baseT_Full)
	26
	27	#define PHY_100BT_FEATURES (SUPPORTED_100baseT_Half \| \
	28	SUPPORTED_100baseT_Full)
	29
	30	#define PHY_1000BT_FEATURES (SUPPORTED_1000baseT_Half \| \
5f184715 AF	31	SUPPORTED_1000baseT_Full)
5f184715 AF	32
4dae610b FF	33	#define PHY_BASIC_FEATURES (PHY_10BT_FEATURES \| \
	34	PHY_100BT_FEATURES \| \
	35	PHY_DEFAULT_FEATURES)
	36
	37	#define PHY_GBIT_FEATURES (PHY_BASIC_FEATURES \| \
	38	PHY_1000BT_FEATURES)
	39
5f184715 AF	40	#define PHY_10G_FEATURES (PHY_GBIT_FEATURES \| \
	41	SUPPORTED_10000baseT_Full)
	42
4fb3f0c8	43	#ifndef PHY_ANEG_TIMEOUT
5f184715	44	#define PHY_ANEG_TIMEOUT 4000
4fb3f0c8	45	#endif
5f184715 AF	46
	47
	48	typedef enum {
	49	PHY_INTERFACE_MODE_MII,
	50	PHY_INTERFACE_MODE_GMII,
	51	PHY_INTERFACE_MODE_SGMII,
c35f8693	52	PHY_INTERFACE_MODE_SGMII_2500,
7794b1a7	53	PHY_INTERFACE_MODE_QSGMII,
5f184715 AF	54	PHY_INTERFACE_MODE_TBI,
	55	PHY_INTERFACE_MODE_RMII,
	56	PHY_INTERFACE_MODE_RGMII,
	57	PHY_INTERFACE_MODE_RGMII_ID,
	58	PHY_INTERFACE_MODE_RGMII_RXID,
	59	PHY_INTERFACE_MODE_RGMII_TXID,
	60	PHY_INTERFACE_MODE_RTBI,
	61	PHY_INTERFACE_MODE_XGMII,
c74c8e66 SG	62	PHY_INTERFACE_MODE_NONE, /* Must be last */
	63
	64	PHY_INTERFACE_MODE_COUNT,
5f184715 AF	65	} phy_interface_t;
	66
	67	static const char *phy_interface_strings[] = {
	68	[PHY_INTERFACE_MODE_MII] = "mii",
	69	[PHY_INTERFACE_MODE_GMII] = "gmii",
	70	[PHY_INTERFACE_MODE_SGMII] = "sgmii",
c35f8693	71	[PHY_INTERFACE_MODE_SGMII_2500] = "sgmii-2500",
7794b1a7	72	[PHY_INTERFACE_MODE_QSGMII] = "qsgmii",
5f184715 AF	73	[PHY_INTERFACE_MODE_TBI] = "tbi",
	74	[PHY_INTERFACE_MODE_RMII] = "rmii",
	75	[PHY_INTERFACE_MODE_RGMII] = "rgmii",
	76	[PHY_INTERFACE_MODE_RGMII_ID] = "rgmii-id",
	77	[PHY_INTERFACE_MODE_RGMII_RXID] = "rgmii-rxid",
	78	[PHY_INTERFACE_MODE_RGMII_TXID] = "rgmii-txid",
	79	[PHY_INTERFACE_MODE_RTBI] = "rtbi",
	80	[PHY_INTERFACE_MODE_XGMII] = "xgmii",
	81	[PHY_INTERFACE_MODE_NONE] = "",
	82	};
	83
	84	static inline const char *phy_string_for_interface(phy_interface_t i)
	85	{
	86	/* Default to unknown */
	87	if (i > PHY_INTERFACE_MODE_NONE)
	88	i = PHY_INTERFACE_MODE_NONE;
	89
	90	return phy_interface_strings[i];
	91	}
	92
	93
	94	struct phy_device;
	95
	96	#define MDIO_NAME_LEN 32
	97
	98	struct mii_dev {
	99	struct list_head link;
	100	char name[MDIO_NAME_LEN];
	101	void *priv;
	102	int (read)(struct mii_dev bus, int addr, int devad, int reg);
	103	int (write)(struct mii_dev bus, int addr, int devad, int reg,
	104	u16 val);
	105	int (reset)(struct mii_dev bus);
	106	struct phy_device *phymap[PHY_MAX_ADDR];
	107	u32 phy_mask;
	108	};
	109
	110	/* struct phy_driver: a structure which defines PHY behavior
	111	*
	112	* uid will contain a number which represents the PHY. During
	113	* startup, the driver will poll the PHY to find out what its
	114	* UID--as defined by registers 2 and 3--is. The 32-bit result
	115	* gotten from the PHY will be masked to
	116	* discard any bits which may change based on revision numbers
	117	* unimportant to functionality
	118	*
	119	*/
	120	struct phy_driver {
	121	char *name;
	122	unsigned int uid;
	123	unsigned int mask;
	124	unsigned int mmds;
	125
	126	u32 features;
	127
	128	/* Called to do any driver startup necessities */
	129	/* Will be called during phy_connect */
	130	int (probe)(struct phy_device phydev);
	131
	132	/* Called to configure the PHY, and modify the controller
	133	* based on the results. Should be called after phy_connect */
	134	int (config)(struct phy_device phydev);
	135
	136	/* Called when starting up the controller */
137	int (startup)(struct phy_device phydev);
138
139	/* Called when bringing down the controller */
140	int (shutdown)(struct phy_device phydev);
141
b71841b9 SB	142	int (readext)(struct phy_device phydev, int addr, int devad, int reg);
	143	int (writeext)(struct phy_device phydev, int addr, int devad, int reg,
	144	u16 val);
5f184715 AF	145	struct list_head list;
	146	};
	147
	148	struct phy_device {
	149	/* Information about the PHY type */
	150	/* And management functions */
	151	struct mii_dev *bus;
	152	struct phy_driver *drv;
	153	void *priv;
	154
c74c8e66 SG	155	#ifdef CONFIG_DM_ETH
	156	struct udevice *dev;
	157	#else
5f184715	158	struct eth_device *dev;
c74c8e66	159	#endif
5f184715 AF	160
	161	/* forced speed & duplex (no autoneg)
	162	* partner speed & duplex & pause (autoneg)
	163	*/
	164	int speed;
	165	int duplex;
	166
	167	/* The most recently read link state */
	168	int link;
	169	int port;
	170	phy_interface_t interface;
	171
	172	u32 advertising;
	173	u32 supported;
	174	u32 mmds;
	175
	176	int autoneg;
	177	int addr;
	178	int pause;
	179	int asym_pause;
	180	u32 phy_id;
	181	u32 flags;
	182	};
	183
f55a776c SX	184	struct fixed_link {
	185	int phy_id;
	186	int duplex;
	187	int link_speed;
	188	int pause;
	189	int asym_pause;
	190	};
	191
5f184715 AF	192	static inline int phy_read(struct phy_device *phydev, int devad, int regnum)
	193	{
	194	struct mii_dev *bus = phydev->bus;
	195
	196	return bus->read(bus, phydev->addr, devad, regnum);
	197	}
	198
	199	static inline int phy_write(struct phy_device *phydev, int devad, int regnum,
	200	u16 val)
	201	{
	202	struct mii_dev *bus = phydev->bus;
	203
	204	return bus->write(bus, phydev->addr, devad, regnum, val);
	205	}
	206
	207	#ifdef CONFIG_PHYLIB_10G
	208	extern struct phy_driver gen10g_driver;
	209
	210	/* For now, XGMII is the only 10G interface */
	211	static inline int is_10g_interface(phy_interface_t interface)
	212	{
	213	return interface == PHY_INTERFACE_MODE_XGMII;
	214	}
	215
	216	#endif
	217
	218	int phy_init(void);
	219	int phy_reset(struct phy_device *phydev);
1adb406b TK	220	struct phy_device phy_find_by_mask(struct mii_dev bus, unsigned phy_mask,
1adb406b TK	221	phy_interface_t interface);
c74c8e66 SG	222	#ifdef CONFIG_DM_ETH
	223	void phy_connect_dev(struct phy_device phydev, struct udevice dev);
	224	struct phy_device phy_connect(struct mii_dev bus, int addr,
	225	struct udevice *dev,
	226	phy_interface_t interface);
	227	#else
1adb406b	228	void phy_connect_dev(struct phy_device phydev, struct eth_device dev);
5f184715 AF	229	struct phy_device phy_connect(struct mii_dev bus, int addr,
	230	struct eth_device *dev,
	231	phy_interface_t interface);
c74c8e66	232	#endif
5f184715 AF	233	int phy_startup(struct phy_device *phydev);
	234	int phy_config(struct phy_device *phydev);
	235	int phy_shutdown(struct phy_device *phydev);
	236	int phy_register(struct phy_driver *drv);
	237	int genphy_config_aneg(struct phy_device *phydev);
8682aba7	238	int genphy_restart_aneg(struct phy_device *phydev);
5f184715	239	int genphy_update_link(struct phy_device *phydev);
e2043f5c	240	int genphy_parse_link(struct phy_device *phydev);
5f184715 AF	241	int genphy_config(struct phy_device *phydev);
	242	int genphy_startup(struct phy_device *phydev);
	243	int genphy_shutdown(struct phy_device *phydev);
	244	int gen10g_config(struct phy_device *phydev);
	245	int gen10g_startup(struct phy_device *phydev);
	246	int gen10g_shutdown(struct phy_device *phydev);
	247	int gen10g_discover_mmds(struct phy_device *phydev);
	248
f7c38cf8	249	int phy_aquantia_init(void);
9082eeac AF	250	int phy_atheros_init(void);
9082eeac AF	251	int phy_broadcom_init(void);
9b18e519	252	int phy_cortina_init(void);
9082eeac	253	int phy_davicom_init(void);
f485c8a3	254	int phy_et1011c_init(void);
9082eeac AF	255	int phy_lxt_init(void);
	256	int phy_marvell_init(void);
	257	int phy_micrel_init(void);
	258	int phy_natsemi_init(void);
	259	int phy_realtek_init(void);
b6abf555	260	int phy_smsc_init(void);
9082eeac	261	int phy_teranetics_init(void);
721aed79	262	int phy_ti_init(void);
9082eeac	263	int phy_vitesse_init(void);
a836626c	264
2fb63964	265	int board_phy_config(struct phy_device *phydev);
5707d5ff	266	int get_phy_id(struct mii_dev bus, int addr, int devad, u32 phy_id);
2fb63964	267
c74c8e66 SG	268	/**
	269	* phy_get_interface_by_name() - Look up a PHY interface name
	270	*
	271	* @str: PHY interface name, e.g. "mii"
	272	* @return PHY_INTERFACE_MODE_... value, or -1 if not found
	273	*/
	274	int phy_get_interface_by_name(const char *str);
	275
a836626c	276	/* PHY UIDs for various PHYs that are referenced in external code */
9b18e519	277	#define PHY_UID_CS4340 0x13e51002
a836626c TT	278	#define PHY_UID_TN2020 0x00a19410
a836626c TT	279
5f184715	280	#endif